1//===-- X86InstrUtils.td - X86 Instruction Utilities --------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file provides utilities for simplifying the instruction definitions. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Classes for setting the fields of X86Inst 15//===----------------------------------------------------------------------===// 16 17// Prefix byte classes which are used to indicate to the ad-hoc machine code 18// emitter that various prefix bytes are required. 19class OpSize16 { OperandSize OpSize = OpSize16; } 20class OpSize32 { OperandSize OpSize = OpSize32; } 21class AdSize16 { AddressSize AdSize = AdSize16; } 22class AdSize32 { AddressSize AdSize = AdSize32; } 23class AdSize64 { AddressSize AdSize = AdSize64; } 24class REX_W { bit hasREX_W = 1; } 25class LOCK { bit hasLockPrefix = 1; } 26class REP { bit hasREPPrefix = 1; } 27class TB { Map OpMap = TB; } 28class T8 { Map OpMap = T8; } 29class TA { Map OpMap = TA; } 30class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; } 31class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; } 32class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; } 33class ThreeDNow { Map OpMap = ThreeDNow; } 34class T_MAP4 { Map OpMap = T_MAP4; } 35class T_MAP4PS : T_MAP4 { Prefix OpPrefix = PS; } // none 36class T_MAP4PD : T_MAP4 { Prefix OpPrefix = PD; } // 0x66 37class T_MAP4XS : T_MAP4 { Prefix OpPrefix = XS; } // 0xF3 38class T_MAP4XD : T_MAP4 { Prefix OpPrefix = XD; } // 0xF2 39class T_MAP5 { Map OpMap = T_MAP5; } 40class T_MAP5PS : T_MAP5 { Prefix OpPrefix = PS; } // none 41class T_MAP5PD : T_MAP5 { Prefix OpPrefix = PD; } // 0x66 42class T_MAP5XS : T_MAP5 { Prefix OpPrefix = XS; } // 0xF3 43class T_MAP5XD : T_MAP5 { Prefix OpPrefix = XD; } // 0xF2 44class T_MAP6 { Map OpMap = T_MAP6; } 45class T_MAP6PS : T_MAP6 { Prefix OpPrefix = PS; } 46class T_MAP6PD : T_MAP6 { Prefix OpPrefix = PD; } 47class T_MAP6XS : T_MAP6 { Prefix OpPrefix = XS; } 48class T_MAP6XD : T_MAP6 { Prefix OpPrefix = XD; } 49class T_MAP7 { Map OpMap = T_MAP7; } 50class T_MAP7XS : T_MAP7 { Prefix OpPrefix = XS; } // 0xF3 51class T_MAP7XD : T_MAP7 { Prefix OpPrefix = XD; } // 0xF2 52class OBXS { Prefix OpPrefix = XS; } 53class PS : TB { Prefix OpPrefix = PS; } 54class PD : TB { Prefix OpPrefix = PD; } 55class XD : TB { Prefix OpPrefix = XD; } 56class XS : TB { Prefix OpPrefix = XS; } 57class T8PS : T8 { Prefix OpPrefix = PS; } 58class T8PD : T8 { Prefix OpPrefix = PD; } 59class T8XD : T8 { Prefix OpPrefix = XD; } 60class T8XS : T8 { Prefix OpPrefix = XS; } 61class TAPS : TA { Prefix OpPrefix = PS; } 62class TAPD : TA { Prefix OpPrefix = PD; } 63class TAXD : TA { Prefix OpPrefix = XD; } 64class TAXS : TA { Prefix OpPrefix = XS; } 65class VEX { Encoding OpEnc = EncVEX; } 66class WIG { bit IgnoresW = 1; } 67// Special version of REX_W that can be changed to VEX.W==0 for EVEX2VEX. 68class VEX_W1X { bit hasREX_W = 1; bit EVEX_W1_VEX_W0 = 1; } 69class VEX_4V : VEX { bit hasVEX_4V = 1; } 70class VEX_L { bit hasVEX_L = 1; } 71class VEX_LIG { bit ignoresVEX_L = 1; } 72class EVEX { Encoding OpEnc = EncEVEX; } 73class EVEX_4V : EVEX { bit hasVEX_4V = 1; } 74class EVEX_K { bit hasEVEX_K = 1; } 75class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; } 76class EVEX_B { bit hasEVEX_B = 1; } 77class EVEX_RC { bit hasEVEX_RC = 1; } 78class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; } 79class EVEX_V256 { bit hasEVEX_L2 = 0; bit hasVEX_L = 1; } 80class EVEX_V128 { bit hasEVEX_L2 = 0; bit hasVEX_L = 0; } 81class NOTRACK { bit hasNoTrackPrefix = 1; } 82class SIMD_EXC { list<Register> Uses = [MXCSR]; bit mayRaiseFPException = 1; } 83// Specify AVX512 8-bit compressed displacement encoding based on the vector 84// element size in bits (8, 16, 32, 64) and the CDisp8 form. 85class EVEX_CD8<int esize, CD8VForm form> { 86 int CD8_EltSize = !srl(esize, 3); 87 bits<3> CD8_Form = form.Value; 88} 89class EVEX_NoCD8 : EVEX { bits<7> CD8_Scale = 0; } 90class XOP { Encoding OpEnc = EncXOP; } 91class XOP_4V : XOP { bit hasVEX_4V = 1; } 92class EVEX2VEXOverride<string VEXInstrName> { 93 string EVEX2VEXOverride = VEXInstrName; 94} 95class AVX512BIi8Base : PD { 96 Domain ExeDomain = SSEPackedInt; 97 ImmType ImmT = Imm8; 98} 99class AVX512XSIi8Base : XS { 100 Domain ExeDomain = SSEPackedInt; 101 ImmType ImmT = Imm8; 102} 103class AVX512XDIi8Base : XD { 104 Domain ExeDomain = SSEPackedInt; 105 ImmType ImmT = Imm8; 106} 107class AVX512PSIi8Base : PS { 108 Domain ExeDomain = SSEPackedSingle; 109 ImmType ImmT = Imm8; 110} 111class AVX512PDIi8Base : PD { 112 Domain ExeDomain = SSEPackedDouble; 113 ImmType ImmT = Imm8; 114} 115class NotEVEX2VEXConvertible { bit notEVEX2VEXConvertible = 1; } 116class ExplicitREX2Prefix { ExplicitOpPrefix explicitOpPrefix = ExplicitREX2; } 117class ExplicitVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitVEX; } 118class ExplicitEVEXPrefix { ExplicitOpPrefix explicitOpPrefix = ExplicitEVEX; } 119 120// SchedModel info for instruction that loads one value and gets the second 121// (and possibly third) value from a register. 122// This is used for instructions that put the memory operands before other 123// uses. 124class SchedLoadReg<X86FoldableSchedWrite Sched> : Sched<[Sched.Folded, 125 // Memory operand. 126 ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault, 127 // Register reads (implicit or explicit). 128 Sched.ReadAfterFold, Sched.ReadAfterFold]>; 129 130//===----------------------------------------------------------------------===// 131// X86 Type infomation definitions 132//===----------------------------------------------------------------------===// 133 134/// X86TypeInfo - This is a bunch of information that describes relevant X86 135/// information about value types. For example, it can tell you what the 136/// register class and preferred load to use. 137class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass, 138 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind, 139 Operand immoperand, SDPatternOperator immoperator, 140 SDPatternOperator immnosuoperator, Operand imm8operand, 141 SDPatternOperator imm8operator, SDPatternOperator imm8nosuoperator, 142 bit hasOddOpcode, OperandSize opSize, 143 bit hasREX_W> { 144 /// VT - This is the value type itself. 145 ValueType VT = vt; 146 147 /// InstrSuffix - This is the suffix used on instructions with this type. For 148 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q". 149 string InstrSuffix = instrsuffix; 150 151 /// RegClass - This is the register class associated with this type. For 152 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64. 153 RegisterClass RegClass = regclass; 154 155 /// LoadNode - This is the load node associated with this type. For 156 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64. 157 PatFrag LoadNode = loadnode; 158 159 /// MemOperand - This is the memory operand associated with this type. For 160 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem. 161 X86MemOperand MemOperand = memoperand; 162 163 /// ImmEncoding - This is the encoding of an immediate of this type. For 164 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32 165 /// since the immediate fields of i64 instructions is a 32-bit sign extended 166 /// value. 167 ImmType ImmEncoding = immkind; 168 169 /// ImmOperand - This is the operand kind of an immediate of this type. For 170 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 -> 171 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign 172 /// extended value. 173 Operand ImmOperand = immoperand; 174 175 /// ImmOperator - This is the operator that should be used to match an 176 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32). 177 SDPatternOperator ImmOperator = immoperator; 178 179 SDPatternOperator ImmNoSuOperator = immnosuoperator; 180 181 /// Imm8Operand - This is the operand kind to use for an imm8 of this type. 182 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is 183 /// only used for instructions that have a sign-extended imm8 field form. 184 Operand Imm8Operand = imm8operand; 185 186 /// Imm8Operator - This is the operator that should be used to match an 8-bit 187 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8). 188 SDPatternOperator Imm8Operator = imm8operator; 189 190 SDPatternOperator Imm8NoSuOperator = imm8nosuoperator; 191 192 /// HasOddOpcode - This bit is true if the instruction should have an odd (as 193 /// opposed to even) opcode. Operations on i8 are usually even, operations on 194 /// other datatypes are odd. 195 bit HasOddOpcode = hasOddOpcode; 196 197 /// OpSize - Selects whether the instruction needs a 0x66 prefix based on 198 /// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this 199 /// to Opsize16. i32 sets this to OpSize32. 200 OperandSize OpSize = opSize; 201 202 /// HasREX_W - This bit is set to true if the instruction should have 203 /// the 0x40 REX prefix. This is set for i64 types. 204 bit HasREX_W = hasREX_W; 205} 206 207def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">; 208 209def Xi8 : X86TypeInfo<i8, "b", GR8, loadi8, i8mem, Imm8, i8imm, 210 imm_su, imm, i8imm, invalid_node, invalid_node, 211 0, OpSizeFixed, 0>; 212def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, Imm16, i16imm, 213 imm_su, imm, i16i8imm, i16immSExt8_su, i16immSExt8, 214 1, OpSize16, 0>; 215def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, Imm32, i32imm, 216 imm_su, imm, i32i8imm, i32immSExt8_su, i32immSExt8, 217 1, OpSize32, 0>; 218def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, Imm32S, i64i32imm, 219 i64immSExt32_su, i64immSExt32, i64i8imm, i64immSExt8_su, 220 i64immSExt8, 1, OpSizeFixed, 1>; 221 222// Group template arguments that can be derived from the vector type (EltNum x 223// EltVT). These are things like the register class for the writemask, etc. 224// The idea is to pass one of these as the template argument rather than the 225// individual arguments. 226// The template is also used for scalar types, in this case numelts is 1. 227class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc, 228 string suffix = ""> { 229 RegisterClass RC = rc; 230 ValueType EltVT = eltvt; 231 int NumElts = numelts; 232 233 // Corresponding mask register class. 234 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts); 235 236 // Corresponding mask register pair class. 237 RegisterOperand KRPC = !if (!gt(NumElts, 16), ?, 238 !cast<RegisterOperand>("VK" # NumElts # "Pair")); 239 240 // Corresponding write-mask register class. 241 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM"); 242 243 // The mask VT. 244 ValueType KVT = !cast<ValueType>("v" # NumElts # "i1"); 245 246 // Suffix used in the instruction mnemonic. 247 string Suffix = suffix; 248 249 // VTName is a string name for vector VT. For vector types it will be 250 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32 251 // It is a little bit complex for scalar types, where NumElts = 1. 252 // In this case we build v4f32 or v2f64 253 string VTName = "v" # !if (!eq (NumElts, 1), 254 !if (!eq (EltVT.Size, 16), 8, 255 !if (!eq (EltVT.Size, 32), 4, 256 !if (!eq (EltVT.Size, 64), 2, NumElts))), NumElts) # EltVT; 257 258 // The vector VT. 259 ValueType VT = !cast<ValueType>(VTName); 260 261 string EltTypeName = !cast<string>(EltVT); 262 // Size of the element type in bits, e.g. 32 for v16i32. 263 string EltSizeName = !subst("i", "", !subst("f", "", !subst("b", "", EltTypeName))); 264 int EltSize = EltVT.Size; 265 266 // "i" for integer types and "f" for floating-point types 267 string TypeVariantName = !subst("b", "", !subst(EltSizeName, "", EltTypeName)); 268 269 // Size of RC in bits, e.g. 512 for VR512. 270 int Size = VT.Size; 271 272 // The corresponding memory operand, e.g. i512mem for VR512. 273 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem"); 274 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(!subst("b", "", EltTypeName) # "mem"); 275 // FP scalar memory operand for intrinsics - ssmem/sdmem. 276 Operand IntScalarMemOp = !if (!eq (EltTypeName, "f16"), !cast<Operand>("shmem"), 277 !if (!eq (EltTypeName, "bf16"), !cast<Operand>("shmem"), 278 !if (!eq (EltTypeName, "f32"), !cast<Operand>("ssmem"), 279 !if (!eq (EltTypeName, "f64"), !cast<Operand>("sdmem"), ?)))); 280 281 // Load patterns 282 PatFrag LdFrag = !cast<PatFrag>("load" # VTName); 283 284 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" # VTName); 285 286 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # !subst("b", "", EltTypeName)); 287 PatFrag BroadcastLdFrag = !cast<PatFrag>("X86VBroadcastld" # EltSizeName); 288 289 PatFrags ScalarIntMemFrags = !if (!eq (EltTypeName, "f16"), !cast<PatFrags>("sse_load_f16"), 290 !if (!eq (EltTypeName, "bf16"), !cast<PatFrags>("sse_load_f16"), 291 !if (!eq (EltTypeName, "f32"), !cast<PatFrags>("sse_load_f32"), 292 !if (!eq (EltTypeName, "f64"), !cast<PatFrags>("sse_load_f64"), ?)))); 293 294 // The string to specify embedded broadcast in assembly. 295 string BroadcastStr = "{1to" # NumElts # "}"; 296 297 // 8-bit compressed displacement tuple/subvector format. This is only 298 // defined for NumElts <= 8. 299 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0), 300 !cast<CD8VForm>("CD8VT" # NumElts), ?); 301 302 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm, 303 !if (!eq (Size, 256), sub_ymm, ?)); 304 305 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle, 306 !if (!eq (EltTypeName, "f64"), SSEPackedDouble, 307 !if (!eq (EltTypeName, "f16"), SSEPackedSingle, // FIXME? 308 !if (!eq (EltTypeName, "bf16"), SSEPackedSingle, // FIXME? 309 SSEPackedInt)))); 310 311 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, 312 !if (!eq (EltTypeName, "f16"), FR16X, 313 !if (!eq (EltTypeName, "bf16"), FR16X, 314 FR64X))); 315 316 dag ImmAllZerosV = (VT immAllZerosV); 317 318 string ZSuffix = !if (!eq (Size, 128), "Z128", 319 !if (!eq (Size, 256), "Z256", "Z")); 320} 321 322def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">; 323def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">; 324def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">; 325def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">; 326def v32f16_info : X86VectorVTInfo<32, f16, VR512, "ph">; 327def v32bf16_info: X86VectorVTInfo<32, bf16, VR512, "pbf">; 328def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">; 329def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">; 330 331// "x" in v32i8x_info means RC = VR256X 332def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">; 333def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">; 334def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">; 335def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">; 336def v16f16x_info : X86VectorVTInfo<16, f16, VR256X, "ph">; 337def v16bf16x_info: X86VectorVTInfo<16, bf16, VR256X, "pbf">; 338def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">; 339def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">; 340 341def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">; 342def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">; 343def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">; 344def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">; 345def v8f16x_info : X86VectorVTInfo<8, f16, VR128X, "ph">; 346def v8bf16x_info : X86VectorVTInfo<8, bf16, VR128X, "pbf">; 347def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">; 348def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">; 349 350// We map scalar types to the smallest (128-bit) vector type 351// with the appropriate element type. This allows to use the same masking logic. 352def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">; 353def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">; 354def f16x_info : X86VectorVTInfo<1, f16, VR128X, "sh">; 355def bf16x_info : X86VectorVTInfo<1, bf16, VR128X, "sbf">; 356def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">; 357def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">; 358 359class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256, 360 X86VectorVTInfo i128> { 361 X86VectorVTInfo info512 = i512; 362 X86VectorVTInfo info256 = i256; 363 X86VectorVTInfo info128 = i128; 364} 365 366def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info, 367 v16i8x_info>; 368def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info, 369 v8i16x_info>; 370def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info, 371 v4i32x_info>; 372def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info, 373 v2i64x_info>; 374def avx512vl_f16_info : AVX512VLVectorVTInfo<v32f16_info, v16f16x_info, 375 v8f16x_info>; 376def avx512vl_bf16_info : AVX512VLVectorVTInfo<v32bf16_info, v16bf16x_info, 377 v8bf16x_info>; 378def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info, 379 v4f32x_info>; 380def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info, 381 v2f64x_info>; 382 383class X86KVectorVTInfo<RegisterClass _krc, RegisterClass _krcwm, 384 ValueType _vt> { 385 RegisterClass KRC = _krc; 386 RegisterClass KRCWM = _krcwm; 387 ValueType KVT = _vt; 388} 389 390def v1i1_info : X86KVectorVTInfo<VK1, VK1WM, v1i1>; 391def v2i1_info : X86KVectorVTInfo<VK2, VK2WM, v2i1>; 392def v4i1_info : X86KVectorVTInfo<VK4, VK4WM, v4i1>; 393def v8i1_info : X86KVectorVTInfo<VK8, VK8WM, v8i1>; 394def v16i1_info : X86KVectorVTInfo<VK16, VK16WM, v16i1>; 395def v32i1_info : X86KVectorVTInfo<VK32, VK32WM, v32i1>; 396def v64i1_info : X86KVectorVTInfo<VK64, VK64WM, v64i1>; 397 398// Subclasses of X86Inst 399class PseudoI<dag oops, dag iops, list<dag> pattern> 400 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> { 401 let Pattern = pattern; 402} 403 404class I<bits<8> o, Format f, dag outs, dag ins, string asm, 405 list<dag> pattern, Domain d = GenericDomain> 406 : X86Inst<o, f, NoImm, outs, ins, asm, d> { 407 let Pattern = pattern; 408} 409class Ii8<bits<8> o, Format f, dag outs, dag ins, string asm, 410 list<dag> pattern, Domain d = GenericDomain> 411 : X86Inst<o, f, Imm8, outs, ins, asm, d> { 412 let Pattern = pattern; 413} 414class Ii8Reg<bits<8> o, Format f, dag outs, dag ins, string asm, 415 list<dag> pattern, Domain d = GenericDomain> 416 : X86Inst<o, f, Imm8Reg, outs, ins, asm, d> { 417 let Pattern = pattern; 418} 419class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 420 list<dag> pattern> 421 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> { 422 let Pattern = pattern; 423} 424class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, 425 list<dag> pattern> 426 : X86Inst<o, f, Imm16, outs, ins, asm> { 427 let Pattern = pattern; 428} 429class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, 430 list<dag> pattern> 431 : X86Inst<o, f, Imm32, outs, ins, asm> { 432 let Pattern = pattern; 433} 434class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm, 435 list<dag> pattern> 436 : X86Inst<o, f, Imm32S, outs, ins, asm> { 437 let Pattern = pattern; 438} 439 440class Ii64<bits<8> o, Format f, dag outs, dag ins, string asm, 441 list<dag> pattern> 442 : X86Inst<o, f, Imm64, outs, ins, asm> { 443 let Pattern = pattern; 444} 445 446class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 447 list<dag> pattern> 448 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> { 449 let Pattern = pattern; 450} 451 452class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 453 list<dag> pattern> 454 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> { 455 let Pattern = pattern; 456} 457 458// FPStack Instruction Templates: 459// FPI - Floating Point Instruction template. 460class FPI<bits<8> o, Format F, dag outs, dag ins, string asm> 461 : I<o, F, outs, ins, asm, []> { 462 let Defs = [FPSW]; 463 let Predicates = [HasX87]; 464} 465 466// FpI_ - Floating Point Pseudo Instruction template. 467class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern> 468 : PseudoI<outs, ins, pattern> { 469 let FPForm = fp; 470 let Defs = [FPSW]; 471 let Predicates = [HasX87]; 472} 473 474// Templates for instructions that use a 16- or 32-bit segmented address as 475// their only operand: lcall (FAR CALL) and ljmp (FAR JMP) 476// 477// Iseg16 - 16-bit segment selector, 16-bit offset 478// Iseg32 - 16-bit segment selector, 32-bit offset 479 480class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, 481 list<dag> pattern> 482 : X86Inst<o, f, Imm16, outs, ins, asm> { 483 let Pattern = pattern; 484} 485 486class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, 487 list<dag> pattern> 488 : X86Inst<o, f, Imm32, outs, ins, asm> { 489 let Pattern = pattern; 490} 491 492// SI - SSE 1 & 2 scalar instructions 493class SI<bits<8> o, Format F, dag outs, dag ins, string asm, 494 list<dag> pattern, Domain d = GenericDomain> 495 : I<o, F, outs, ins, asm, pattern, d> { 496 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 497 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], 498 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 499 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], 500 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 501 [UseSSE1]))))); 502 503 // AVX instructions have a 'v' prefix in the mnemonic 504 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 505 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 506 asm)); 507} 508 509// SI - SSE 1 & 2 scalar intrinsics - vex form available on AVX512 510class SI_Int<bits<8> o, Format F, dag outs, dag ins, string asm, 511 list<dag> pattern, Domain d = GenericDomain> 512 : I<o, F, outs, ins, asm, pattern, d> { 513 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 514 !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], 515 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 516 !if(!eq(OpPrefix.Value, XD.Value), [UseSSE2], 517 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 518 [UseSSE1]))))); 519 520 // AVX instructions have a 'v' prefix in the mnemonic 521 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 522 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 523 asm)); 524} 525// SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512 526class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 527 list<dag> pattern> 528 : Ii8<o, F, outs, ins, asm, pattern> { 529 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 530 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 531 !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], 532 [UseSSE2]))); 533 534 // AVX instructions have a 'v' prefix in the mnemonic 535 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 536 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 537 asm)); 538} 539 540// PI - SSE 1 & 2 packed instructions 541class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 542 Domain d> 543 : I<o, F, outs, ins, asm, pattern, d> { 544 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 545 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 546 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 547 [UseSSE1]))); 548 549 // AVX instructions have a 'v' prefix in the mnemonic 550 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 551 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 552 asm)); 553} 554 555// MMXPI - SSE 1 & 2 packed instructions with MMX operands 556class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, 557 Domain d> 558 : I<o, F, outs, ins, asm, pattern, d> { 559 let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2], 560 [HasMMX, HasSSE1]); 561} 562 563// PIi8 - SSE 1 & 2 packed instructions with immediate 564class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 565 list<dag> pattern, Domain d> 566 : Ii8<o, F, outs, ins, asm, pattern, d> { 567 let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], 568 !if(!eq(OpEnc.Value, EncVEX.Value), [HasAVX], 569 !if(!eq(OpPrefix.Value, PD.Value), [UseSSE2], 570 [UseSSE1]))); 571 572 // AVX instructions have a 'v' prefix in the mnemonic 573 let AsmString = !if(!eq(OpEnc.Value, EncEVEX.Value), !strconcat("v", asm), 574 !if(!eq(OpEnc.Value, EncVEX.Value), !strconcat("v", asm), 575 asm)); 576} 577 578// SSE1 Instruction Templates: 579// 580// SSI - SSE1 instructions with XS prefix. 581// PSI - SSE1 instructions with PS prefix. 582// PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. 583// VSSI - SSE1 instructions with XS prefix in AVX form. 584// VPSI - SSE1 instructions with PS prefix in AVX form, packed single. 585 586class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, 587 list<dag> pattern> 588 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE1]>; 589class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 590 list<dag> pattern> 591 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE1]>; 592class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 593 list<dag> pattern> 594 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, PS, 595 Requires<[UseSSE1]>; 596class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 597 list<dag> pattern> 598 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, PS, 599 Requires<[UseSSE1]>; 600class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm, 601 list<dag> pattern> 602 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS, 603 Requires<[HasAVX]>; 604class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm, 605 list<dag> pattern> 606 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, PS, 607 Requires<[HasAVX]>; 608 609// SSE2 Instruction Templates: 610// 611// SDI - SSE2 instructions with XD prefix. 612// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. 613// S2SI - SSE2 instructions with XS prefix. 614// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix. 615// PDI - SSE2 instructions with PD prefix, packed double domain. 616// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix. 617// VSDI - SSE2 scalar instructions with XD prefix in AVX form. 618// VPDI - SSE2 vector instructions with PD prefix in AVX form, 619// packed double domain. 620// VS2I - SSE2 scalar instructions with PD prefix in AVX form. 621// S2I - SSE2 scalar instructions with PD prefix. 622// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as 623// MMX operands. 624// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as 625// MMX operands. 626 627class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, 628 list<dag> pattern> 629 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[UseSSE2]>; 630class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 631 list<dag> pattern> 632 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[UseSSE2]>; 633class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 634 list<dag> pattern> 635 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>; 636class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 637 list<dag> pattern> 638 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>; 639class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 640 list<dag> pattern> 641 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 642 Requires<[UseSSE2]>; 643class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 644 list<dag> pattern> 645 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 646 Requires<[UseSSE2]>; 647class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm, 648 list<dag> pattern> 649 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD, 650 Requires<[UseAVX]>; 651class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm, 652 list<dag> pattern> 653 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS, 654 Requires<[HasAVX]>; 655class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm, 656 list<dag> pattern> 657 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>, 658 PD, Requires<[HasAVX]>; 659class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 660 list<dag> pattern> 661 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, PD, 662 Requires<[UseAVX]>; 663class S2I<bits<8> o, Format F, dag outs, dag ins, string asm, 664 list<dag> pattern> 665 : I<o, F, outs, ins, asm, pattern>, PD, Requires<[UseSSE2]>; 666class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 667 list<dag> pattern> 668 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX, HasSSE2]>; 669class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 670 list<dag> pattern> 671 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX, HasSSE2]>; 672 673// SSE3 Instruction Templates: 674// 675// S3I - SSE3 instructions with PD prefixes. 676// S3SI - SSE3 instructions with XS prefix. 677// S3DI - SSE3 instructions with XD prefix. 678 679class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, 680 list<dag> pattern> 681 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS, 682 Requires<[UseSSE3]>; 683class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, 684 list<dag> pattern> 685 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD, 686 Requires<[UseSSE3]>; 687class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, 688 list<dag> pattern> 689 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 690 Requires<[UseSSE3]>; 691 692 693// SSSE3 Instruction Templates: 694// 695// SS38I - SSSE3 instructions with T8 prefix. 696// SS3AI - SSSE3 instructions with TA prefix. 697// MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. 698// MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands. 699// 700// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version 701// uses the MMX registers. The 64-bit versions are grouped with the MMX 702// classes. They need to be enabled even if AVX is enabled. 703 704class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 705 list<dag> pattern> 706 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 707 Requires<[UseSSSE3]>; 708class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 709 list<dag> pattern> 710 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 711 Requires<[UseSSSE3]>; 712class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm, 713 list<dag> pattern> 714 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PS, 715 Requires<[HasMMX, HasSSSE3]>; 716class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, 717 list<dag> pattern> 718 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPS, 719 Requires<[HasMMX, HasSSSE3]>; 720 721// SSE4.1 Instruction Templates: 722// 723// SS48I - SSE 4.1 instructions with T8 prefix. 724// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. 725// 726class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm, 727 list<dag> pattern> 728 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 729 Requires<[UseSSE41]>; 730class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 731 list<dag> pattern> 732 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 733 Requires<[UseSSE41]>; 734 735// SSE4.2 Instruction Templates: 736// 737// SS428I - SSE 4.2 instructions with T8 prefix. 738class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm, 739 list<dag> pattern> 740 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 741 Requires<[UseSSE42]>; 742 743// SS42AI = SSE 4.2 instructions with TA prefix 744class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, 745 list<dag> pattern> 746 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 747 Requires<[UseSSE42]>; 748 749// CRC32I - SSE 4.2 CRC32 instructions. 750// NOTE: 'HasCRC32' is used as CRC32 instructions are GPR only and not directly 751// controlled by the SSE42 flag. 752class CRC32I<bits<8> o, Format F, dag outs, dag ins, string asm, 753 list<dag> pattern> 754 : I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasCRC32]>; 755 756// AVX Instruction Templates: 757// Instructions introduced in AVX (no SSE equivalent forms) 758// 759// AVX8I - AVX instructions with T8PD prefix. 760// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8. 761class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm, 762 list<dag> pattern> 763 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 764 Requires<[HasAVX]>; 765class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 766 list<dag> pattern> 767 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 768 Requires<[HasAVX]>; 769 770// AVX2 Instruction Templates: 771// Instructions introduced in AVX2 (no SSE equivalent forms) 772// 773// AVX28I - AVX2 instructions with T8PD prefix. 774// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8. 775class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm, 776 list<dag> pattern> 777 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 778 Requires<[HasAVX2]>; 779class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 780 list<dag> pattern> 781 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 782 Requires<[HasAVX2]>; 783 784 785// AVX-512 Instruction Templates: 786// Instructions introduced in AVX-512 (no SSE equivalent forms) 787// 788// AVX5128I - AVX-512 instructions with T8PD prefix. 789// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8. 790// AVX512PDI - AVX-512 instructions with PD, double packed. 791// AVX512PSI - AVX-512 instructions with PS, single packed. 792// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes. 793// AVX512XSI - AVX-512 instructions with XS prefix, generic domain. 794// AVX512BI - AVX-512 instructions with PD, int packed domain. 795// AVX512SI - AVX-512 scalar instructions with PD prefix. 796 797class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm, 798 list<dag> pattern> 799 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 800 Requires<[HasAVX512]>; 801class AVX5128IBase : T8PD { 802 Domain ExeDomain = SSEPackedInt; 803} 804class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm, 805 list<dag> pattern> 806 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8XS, 807 Requires<[HasAVX512]>; 808class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm, 809 list<dag> pattern> 810 : I<o, F, outs, ins, asm, pattern>, XS, 811 Requires<[HasAVX512]>; 812class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm, 813 list<dag> pattern> 814 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, XD, 815 Requires<[HasAVX512]>; 816class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm, 817 list<dag> pattern> 818 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, PD, 819 Requires<[HasAVX512]>; 820class AVX512BIBase : PD { 821 Domain ExeDomain = SSEPackedInt; 822} 823class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 824 list<dag> pattern> 825 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, PD, 826 Requires<[HasAVX512]>; 827class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 828 list<dag> pattern> 829 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 830 Requires<[HasAVX512]>; 831class AVX512AIi8Base : TAPD { 832 ImmType ImmT = Imm8; 833} 834class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm, 835 list<dag> pattern> 836 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, 837 Requires<[HasAVX512]>; 838class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm, 839 list<dag> pattern> 840 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, PD, 841 Requires<[HasAVX512]>; 842class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm, 843 list<dag> pattern> 844 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, PS, 845 Requires<[HasAVX512]>; 846class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 847 list<dag> pattern, Domain d> 848 : Ii8<o, F, outs, ins, asm, pattern, d>, Requires<[HasAVX512]>; 849class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm, 850 list<dag> pattern, Domain d> 851 : I<o, F, outs, ins, asm, pattern, d>, Requires<[HasAVX512]>; 852class AVX512FMA3S<bits<8> o, Format F, dag outs, dag ins, string asm, 853 list<dag>pattern> 854 : I<o, F, outs, ins, asm, pattern>, T8PD, 855 EVEX_4V, Requires<[HasAVX512]>; 856 857class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm, 858 list<dag>pattern> 859 : I<o, F, outs, ins, asm, pattern>, Requires<[HasAVX512]>; 860 861// AES Instruction Templates: 862// 863// AES8I 864// These use the same encoding as the SSE4.2 T8 and TA encodings. 865class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm, 866 list<dag>pattern> 867 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PD, 868 Requires<[NoAVX, HasAES]>; 869 870class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm, 871 list<dag> pattern> 872 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 873 Requires<[NoAVX, HasAES]>; 874 875// PCLMUL Instruction Templates 876class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 877 list<dag>pattern> 878 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD; 879 880// FMA3 Instruction Templates 881class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, 882 list<dag>pattern> 883 : I<o, F, outs, ins, asm, pattern>, T8PD, 884 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>; 885class FMA3S<bits<8> o, Format F, dag outs, dag ins, string asm, 886 list<dag>pattern> 887 : I<o, F, outs, ins, asm, pattern>, T8PD, 888 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>; 889class FMA3S_Int<bits<8> o, Format F, dag outs, dag ins, string asm, 890 list<dag>pattern> 891 : I<o, F, outs, ins, asm, pattern>, T8PD, 892 VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>; 893 894// FMA4 Instruction Templates 895class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm, 896 list<dag>pattern> 897 : Ii8Reg<o, F, outs, ins, asm, pattern>, TAPD, 898 VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>; 899class FMA4S<bits<8> o, Format F, dag outs, dag ins, string asm, 900 list<dag>pattern> 901 : Ii8Reg<o, F, outs, ins, asm, pattern>, TAPD, 902 VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>; 903class FMA4S_Int<bits<8> o, Format F, dag outs, dag ins, string asm, 904 list<dag>pattern> 905 : Ii8Reg<o, F, outs, ins, asm, pattern>, TAPD, 906 VEX_4V, FMASC, Requires<[HasFMA4]>; 907 908// XOP 2, 3 and 4 Operand Instruction Template 909class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm, 910 list<dag> pattern> 911 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, 912 XOP9, Requires<[HasXOP]>; 913 914// XOP 2 and 3 Operand Instruction Templates with imm byte 915class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm, 916 list<dag> pattern> 917 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, 918 XOP8, Requires<[HasXOP]>; 919// XOP 4 Operand Instruction Templates with imm byte 920class IXOPi8Reg<bits<8> o, Format F, dag outs, dag ins, string asm, 921 list<dag> pattern> 922 : Ii8Reg<o, F, outs, ins, asm, pattern, SSEPackedDouble>, 923 XOP8, Requires<[HasXOP]>; 924 925// XOP 5 operand instruction (VEX encoding!) 926class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm, 927 list<dag>pattern> 928 : Ii8Reg<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPD, 929 VEX_4V, Requires<[HasXOP]>; 930 931// X86-64 Instruction templates... 932// 933 934class RI<bits<8> o, Format F, dag outs, dag ins, string asm, 935 list<dag> pattern> 936 : I<o, F, outs, ins, asm, pattern>, REX_W; 937class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm, 938 list<dag> pattern> 939 : Ii8<o, F, outs, ins, asm, pattern>, REX_W; 940class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm, 941 list<dag> pattern> 942 : Ii16<o, F, outs, ins, asm, pattern>, REX_W; 943class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm, 944 list<dag> pattern> 945 : Ii32<o, F, outs, ins, asm, pattern>, REX_W; 946class RIi32S <bits<8> o, Format F, dag outs, dag ins, string asm, 947 list<dag> pattern> 948 : Ii32S<o, F, outs, ins, asm, pattern>, REX_W; 949class RIi64<bits<8> o, Format F, dag outs, dag ins, string asm, 950 list<dag> pattern> 951 : Ii64<o, F, outs, ins, asm, pattern>, REX_W; 952 953class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 954 list<dag> pattern> 955 : S2I<o, F, outs, ins, asm, pattern>, REX_W; 956class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm, 957 list<dag> pattern> 958 : VS2I<o, F, outs, ins, asm, pattern>, REX_W; 959 960// MMX Instruction templates 961// 962 963// MMXI - MMX instructions with TB prefix. 964// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode. 965// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode. 966// MMX2I - MMX / SSE2 instructions with PD prefix. 967// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 968// MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. 969// MMXID - MMX instructions with XD prefix. 970// MMXIS - MMX instructions with XS prefix. 971class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, 972 list<dag> pattern> 973 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX]>; 974class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, 975 list<dag> pattern> 976 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,Not64BitMode]>; 977class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, 978 list<dag> pattern> 979 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,In64BitMode]>; 980class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, 981 list<dag> pattern> 982 : I<o, F, outs, ins, asm, pattern>, PS, REX_W, 983 Requires<[HasMMX,In64BitMode]>; 984class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, 985 list<dag> pattern> 986 : I<o, F, outs, ins, asm, pattern>, PD, Requires<[HasMMX]>; 987class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 988 list<dag> pattern> 989 : Ii8<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX]>; 990class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, 991 list<dag> pattern> 992 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>; 993class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, 994 list<dag> pattern> 995 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>; 996 997/// ITy - This instruction base class takes the type info for the instruction. 998/// Using this, it: 999/// 1. Concatenates together the instruction mnemonic with the appropriate 1000/// suffix letter, a tab, and the arguments. 1001/// 2. Infers whether the instruction should have a 0x66 prefix byte. 1002/// 3. Infers whether the instruction should have a 0x40 REX_W prefix. 1003/// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations) 1004/// or 1 (for i16,i32,i64 operations). 1005class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, 1006 string mnemonic, string args, list<dag> pattern> 1007 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4}, 1008 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode }, 1009 f, outs, ins, 1010 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> { 1011 1012 // Infer instruction prefixes from type info. 1013 let OpSize = typeinfo.OpSize; 1014 let hasREX_W = typeinfo.HasREX_W; 1015} 1016