1//===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This describes the available hardware counters for various subtargets.
10//
11//===----------------------------------------------------------------------===//
12
13def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;
14def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;
15
16// No default counters on X86.
17def DefaultPfmCounters : ProcPfmCounters {}
18def : PfmCountersDefaultBinding<DefaultPfmCounters>;
19
20// Intel X86 Counters.
21def PentiumPfmCounters : ProcPfmCounters {
22  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
23  let UopsCounter = PfmCounter<"uops_retired">;
24}
25def : PfmCountersBinding<"pentiumpro", PentiumPfmCounters>;
26def : PfmCountersBinding<"pentium2", PentiumPfmCounters>;
27def : PfmCountersBinding<"pentium3", PentiumPfmCounters>;
28def : PfmCountersBinding<"pentium3m", PentiumPfmCounters>;
29def : PfmCountersBinding<"pentium-m", PentiumPfmCounters>;
30
31def CorePfmCounters : ProcPfmCounters {
32  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
33  let UopsCounter = PfmCounter<"uops_retired:any">;
34}
35def : PfmCountersBinding<"yonah", CorePfmCounters>;
36def : PfmCountersBinding<"prescott", CorePfmCounters>;
37
38def AtomPfmCounters : ProcPfmCounters {
39  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
40  let UopsCounter = PfmCounter<"uops_retired:any">;
41}
42def : PfmCountersBinding<"bonnell", AtomPfmCounters>;
43def : PfmCountersBinding<"atom", AtomPfmCounters>;
44
45def SLMPfmCounters : ProcPfmCounters {
46  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
47  let UopsCounter = PfmCounter<"uops_retired:any">;
48  let IssueCounters = [
49    PfmIssueCounter<"SLM_MEC_RSV", "mem_uop_retired:any_ld + mem_uop_retired:any_st">
50  ];
51}
52def : PfmCountersBinding<"silvermont", SLMPfmCounters>;
53def : PfmCountersBinding<"goldmont", SLMPfmCounters>;
54def : PfmCountersBinding<"goldmont-plus", SLMPfmCounters>;
55def : PfmCountersBinding<"tremont", SLMPfmCounters>;
56
57def KnightPfmCounters : ProcPfmCounters {
58  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
59  let UopsCounter = PfmCounter<"uops_retired:all">;
60}
61def : PfmCountersBinding<"knl", KnightPfmCounters>;
62def : PfmCountersBinding<"knm", KnightPfmCounters>;
63
64def Core2PfmCounters : ProcPfmCounters {
65  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
66  let UopsCounter = PfmCounter<"uops_retired:any">;
67  let IssueCounters = [
68    PfmIssueCounter<"SBPort0",  "rs_uops_dispatched_cycles:port_0">,
69    PfmIssueCounter<"SBPort1",  "rs_uops_dispatched_cycles:port_1">,
70    PfmIssueCounter<"SBPort23", "rs_uops_dispatched_cycles:port_2 + rs_uops_dispatched_cycles:port_3">,
71    PfmIssueCounter<"SBPort4",  "rs_uops_dispatched_cycles:port_4">,
72    PfmIssueCounter<"SBPort5",  "rs_uops_dispatched_cycles:port_5">
73  ];
74}
75def : PfmCountersBinding<"core2", Core2PfmCounters>;
76def : PfmCountersBinding<"penryn", Core2PfmCounters>;
77
78def NehalemPfmCounters : ProcPfmCounters {
79  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
80  let UopsCounter = PfmCounter<"uops_retired:any">;
81  let IssueCounters = [
82    PfmIssueCounter<"SBPort0",  "uops_executed:port0">,
83    PfmIssueCounter<"SBPort1",  "uops_executed:port1">,
84    PfmIssueCounter<"SBPort23", "uops_executed:port2_core + uops_executed:port3_core">,
85    PfmIssueCounter<"SBPort4",  "uops_executed:port4_core">,
86    PfmIssueCounter<"SBPort5",  "uops_executed:port5">
87  ];
88}
89def : PfmCountersBinding<"nehalem", NehalemPfmCounters>;
90def : PfmCountersBinding<"corei7", NehalemPfmCounters>;
91def : PfmCountersBinding<"westmere", NehalemPfmCounters>;
92
93def SandyBridgePfmCounters : ProcPfmCounters {
94  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
95  let UopsCounter = UopsIssuedPfmCounter;
96  let IssueCounters = [
97    PfmIssueCounter<"SBPort0",  "uops_dispatched_port:port_0">,
98    PfmIssueCounter<"SBPort1",  "uops_dispatched_port:port_1">,
99    PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,
100    PfmIssueCounter<"SBPort4",  "uops_dispatched_port:port_4">,
101    PfmIssueCounter<"SBPort5",  "uops_dispatched_port:port_5">
102  ];
103}
104def : PfmCountersBinding<"sandybridge", SandyBridgePfmCounters>;
105def : PfmCountersBinding<"ivybridge", SandyBridgePfmCounters>;
106
107def HaswellPfmCounters : ProcPfmCounters {
108  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
109  let UopsCounter = UopsIssuedPfmCounter;
110  let IssueCounters = [
111    PfmIssueCounter<"HWPort0", "uops_executed_port:port_0">,
112    PfmIssueCounter<"HWPort1", "uops_executed_port:port_1">,
113    PfmIssueCounter<"HWPort2", "uops_executed_port:port_2">,
114    PfmIssueCounter<"HWPort3", "uops_executed_port:port_3">,
115    PfmIssueCounter<"HWPort4", "uops_executed_port:port_4">,
116    PfmIssueCounter<"HWPort5", "uops_executed_port:port_5">,
117    PfmIssueCounter<"HWPort6", "uops_executed_port:port_6">,
118    PfmIssueCounter<"HWPort7", "uops_executed_port:port_7">
119  ];
120}
121def : PfmCountersBinding<"haswell", HaswellPfmCounters>;
122
123def BroadwellPfmCounters : ProcPfmCounters {
124  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
125  let UopsCounter = UopsIssuedPfmCounter;
126  let IssueCounters = [
127    PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">,
128    PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">,
129    PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">,
130    PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">,
131    PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">,
132    PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">,
133    PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">,
134    PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">
135  ];
136}
137def : PfmCountersBinding<"broadwell", BroadwellPfmCounters>;
138
139def SkylakeClientPfmCounters : ProcPfmCounters {
140  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
141  let UopsCounter = UopsIssuedPfmCounter;
142  let IssueCounters = [
143    PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">,
144    PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">,
145    PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">,
146    PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">,
147    PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">,
148    PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">,
149    PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">,
150    PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">
151  ];
152}
153def : PfmCountersBinding<"skylake", SkylakeClientPfmCounters>;
154
155def SkylakeServerPfmCounters : ProcPfmCounters {
156  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
157  let UopsCounter = UopsIssuedPfmCounter;
158  let IssueCounters = [
159    PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">,
160    PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">,
161    PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">,
162    PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">,
163    PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">,
164    PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">,
165    PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">,
166    PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">
167  ];
168}
169def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;
170def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>;
171def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>;
172
173def IceLakePfmCounters : ProcPfmCounters {
174  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
175  let UopsCounter = UopsIssuedPfmCounter;
176  let IssueCounters = [
177    PfmIssueCounter<"ICXPort0",  "uops_dispatched_port:port_0">,
178    PfmIssueCounter<"ICXPort1",  "uops_dispatched_port:port_1">,
179    PfmIssueCounter<"ICXPort23", "uops_dispatched_port:port_2_3">,
180    PfmIssueCounter<"ICXPort49", "uops_dispatched_port:port_4_9">,
181    PfmIssueCounter<"ICXPort5",  "uops_dispatched_port:port_5">,
182    PfmIssueCounter<"ICXPort6",  "uops_dispatched_port:port_6">,
183    PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8">
184  ];
185}
186def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>;
187def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
188def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
189def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;
190
191// AMD X86 Counters.
192// Set basic counters for AMD cpus that we know libpfm4 supports.
193def DefaultAMDPfmCounters : ProcPfmCounters {
194  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
195  let UopsCounter = PfmCounter<"retired_uops">;
196}
197def : PfmCountersBinding<"athlon", DefaultAMDPfmCounters>;
198def : PfmCountersBinding<"athlon-tbird", DefaultAMDPfmCounters>;
199def : PfmCountersBinding<"athlon-4", DefaultAMDPfmCounters>;
200def : PfmCountersBinding<"athlon-xp", DefaultAMDPfmCounters>;
201def : PfmCountersBinding<"athlon-mp", DefaultAMDPfmCounters>;
202def : PfmCountersBinding<"k8", DefaultAMDPfmCounters>;
203def : PfmCountersBinding<"opteron", DefaultAMDPfmCounters>;
204def : PfmCountersBinding<"athlon64", DefaultAMDPfmCounters>;
205def : PfmCountersBinding<"athlon-fx", DefaultAMDPfmCounters>;
206def : PfmCountersBinding<"k8-sse3", DefaultAMDPfmCounters>;
207def : PfmCountersBinding<"opteron-sse3", DefaultAMDPfmCounters>;
208def : PfmCountersBinding<"athlon64-sse3", DefaultAMDPfmCounters>;
209def : PfmCountersBinding<"amdfam10", DefaultAMDPfmCounters>;
210def : PfmCountersBinding<"barcelona", DefaultAMDPfmCounters>;
211
212def BdVer2PfmCounters : ProcPfmCounters {
213  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
214  let UopsCounter = PfmCounter<"retired_uops">;
215  let IssueCounters = [
216    PfmIssueCounter<"PdFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
217    PfmIssueCounter<"PdFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
218    PfmIssueCounter<"PdFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">,
219    PfmIssueCounter<"PdFPU3", "dispatched_fpu_ops:ops_pipe3 + dispatched_fpu_ops:ops_dual_pipe3">
220  ];
221}
222def : PfmCountersBinding<"bdver1", BdVer2PfmCounters>;
223def : PfmCountersBinding<"bdver2", BdVer2PfmCounters>;
224
225def BdVer3PfmCounters : ProcPfmCounters {
226  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
227  let UopsCounter = PfmCounter<"retired_uops">;
228  let IssueCounters = [
229    PfmIssueCounter<"SrFPU0", "dispatched_fpu_ops:ops_pipe0 + dispatched_fpu_ops:ops_dual_pipe0">,
230    PfmIssueCounter<"SrFPU1", "dispatched_fpu_ops:ops_pipe1 + dispatched_fpu_ops:ops_dual_pipe1">,
231    PfmIssueCounter<"SrFPU2", "dispatched_fpu_ops:ops_pipe2 + dispatched_fpu_ops:ops_dual_pipe2">
232  ];
233}
234def : PfmCountersBinding<"bdver3", BdVer3PfmCounters>;
235def : PfmCountersBinding<"bdver4", BdVer3PfmCounters>;
236
237def BtVer1PfmCounters : ProcPfmCounters {
238  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
239  let UopsCounter = PfmCounter<"retired_uops">;
240  let IssueCounters = [
241    PfmIssueCounter<"BtFPU0", "dispatched_fpu:pipe0">,
242    PfmIssueCounter<"BtFPU1", "dispatched_fpu:pipe1">
243  ];
244}
245def : PfmCountersBinding<"btver1", BtVer1PfmCounters>;
246
247def BtVer2PfmCounters : ProcPfmCounters {
248  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
249  let UopsCounter = PfmCounter<"retired_uops">;
250  let IssueCounters = [
251    PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">,
252    PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1">
253  ];
254}
255def : PfmCountersBinding<"btver2", BtVer2PfmCounters>;
256
257def ZnVer1PfmCounters : ProcPfmCounters {
258  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
259  let UopsCounter = PfmCounter<"retired_uops">;
260  let IssueCounters = [
261    PfmIssueCounter<"ZnFPU0", "fpu_pipe_assignment:total0">,
262    PfmIssueCounter<"ZnFPU1", "fpu_pipe_assignment:total1">,
263    PfmIssueCounter<"ZnFPU2", "fpu_pipe_assignment:total2">,
264    PfmIssueCounter<"ZnFPU3", "fpu_pipe_assignment:total3">,
265    PfmIssueCounter<"ZnAGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
266    PfmIssueCounter<"ZnDivider", "div_op_count">
267  ];
268}
269def : PfmCountersBinding<"znver1", ZnVer1PfmCounters>;
270
271def ZnVer2PfmCounters : ProcPfmCounters {
272  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
273  let UopsCounter = PfmCounter<"retired_uops">;
274  let IssueCounters = [
275    PfmIssueCounter<"Zn2AGU", "ls_dispatch:ld_st_dispatch + ls_dispatch:ld_dispatch + ls_dispatch:store_dispatch">,
276    PfmIssueCounter<"Zn2Divider", "div_op_count">
277  ];
278}
279def : PfmCountersBinding<"znver2", ZnVer2PfmCounters>;
280
281def ZnVer3PfmCounters : ProcPfmCounters {
282  let CycleCounter = PfmCounter<"cycles_not_in_halt">;
283  let UopsCounter = PfmCounter<"retired_ops">;
284  let IssueCounters = [
285    PfmIssueCounter<"Zn3Int", "ops_type_dispatched_from_decoder:int_disp_retire_mode">,
286    PfmIssueCounter<"Zn3FPU", "ops_type_dispatched_from_decoder:fp_disp_retire_mode">,
287    PfmIssueCounter<"Zn3Load", "ls_dispatch:ld_dispatch">,
288    PfmIssueCounter<"Zn3Store", "ls_dispatch:store_dispatch">,
289    PfmIssueCounter<"Zn3Divider", "div_op_count">
290  ];
291}
292def : PfmCountersBinding<"znver3", ZnVer3PfmCounters>;
293def : PfmCountersBinding<"znver4", ZnVer3PfmCounters>;
294