1 //===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the X86 implementation of the TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H 14 #define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H 15 16 #include "llvm/CodeGen/TargetRegisterInfo.h" 17 18 #define GET_REGINFO_HEADER 19 #include "X86GenRegisterInfo.inc" 20 21 namespace llvm { 22 class Triple; 23 24 class X86RegisterInfo final : public X86GenRegisterInfo { 25 private: 26 /// Is64Bit - Is the target 64-bits. 27 /// 28 bool Is64Bit; 29 30 /// IsWin64 - Is the target on of win64 flavours 31 /// 32 bool IsWin64; 33 34 /// SlotSize - Stack slot size in bytes. 35 /// 36 unsigned SlotSize; 37 38 /// StackPtr - X86 physical register used as stack ptr. 39 /// 40 unsigned StackPtr; 41 42 /// FramePtr - X86 physical register used as frame ptr. 43 /// 44 unsigned FramePtr; 45 46 /// BasePtr - X86 physical register used as a base ptr in complex stack 47 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 48 /// variable size stack objects. 49 unsigned BasePtr; 50 51 public: 52 explicit X86RegisterInfo(const Triple &TT); 53 54 // FIXME: This should be tablegen'd like getDwarfRegNum is 55 int getSEHRegNum(unsigned i) const; 56 57 /// Code Generation virtual methods... 58 /// 59 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; 60 61 /// getMatchingSuperRegClass - Return a subclass of the specified register 62 /// class A so that each register in it has a sub-register of the 63 /// specified sub-register index which is in the specified register class B. 64 const TargetRegisterClass * 65 getMatchingSuperRegClass(const TargetRegisterClass *A, 66 const TargetRegisterClass *B, 67 unsigned Idx) const override; 68 69 const TargetRegisterClass * 70 getSubClassWithSubReg(const TargetRegisterClass *RC, 71 unsigned Idx) const override; 72 73 const TargetRegisterClass * 74 getLargestLegalSuperClass(const TargetRegisterClass *RC, 75 const MachineFunction &MF) const override; 76 77 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 78 unsigned DefSubReg, 79 const TargetRegisterClass *SrcRC, 80 unsigned SrcSubReg) const override; 81 82 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 83 /// values. 84 const TargetRegisterClass * 85 getPointerRegClass(const MachineFunction &MF, 86 unsigned Kind = 0) const override; 87 88 /// getCrossCopyRegClass - Returns a legal register class to copy a register 89 /// in the specified class to or from. Returns NULL if it is possible to copy 90 /// between a two registers of the specified class. 91 const TargetRegisterClass * 92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 93 94 /// getGPRsForTailCall - Returns a register class with registers that can be 95 /// used in forming tail calls. 96 const TargetRegisterClass * 97 getGPRsForTailCall(const MachineFunction &MF) const; 98 99 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 100 MachineFunction &MF) const override; 101 102 /// getCalleeSavedRegs - Return a null-terminated list of all of the 103 /// callee-save registers on this target. 104 const MCPhysReg * 105 getCalleeSavedRegs(const MachineFunction* MF) const override; 106 const MCPhysReg * 107 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const; 108 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 109 CallingConv::ID) const override; 110 const uint32_t *getNoPreservedMask() const override; 111 112 // Calls involved in thread-local variable lookup save more registers than 113 // normal calls, so they need a different mask to represent this. 114 const uint32_t *getDarwinTLSCallPreservedMask() const; 115 116 /// getReservedRegs - Returns a bitset indexed by physical register number 117 /// indicating if a register is a special register that has particular uses and 118 /// should be considered unavailable at all times, e.g. SP, RA. This is used by 119 /// register scavenger to determine what registers are free. 120 BitVector getReservedRegs(const MachineFunction &MF) const override; 121 122 void adjustStackMapLiveOutMask(uint32_t *Mask) const override; 123 124 bool hasBasePointer(const MachineFunction &MF) const; 125 126 bool canRealignStack(const MachineFunction &MF) const override; 127 128 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 129 int &FrameIdx) const override; 130 131 void eliminateFrameIndex(MachineBasicBlock::iterator MI, 132 int SPAdj, unsigned FIOperandNum, 133 RegScavenger *RS = nullptr) const override; 134 135 // Debug information queries. 136 Register getFrameRegister(const MachineFunction &MF) const override; 137 unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const; 138 unsigned getPtrSizedStackRegister(const MachineFunction &MF) const; 139 Register getStackRegister() const { return StackPtr; } 140 Register getBaseRegister() const { return BasePtr; } 141 /// Returns physical register used as frame pointer. 142 /// This will always returns the frame pointer register, contrary to 143 /// getFrameRegister() which returns the "base pointer" in situations 144 /// involving a stack, frame and base pointer. 145 Register getFramePtr() const { return FramePtr; } 146 // FIXME: Move to FrameInfok 147 unsigned getSlotSize() const { return SlotSize; } 148 }; 149 150 } // End llvm namespace 151 152 #endif 153