10b57cec5SDimitry Andric//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the X86 Register file, defining the registers themselves, 100b57cec5SDimitry Andric// aliases between the registers, and the register classes built out of the 110b57cec5SDimitry Andric// registers. 120b57cec5SDimitry Andric// 130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andricclass X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { 160b57cec5SDimitry Andric let Namespace = "X86"; 170b57cec5SDimitry Andric let HWEncoding = Enc; 180b57cec5SDimitry Andric let SubRegs = subregs; 190b57cec5SDimitry Andric} 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric// Subregister indices. 220b57cec5SDimitry Andriclet Namespace = "X86" in { 230b57cec5SDimitry Andric def sub_8bit : SubRegIndex<8>; 240b57cec5SDimitry Andric def sub_8bit_hi : SubRegIndex<8, 8>; 250b57cec5SDimitry Andric def sub_8bit_hi_phony : SubRegIndex<8, 8>; 260b57cec5SDimitry Andric def sub_16bit : SubRegIndex<16>; 270b57cec5SDimitry Andric def sub_16bit_hi : SubRegIndex<16, 16>; 280b57cec5SDimitry Andric def sub_32bit : SubRegIndex<32>; 290b57cec5SDimitry Andric def sub_xmm : SubRegIndex<128>; 300b57cec5SDimitry Andric def sub_ymm : SubRegIndex<256>; 310b57cec5SDimitry Andric def sub_mask_0 : SubRegIndex<-1>; 320b57cec5SDimitry Andric def sub_mask_1 : SubRegIndex<-1, -1>; 330b57cec5SDimitry Andric} 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 360b57cec5SDimitry Andric// Register definitions... 370b57cec5SDimitry Andric// 380b57cec5SDimitry Andric 390b57cec5SDimitry Andric// In the register alias definitions below, we define which registers alias 400b57cec5SDimitry Andric// which others. We only specify which registers the small registers alias, 410b57cec5SDimitry Andric// because the register file generator is smart enough to figure out that 420b57cec5SDimitry Andric// AL aliases AX if we tell it that AX aliased AL (for example). 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric// Dwarf numbering is different for 32-bit and 64-bit, and there are 450b57cec5SDimitry Andric// variations by target as well. Currently the first entry is for X86-64, 460b57cec5SDimitry Andric// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 470b57cec5SDimitry Andric// and debug information on X86-32/Darwin) 480b57cec5SDimitry Andric 490b57cec5SDimitry Andric// 8-bit registers 500b57cec5SDimitry Andric// Low registers 510b57cec5SDimitry Andricdef AL : X86Reg<"al", 0>; 520b57cec5SDimitry Andricdef DL : X86Reg<"dl", 2>; 530b57cec5SDimitry Andricdef CL : X86Reg<"cl", 1>; 540b57cec5SDimitry Andricdef BL : X86Reg<"bl", 3>; 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric// High registers. On x86-64, these cannot be used in any instruction 570b57cec5SDimitry Andric// with a REX prefix. 580b57cec5SDimitry Andricdef AH : X86Reg<"ah", 4>; 590b57cec5SDimitry Andricdef DH : X86Reg<"dh", 6>; 600b57cec5SDimitry Andricdef CH : X86Reg<"ch", 5>; 610b57cec5SDimitry Andricdef BH : X86Reg<"bh", 7>; 620b57cec5SDimitry Andric 630b57cec5SDimitry Andric// X86-64 only, requires REX. 640b57cec5SDimitry Andricdef SIL : X86Reg<"sil", 6>; 650b57cec5SDimitry Andricdef DIL : X86Reg<"dil", 7>; 660b57cec5SDimitry Andricdef BPL : X86Reg<"bpl", 5>; 670b57cec5SDimitry Andricdef SPL : X86Reg<"spl", 4>; 680b57cec5SDimitry Andricdef R8B : X86Reg<"r8b", 8>; 690b57cec5SDimitry Andricdef R9B : X86Reg<"r9b", 9>; 700b57cec5SDimitry Andricdef R10B : X86Reg<"r10b", 10>; 710b57cec5SDimitry Andricdef R11B : X86Reg<"r11b", 11>; 720b57cec5SDimitry Andricdef R12B : X86Reg<"r12b", 12>; 730b57cec5SDimitry Andricdef R13B : X86Reg<"r13b", 13>; 740b57cec5SDimitry Andricdef R14B : X86Reg<"r14b", 14>; 750b57cec5SDimitry Andricdef R15B : X86Reg<"r15b", 15>; 765f757f3fSDimitry Andric// RAGreedy prefers to select a cheaper register 775f757f3fSDimitry Andric// For x86, 785f757f3fSDimitry Andric// Cost(caller-save reg) < Cost(callee-save reg) 795f757f3fSDimitry Andric// b/c callee-save register needs push/pop in prolog/epilog. 805f757f3fSDimitry Andric// If both registers are callee-saved or caller-saved, 815f757f3fSDimitry Andric// Cost(short-encoding reg) < Cost(long-encoding reg) 825f757f3fSDimitry Andric// 835f757f3fSDimitry Andric// To achieve this, we do the following things: 845f757f3fSDimitry Andric// 1. Set CostPerUse=1 for registers that need prefix 855f757f3fSDimitry Andric// 2. Consider callee-save register is never cheaper than a register w/ cost 1 865f757f3fSDimitry Andric// 3. List caller-save register before callee-save regsiter in RegisterClass 875f757f3fSDimitry Andric// or AllocationOrder 885f757f3fSDimitry Andric// 895f757f3fSDimitry Andric// NOTE: 905f757f3fSDimitry Andric// D133902 stopped assigning register costs for R8-R15, which brought gain 915f757f3fSDimitry Andric// and regression. We don't know if we should assign cost to R16-R31 w/o 925f757f3fSDimitry Andric// performance data. 935f757f3fSDimitry Andric// TODO: 945f757f3fSDimitry Andric// Update the comment/cost after tuning. 955f757f3fSDimitry Andric// APX only, requires REX2 or EVEX. 965f757f3fSDimitry Andriclet PositionOrder = 4 in { 975f757f3fSDimitry Andricdef R16B : X86Reg<"r16b", 16>; 985f757f3fSDimitry Andricdef R17B : X86Reg<"r17b", 17>; 995f757f3fSDimitry Andricdef R18B : X86Reg<"r18b", 18>; 1005f757f3fSDimitry Andricdef R19B : X86Reg<"r19b", 19>; 1015f757f3fSDimitry Andricdef R20B : X86Reg<"r20b", 20>; 1025f757f3fSDimitry Andricdef R21B : X86Reg<"r21b", 21>; 1035f757f3fSDimitry Andricdef R22B : X86Reg<"r22b", 22>; 1045f757f3fSDimitry Andricdef R23B : X86Reg<"r23b", 23>; 1055f757f3fSDimitry Andricdef R24B : X86Reg<"r24b", 24>; 1065f757f3fSDimitry Andricdef R25B : X86Reg<"r25b", 25>; 1075f757f3fSDimitry Andricdef R26B : X86Reg<"r26b", 26>; 1085f757f3fSDimitry Andricdef R27B : X86Reg<"r27b", 27>; 1095f757f3fSDimitry Andricdef R28B : X86Reg<"r28b", 28>; 1105f757f3fSDimitry Andricdef R29B : X86Reg<"r29b", 29>; 1115f757f3fSDimitry Andricdef R30B : X86Reg<"r30b", 30>; 1125f757f3fSDimitry Andricdef R31B : X86Reg<"r31b", 31>; 1135f757f3fSDimitry Andric} 1140b57cec5SDimitry Andric 1150b57cec5SDimitry Andriclet isArtificial = 1 in { 1160b57cec5SDimitry Andric// High byte of the low 16 bits of the super-register: 1170b57cec5SDimitry Andricdef SIH : X86Reg<"", -1>; 1180b57cec5SDimitry Andricdef DIH : X86Reg<"", -1>; 1190b57cec5SDimitry Andricdef BPH : X86Reg<"", -1>; 1200b57cec5SDimitry Andricdef SPH : X86Reg<"", -1>; 1210b57cec5SDimitry Andricdef R8BH : X86Reg<"", -1>; 1220b57cec5SDimitry Andricdef R9BH : X86Reg<"", -1>; 1230b57cec5SDimitry Andricdef R10BH : X86Reg<"", -1>; 1240b57cec5SDimitry Andricdef R11BH : X86Reg<"", -1>; 1250b57cec5SDimitry Andricdef R12BH : X86Reg<"", -1>; 1260b57cec5SDimitry Andricdef R13BH : X86Reg<"", -1>; 1270b57cec5SDimitry Andricdef R14BH : X86Reg<"", -1>; 1280b57cec5SDimitry Andricdef R15BH : X86Reg<"", -1>; 1295f757f3fSDimitry Andriclet PositionOrder = 4 in { 1305f757f3fSDimitry Andricdef R16BH : X86Reg<"", -1>; 1315f757f3fSDimitry Andricdef R17BH : X86Reg<"", -1>; 1325f757f3fSDimitry Andricdef R18BH : X86Reg<"", -1>; 1335f757f3fSDimitry Andricdef R19BH : X86Reg<"", -1>; 1345f757f3fSDimitry Andricdef R20BH : X86Reg<"", -1>; 1355f757f3fSDimitry Andricdef R21BH : X86Reg<"", -1>; 1365f757f3fSDimitry Andricdef R22BH : X86Reg<"", -1>; 1375f757f3fSDimitry Andricdef R23BH : X86Reg<"", -1>; 1385f757f3fSDimitry Andricdef R24BH : X86Reg<"", -1>; 1395f757f3fSDimitry Andricdef R25BH : X86Reg<"", -1>; 1405f757f3fSDimitry Andricdef R26BH : X86Reg<"", -1>; 1415f757f3fSDimitry Andricdef R27BH : X86Reg<"", -1>; 1425f757f3fSDimitry Andricdef R28BH : X86Reg<"", -1>; 1435f757f3fSDimitry Andricdef R29BH : X86Reg<"", -1>; 1445f757f3fSDimitry Andricdef R30BH : X86Reg<"", -1>; 1455f757f3fSDimitry Andricdef R31BH : X86Reg<"", -1>; 1465f757f3fSDimitry Andric} 1470b57cec5SDimitry Andric// High word of the low 32 bits of the super-register: 1480b57cec5SDimitry Andricdef HAX : X86Reg<"", -1>; 1490b57cec5SDimitry Andricdef HDX : X86Reg<"", -1>; 1500b57cec5SDimitry Andricdef HCX : X86Reg<"", -1>; 1510b57cec5SDimitry Andricdef HBX : X86Reg<"", -1>; 1520b57cec5SDimitry Andricdef HSI : X86Reg<"", -1>; 1530b57cec5SDimitry Andricdef HDI : X86Reg<"", -1>; 1540b57cec5SDimitry Andricdef HBP : X86Reg<"", -1>; 1550b57cec5SDimitry Andricdef HSP : X86Reg<"", -1>; 1560b57cec5SDimitry Andricdef HIP : X86Reg<"", -1>; 1570b57cec5SDimitry Andricdef R8WH : X86Reg<"", -1>; 1580b57cec5SDimitry Andricdef R9WH : X86Reg<"", -1>; 1590b57cec5SDimitry Andricdef R10WH : X86Reg<"", -1>; 1600b57cec5SDimitry Andricdef R11WH : X86Reg<"", -1>; 1610b57cec5SDimitry Andricdef R12WH : X86Reg<"", -1>; 1620b57cec5SDimitry Andricdef R13WH : X86Reg<"", -1>; 1630b57cec5SDimitry Andricdef R14WH : X86Reg<"", -1>; 1640b57cec5SDimitry Andricdef R15WH : X86Reg<"", -1>; 1655f757f3fSDimitry Andriclet PositionOrder = 4 in { 1665f757f3fSDimitry Andricdef R16WH : X86Reg<"", -1>; 1675f757f3fSDimitry Andricdef R17WH : X86Reg<"", -1>; 1685f757f3fSDimitry Andricdef R18WH : X86Reg<"", -1>; 1695f757f3fSDimitry Andricdef R19WH : X86Reg<"", -1>; 1705f757f3fSDimitry Andricdef R20WH : X86Reg<"", -1>; 1715f757f3fSDimitry Andricdef R21WH : X86Reg<"", -1>; 1725f757f3fSDimitry Andricdef R22WH : X86Reg<"", -1>; 1735f757f3fSDimitry Andricdef R23WH : X86Reg<"", -1>; 1745f757f3fSDimitry Andricdef R24WH : X86Reg<"", -1>; 1755f757f3fSDimitry Andricdef R25WH : X86Reg<"", -1>; 1765f757f3fSDimitry Andricdef R26WH : X86Reg<"", -1>; 1775f757f3fSDimitry Andricdef R27WH : X86Reg<"", -1>; 1785f757f3fSDimitry Andricdef R28WH : X86Reg<"", -1>; 1795f757f3fSDimitry Andricdef R29WH : X86Reg<"", -1>; 1805f757f3fSDimitry Andricdef R30WH : X86Reg<"", -1>; 1815f757f3fSDimitry Andricdef R31WH : X86Reg<"", -1>; 1825f757f3fSDimitry Andric} 1830b57cec5SDimitry Andric} 1840b57cec5SDimitry Andric 1850b57cec5SDimitry Andric// 16-bit registers 1860b57cec5SDimitry Andriclet SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { 1870b57cec5SDimitry Andricdef AX : X86Reg<"ax", 0, [AL,AH]>; 1880b57cec5SDimitry Andricdef DX : X86Reg<"dx", 2, [DL,DH]>; 1890b57cec5SDimitry Andricdef CX : X86Reg<"cx", 1, [CL,CH]>; 1900b57cec5SDimitry Andricdef BX : X86Reg<"bx", 3, [BL,BH]>; 1910b57cec5SDimitry Andric} 1920b57cec5SDimitry Andriclet SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 1930b57cec5SDimitry Andricdef SI : X86Reg<"si", 6, [SIL,SIH]>; 1940b57cec5SDimitry Andricdef DI : X86Reg<"di", 7, [DIL,DIH]>; 1950b57cec5SDimitry Andricdef BP : X86Reg<"bp", 5, [BPL,BPH]>; 1960b57cec5SDimitry Andricdef SP : X86Reg<"sp", 4, [SPL,SPH]>; 1970b57cec5SDimitry Andric} 1980b57cec5SDimitry Andricdef IP : X86Reg<"ip", 0>; 1990b57cec5SDimitry Andric 2000b57cec5SDimitry Andric// X86-64 only, requires REX. 201bdd1243dSDimitry Andriclet SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 2020b57cec5SDimitry Andricdef R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; 2030b57cec5SDimitry Andricdef R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; 2040b57cec5SDimitry Andricdef R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; 2050b57cec5SDimitry Andricdef R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; 2060b57cec5SDimitry Andricdef R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; 2070b57cec5SDimitry Andricdef R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; 2080b57cec5SDimitry Andricdef R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; 2090b57cec5SDimitry Andricdef R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; 2100b57cec5SDimitry Andric} 2115f757f3fSDimitry Andric// APX only, requires REX2 or EVEX. 2125f757f3fSDimitry Andriclet SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 2135f757f3fSDimitry Andriclet PositionOrder = 4 in { 2145f757f3fSDimitry Andricdef R16W : X86Reg<"r16w", 16, [R16B,R16BH]>; 2155f757f3fSDimitry Andricdef R17W : X86Reg<"r17w", 17, [R17B,R17BH]>; 2165f757f3fSDimitry Andricdef R18W : X86Reg<"r18w", 18, [R18B,R18BH]>; 2175f757f3fSDimitry Andricdef R19W : X86Reg<"r19w", 19, [R19B,R19BH]>; 2185f757f3fSDimitry Andricdef R20W : X86Reg<"r20w", 20, [R20B,R20BH]>; 2195f757f3fSDimitry Andricdef R21W : X86Reg<"r21w", 21, [R21B,R21BH]>; 2205f757f3fSDimitry Andricdef R22W : X86Reg<"r22w", 22, [R22B,R22BH]>; 2215f757f3fSDimitry Andricdef R23W : X86Reg<"r23w", 23, [R23B,R23BH]>; 2225f757f3fSDimitry Andricdef R24W : X86Reg<"r24w", 24, [R24B,R24BH]>; 2235f757f3fSDimitry Andricdef R25W : X86Reg<"r25w", 25, [R25B,R25BH]>; 2245f757f3fSDimitry Andricdef R26W : X86Reg<"r26w", 26, [R26B,R26BH]>; 2255f757f3fSDimitry Andricdef R27W : X86Reg<"r27w", 27, [R27B,R27BH]>; 2265f757f3fSDimitry Andricdef R28W : X86Reg<"r28w", 28, [R28B,R28BH]>; 2275f757f3fSDimitry Andricdef R29W : X86Reg<"r29w", 29, [R29B,R29BH]>; 2285f757f3fSDimitry Andricdef R30W : X86Reg<"r30w", 30, [R30B,R30BH]>; 2295f757f3fSDimitry Andricdef R31W : X86Reg<"r31w", 31, [R31B,R31BH]>; 2305f757f3fSDimitry Andric} 2315f757f3fSDimitry Andric} 2320b57cec5SDimitry Andric 2330b57cec5SDimitry Andric// 32-bit registers 2340b57cec5SDimitry Andriclet SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 2350b57cec5SDimitry Andricdef EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; 2360b57cec5SDimitry Andricdef EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; 2370b57cec5SDimitry Andricdef ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; 2380b57cec5SDimitry Andricdef EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; 2390b57cec5SDimitry Andricdef ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; 2400b57cec5SDimitry Andricdef EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; 2410b57cec5SDimitry Andricdef EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; 2420b57cec5SDimitry Andricdef ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; 2430b57cec5SDimitry Andricdef EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; 2440b57cec5SDimitry Andric} 2450b57cec5SDimitry Andric 2460b57cec5SDimitry Andric// X86-64 only, requires REX 247bdd1243dSDimitry Andriclet SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 2480b57cec5SDimitry Andricdef R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; 2490b57cec5SDimitry Andricdef R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; 2500b57cec5SDimitry Andricdef R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; 2510b57cec5SDimitry Andricdef R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; 2520b57cec5SDimitry Andricdef R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; 2530b57cec5SDimitry Andricdef R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; 2540b57cec5SDimitry Andricdef R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; 2550b57cec5SDimitry Andricdef R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; 2560b57cec5SDimitry Andric} 2570b57cec5SDimitry Andric 2585f757f3fSDimitry Andric// APX only, requires REX2 or EVEX. 2595f757f3fSDimitry Andriclet SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 2605f757f3fSDimitry Andriclet PositionOrder = 4 in { 2615f757f3fSDimitry Andricdef R16D : X86Reg<"r16d", 16, [R16W,R16WH]>; 2625f757f3fSDimitry Andricdef R17D : X86Reg<"r17d", 17, [R17W,R17WH]>; 2635f757f3fSDimitry Andricdef R18D : X86Reg<"r18d", 18, [R18W,R18WH]>; 2645f757f3fSDimitry Andricdef R19D : X86Reg<"r19d", 19, [R19W,R19WH]>; 2655f757f3fSDimitry Andricdef R20D : X86Reg<"r20d", 20, [R20W,R20WH]>; 2665f757f3fSDimitry Andricdef R21D : X86Reg<"r21d", 21, [R21W,R21WH]>; 2675f757f3fSDimitry Andricdef R22D : X86Reg<"r22d", 22, [R22W,R22WH]>; 2685f757f3fSDimitry Andricdef R23D : X86Reg<"r23d", 23, [R23W,R23WH]>; 2695f757f3fSDimitry Andricdef R24D : X86Reg<"r24d", 24, [R24W,R24WH]>; 2705f757f3fSDimitry Andricdef R25D : X86Reg<"r25d", 25, [R25W,R25WH]>; 2715f757f3fSDimitry Andricdef R26D : X86Reg<"r26d", 26, [R26W,R26WH]>; 2725f757f3fSDimitry Andricdef R27D : X86Reg<"r27d", 27, [R27W,R27WH]>; 2735f757f3fSDimitry Andricdef R28D : X86Reg<"r28d", 28, [R28W,R28WH]>; 2745f757f3fSDimitry Andricdef R29D : X86Reg<"r29d", 29, [R29W,R29WH]>; 2755f757f3fSDimitry Andricdef R30D : X86Reg<"r30d", 30, [R30W,R30WH]>; 2765f757f3fSDimitry Andricdef R31D : X86Reg<"r31d", 31, [R31W,R31WH]>; 2775f757f3fSDimitry Andric} 2785f757f3fSDimitry Andric} 2790b57cec5SDimitry Andric// 64-bit registers, X86-64 only 2800b57cec5SDimitry Andriclet SubRegIndices = [sub_32bit] in { 2810b57cec5SDimitry Andricdef RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; 2820b57cec5SDimitry Andricdef RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; 2830b57cec5SDimitry Andricdef RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; 2840b57cec5SDimitry Andricdef RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; 2850b57cec5SDimitry Andricdef RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; 2860b57cec5SDimitry Andricdef RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; 2870b57cec5SDimitry Andricdef RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; 2880b57cec5SDimitry Andricdef RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; 2890b57cec5SDimitry Andric 2900b57cec5SDimitry Andric// These also require REX. 2910b57cec5SDimitry Andricdef R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; 2920b57cec5SDimitry Andricdef R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; 2930b57cec5SDimitry Andricdef R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; 2940b57cec5SDimitry Andricdef R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; 2950b57cec5SDimitry Andricdef R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; 2960b57cec5SDimitry Andricdef R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; 2970b57cec5SDimitry Andricdef R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; 2980b57cec5SDimitry Andricdef R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; 2990b57cec5SDimitry Andricdef RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; 3005f757f3fSDimitry Andric// APX only, requires REX2 or EVEX. 3015f757f3fSDimitry Andriclet PositionOrder = 4 in { 3025f757f3fSDimitry Andricdef R16 : X86Reg<"r16", 16, [R16D]>, DwarfRegNum<[130, -2, -2]>; 3035f757f3fSDimitry Andricdef R17 : X86Reg<"r17", 17, [R17D]>, DwarfRegNum<[131, -2, -2]>; 3045f757f3fSDimitry Andricdef R18 : X86Reg<"r18", 18, [R18D]>, DwarfRegNum<[132, -2, -2]>; 3055f757f3fSDimitry Andricdef R19 : X86Reg<"r19", 19, [R19D]>, DwarfRegNum<[133, -2, -2]>; 3065f757f3fSDimitry Andricdef R20 : X86Reg<"r20", 20, [R20D]>, DwarfRegNum<[134, -2, -2]>; 3075f757f3fSDimitry Andricdef R21 : X86Reg<"r21", 21, [R21D]>, DwarfRegNum<[135, -2, -2]>; 3085f757f3fSDimitry Andricdef R22 : X86Reg<"r22", 22, [R22D]>, DwarfRegNum<[136, -2, -2]>; 3095f757f3fSDimitry Andricdef R23 : X86Reg<"r23", 23, [R23D]>, DwarfRegNum<[137, -2, -2]>; 3105f757f3fSDimitry Andricdef R24 : X86Reg<"r24", 24, [R24D]>, DwarfRegNum<[138, -2, -2]>; 3115f757f3fSDimitry Andricdef R25 : X86Reg<"r25", 25, [R25D]>, DwarfRegNum<[139, -2, -2]>; 3125f757f3fSDimitry Andricdef R26 : X86Reg<"r26", 26, [R26D]>, DwarfRegNum<[140, -2, -2]>; 3135f757f3fSDimitry Andricdef R27 : X86Reg<"r27", 27, [R27D]>, DwarfRegNum<[141, -2, -2]>; 3145f757f3fSDimitry Andricdef R28 : X86Reg<"r28", 28, [R28D]>, DwarfRegNum<[142, -2, -2]>; 3155f757f3fSDimitry Andricdef R29 : X86Reg<"r29", 29, [R29D]>, DwarfRegNum<[143, -2, -2]>; 3165f757f3fSDimitry Andricdef R30 : X86Reg<"r30", 30, [R30D]>, DwarfRegNum<[144, -2, -2]>; 3175f757f3fSDimitry Andricdef R31 : X86Reg<"r31", 31, [R31D]>, DwarfRegNum<[145, -2, -2]>; 3185f757f3fSDimitry Andric} 319bdd1243dSDimitry Andric} 3200b57cec5SDimitry Andric 3210b57cec5SDimitry Andric// MMX Registers. These are actually aliased to ST0 .. ST7 3220b57cec5SDimitry Andricdef MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; 3230b57cec5SDimitry Andricdef MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; 3240b57cec5SDimitry Andricdef MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; 3250b57cec5SDimitry Andricdef MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; 3260b57cec5SDimitry Andricdef MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; 3270b57cec5SDimitry Andricdef MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; 3280b57cec5SDimitry Andricdef MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; 3290b57cec5SDimitry Andricdef MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; 3300b57cec5SDimitry Andric 3310b57cec5SDimitry Andric// Pseudo Floating Point registers 3320b57cec5SDimitry Andricdef FP0 : X86Reg<"fp0", 0>; 3330b57cec5SDimitry Andricdef FP1 : X86Reg<"fp1", 0>; 3340b57cec5SDimitry Andricdef FP2 : X86Reg<"fp2", 0>; 3350b57cec5SDimitry Andricdef FP3 : X86Reg<"fp3", 0>; 3360b57cec5SDimitry Andricdef FP4 : X86Reg<"fp4", 0>; 3370b57cec5SDimitry Andricdef FP5 : X86Reg<"fp5", 0>; 3380b57cec5SDimitry Andricdef FP6 : X86Reg<"fp6", 0>; 3390b57cec5SDimitry Andricdef FP7 : X86Reg<"fp7", 0>; 3400b57cec5SDimitry Andric 3410b57cec5SDimitry Andric// XMM Registers, used by the various SSE instruction set extensions. 3420b57cec5SDimitry Andricdef XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; 3430b57cec5SDimitry Andricdef XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; 3440b57cec5SDimitry Andricdef XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; 3450b57cec5SDimitry Andricdef XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; 3460b57cec5SDimitry Andricdef XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; 3470b57cec5SDimitry Andricdef XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; 3480b57cec5SDimitry Andricdef XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; 3490b57cec5SDimitry Andricdef XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; 3500b57cec5SDimitry Andric 3510b57cec5SDimitry Andric// X86-64 only 3520b57cec5SDimitry Andricdef XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; 3530b57cec5SDimitry Andricdef XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; 3540b57cec5SDimitry Andricdef XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; 3550b57cec5SDimitry Andricdef XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; 3560b57cec5SDimitry Andricdef XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; 3570b57cec5SDimitry Andricdef XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; 3580b57cec5SDimitry Andricdef XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; 3590b57cec5SDimitry Andricdef XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; 3600b57cec5SDimitry Andric 3615f757f3fSDimitry Andriclet PositionOrder = 2 in { 3625f757f3fSDimitry Andric// XMM16-31 registers, used by AVX-512 instructions. 3630b57cec5SDimitry Andricdef XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>; 3640b57cec5SDimitry Andricdef XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>; 3650b57cec5SDimitry Andricdef XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>; 3660b57cec5SDimitry Andricdef XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>; 3670b57cec5SDimitry Andricdef XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>; 3680b57cec5SDimitry Andricdef XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>; 3690b57cec5SDimitry Andricdef XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>; 3700b57cec5SDimitry Andricdef XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>; 3710b57cec5SDimitry Andricdef XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>; 3720b57cec5SDimitry Andricdef XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; 3730b57cec5SDimitry Andricdef XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; 3740b57cec5SDimitry Andricdef XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; 3750b57cec5SDimitry Andricdef XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; 3760b57cec5SDimitry Andricdef XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; 3770b57cec5SDimitry Andricdef XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; 3780b57cec5SDimitry Andricdef XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; 3795f757f3fSDimitry Andric} 3800b57cec5SDimitry Andric 3810b57cec5SDimitry Andric// YMM0-15 registers, used by AVX instructions and 3820b57cec5SDimitry Andric// YMM16-31 registers, used by AVX-512 instructions. 3835f757f3fSDimitry Andriclet SubRegIndices = [sub_xmm], PositionOrder = 1 in { 3845f757f3fSDimitry Andric foreach Index = 0-15 in { 3855f757f3fSDimitry Andric def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, 3865f757f3fSDimitry Andric DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 3875f757f3fSDimitry Andric } 3885f757f3fSDimitry Andric} 3895f757f3fSDimitry Andriclet SubRegIndices = [sub_xmm], PositionOrder = 2 in { 3905f757f3fSDimitry Andric foreach Index = 16-31 in { 3910b57cec5SDimitry Andric def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, 3920b57cec5SDimitry Andric DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 3930b57cec5SDimitry Andric } 3940b57cec5SDimitry Andric} 3950b57cec5SDimitry Andric 3965f757f3fSDimitry Andric 3970b57cec5SDimitry Andric// ZMM Registers, used by AVX-512 instructions. 3985f757f3fSDimitry Andriclet SubRegIndices = [sub_ymm], PositionOrder = 2 in { 3990b57cec5SDimitry Andric foreach Index = 0-31 in { 4000b57cec5SDimitry Andric def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>, 4010b57cec5SDimitry Andric DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 4020b57cec5SDimitry Andric } 4030b57cec5SDimitry Andric} 4040b57cec5SDimitry Andric 4055f757f3fSDimitry Andriclet PositionOrder = 2 in { 4060b57cec5SDimitry Andric// Mask Registers, used by AVX-512 instructions. 4070b57cec5SDimitry Andricdef K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; 4080b57cec5SDimitry Andricdef K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; 4090b57cec5SDimitry Andricdef K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; 4100b57cec5SDimitry Andricdef K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; 4110b57cec5SDimitry Andricdef K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; 4120b57cec5SDimitry Andricdef K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; 4130b57cec5SDimitry Andricdef K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; 4140b57cec5SDimitry Andricdef K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; 4155f757f3fSDimitry Andric// Mask register pairs 4165f757f3fSDimitry Andricdef KPAIRS : RegisterTuples<[sub_mask_0, sub_mask_1], 4175f757f3fSDimitry Andric [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>; 4185f757f3fSDimitry Andric} 4195f757f3fSDimitry Andric 4205f757f3fSDimitry Andric// TMM registers, used by AMX instructions. 4215f757f3fSDimitry Andriclet PositionOrder = 3 in { 4225f757f3fSDimitry Andric// Tile config registers. 4235f757f3fSDimitry Andricdef TMMCFG: X86Reg<"tmmcfg", 0>; 4245f757f3fSDimitry Andric// Tile "registers". 4255f757f3fSDimitry Andricdef TMM0: X86Reg<"tmm0", 0>; 4265f757f3fSDimitry Andricdef TMM1: X86Reg<"tmm1", 1>; 4275f757f3fSDimitry Andricdef TMM2: X86Reg<"tmm2", 2>; 4285f757f3fSDimitry Andricdef TMM3: X86Reg<"tmm3", 3>; 4295f757f3fSDimitry Andricdef TMM4: X86Reg<"tmm4", 4>; 4305f757f3fSDimitry Andricdef TMM5: X86Reg<"tmm5", 5>; 4315f757f3fSDimitry Andricdef TMM6: X86Reg<"tmm6", 6>; 4325f757f3fSDimitry Andricdef TMM7: X86Reg<"tmm7", 7>; 4335f757f3fSDimitry Andric} 4340b57cec5SDimitry Andric 4350b57cec5SDimitry Andric// Floating point stack registers. These don't map one-to-one to the FP 4360b57cec5SDimitry Andric// pseudo registers, but we still mark them as aliasing FP registers. That 4370b57cec5SDimitry Andric// way both kinds can be live without exceeding the stack depth. ST registers 4380b57cec5SDimitry Andric// are only live around inline assembly. 4390b57cec5SDimitry Andricdef ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>; 4400b57cec5SDimitry Andricdef ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; 4410b57cec5SDimitry Andricdef ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; 4420b57cec5SDimitry Andricdef ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; 4430b57cec5SDimitry Andricdef ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; 4440b57cec5SDimitry Andricdef ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; 4450b57cec5SDimitry Andricdef ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; 4460b57cec5SDimitry Andricdef ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; 4470b57cec5SDimitry Andric 4480b57cec5SDimitry Andric// Floating-point status word 4490b57cec5SDimitry Andricdef FPSW : X86Reg<"fpsr", 0>; 4500b57cec5SDimitry Andric 4510b57cec5SDimitry Andric// Floating-point control word 4520b57cec5SDimitry Andricdef FPCW : X86Reg<"fpcr", 0>; 4530b57cec5SDimitry Andric 454480093f4SDimitry Andric// SIMD Floating-point control register. 455480093f4SDimitry Andric// Note: We only model the "Uses" of the control bits: current rounding modes, 456480093f4SDimitry Andric// DAZ, FTZ and exception masks. We don't model the "Defs" of flag bits. 457480093f4SDimitry Andricdef MXCSR : X86Reg<"mxcsr", 0>; 458480093f4SDimitry Andric 4590b57cec5SDimitry Andric// Status flags register. 4600b57cec5SDimitry Andric// 4610b57cec5SDimitry Andric// Note that some flags that are commonly thought of as part of the status 4620b57cec5SDimitry Andric// flags register are modeled separately. Typically this is due to instructions 4630b57cec5SDimitry Andric// reading and updating those flags independently of all the others. We don't 4640b57cec5SDimitry Andric// want to create false dependencies between these instructions and so we use 4650b57cec5SDimitry Andric// a separate register to model them. 466bdd1243dSDimitry Andricdef EFLAGS : X86Reg<"flags", 0>, DwarfRegNum<[49, 9, 9]>; 467bdd1243dSDimitry Andricdef _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>; 468bdd1243dSDimitry Andricdef RFLAGS : X86Reg<"rflags", 0>, DwarfRegNum<[49, -2, -2]>; 4690b57cec5SDimitry Andric 4700b57cec5SDimitry Andric// The direction flag. 4710b57cec5SDimitry Andricdef DF : X86Reg<"dirflag", 0>; 4720b57cec5SDimitry Andric 4730b57cec5SDimitry Andric 4740b57cec5SDimitry Andric// Segment registers 47506c3fb27SDimitry Andricdef CS : X86Reg<"cs", 1>, DwarfRegNum<[51, -2, 41]>; 47606c3fb27SDimitry Andricdef DS : X86Reg<"ds", 3>, DwarfRegNum<[53, -2, 43]>; 47706c3fb27SDimitry Andricdef SS : X86Reg<"ss", 2>, DwarfRegNum<[52, -2, 42]>; 47806c3fb27SDimitry Andricdef ES : X86Reg<"es", 0>, DwarfRegNum<[50, -2, 40]>; 47906c3fb27SDimitry Andricdef FS : X86Reg<"fs", 4>, DwarfRegNum<[54, -2, 44]>; 48006c3fb27SDimitry Andricdef GS : X86Reg<"gs", 5>, DwarfRegNum<[55, -2, 45]>; 4810b57cec5SDimitry Andric 482bdd1243dSDimitry Andricdef FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>; 483bdd1243dSDimitry Andricdef GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>; 484bdd1243dSDimitry Andric 4850b57cec5SDimitry Andric// Debug registers 4860b57cec5SDimitry Andricdef DR0 : X86Reg<"dr0", 0>; 4870b57cec5SDimitry Andricdef DR1 : X86Reg<"dr1", 1>; 4880b57cec5SDimitry Andricdef DR2 : X86Reg<"dr2", 2>; 4890b57cec5SDimitry Andricdef DR3 : X86Reg<"dr3", 3>; 4900b57cec5SDimitry Andricdef DR4 : X86Reg<"dr4", 4>; 4910b57cec5SDimitry Andricdef DR5 : X86Reg<"dr5", 5>; 4920b57cec5SDimitry Andricdef DR6 : X86Reg<"dr6", 6>; 4930b57cec5SDimitry Andricdef DR7 : X86Reg<"dr7", 7>; 4940b57cec5SDimitry Andricdef DR8 : X86Reg<"dr8", 8>; 4950b57cec5SDimitry Andricdef DR9 : X86Reg<"dr9", 9>; 4960b57cec5SDimitry Andricdef DR10 : X86Reg<"dr10", 10>; 4970b57cec5SDimitry Andricdef DR11 : X86Reg<"dr11", 11>; 4980b57cec5SDimitry Andricdef DR12 : X86Reg<"dr12", 12>; 4990b57cec5SDimitry Andricdef DR13 : X86Reg<"dr13", 13>; 5000b57cec5SDimitry Andricdef DR14 : X86Reg<"dr14", 14>; 5010b57cec5SDimitry Andricdef DR15 : X86Reg<"dr15", 15>; 5020b57cec5SDimitry Andric 5030b57cec5SDimitry Andric// Control registers 5040b57cec5SDimitry Andricdef CR0 : X86Reg<"cr0", 0>; 5050b57cec5SDimitry Andricdef CR1 : X86Reg<"cr1", 1>; 5060b57cec5SDimitry Andricdef CR2 : X86Reg<"cr2", 2>; 5070b57cec5SDimitry Andricdef CR3 : X86Reg<"cr3", 3>; 5080b57cec5SDimitry Andricdef CR4 : X86Reg<"cr4", 4>; 5090b57cec5SDimitry Andricdef CR5 : X86Reg<"cr5", 5>; 5100b57cec5SDimitry Andricdef CR6 : X86Reg<"cr6", 6>; 5110b57cec5SDimitry Andricdef CR7 : X86Reg<"cr7", 7>; 5120b57cec5SDimitry Andricdef CR8 : X86Reg<"cr8", 8>; 5130b57cec5SDimitry Andricdef CR9 : X86Reg<"cr9", 9>; 5140b57cec5SDimitry Andricdef CR10 : X86Reg<"cr10", 10>; 5150b57cec5SDimitry Andricdef CR11 : X86Reg<"cr11", 11>; 5160b57cec5SDimitry Andricdef CR12 : X86Reg<"cr12", 12>; 5170b57cec5SDimitry Andricdef CR13 : X86Reg<"cr13", 13>; 5180b57cec5SDimitry Andricdef CR14 : X86Reg<"cr14", 14>; 5190b57cec5SDimitry Andricdef CR15 : X86Reg<"cr15", 15>; 5200b57cec5SDimitry Andric 5210b57cec5SDimitry Andric// Pseudo index registers 5220b57cec5SDimitry Andricdef EIZ : X86Reg<"eiz", 4>; 5230b57cec5SDimitry Andricdef RIZ : X86Reg<"riz", 4>; 5240b57cec5SDimitry Andric 5250b57cec5SDimitry Andric// CET registers - Shadow Stack Pointer 5260b57cec5SDimitry Andricdef SSP : X86Reg<"ssp", 0>; 5270b57cec5SDimitry Andric 5280b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 5290b57cec5SDimitry Andric// Register Class Definitions... now that we have all of the pieces, define the 5300b57cec5SDimitry Andric// top-level register classes. The order specified in the register list is 5310b57cec5SDimitry Andric// implicitly defined to be the register allocation order. 5320b57cec5SDimitry Andric// 5330b57cec5SDimitry Andric 5340b57cec5SDimitry Andric// List call-clobbered registers before callee-save registers. RBX, RBP, (and 5350b57cec5SDimitry Andric// R12, R13, R14, and R15 for X86-64) are callee-save registers. 5360b57cec5SDimitry Andric// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 5370b57cec5SDimitry Andric// R8B, ... R15B. 5380b57cec5SDimitry Andric// Allocate R12 and R13 last, as these require an extra byte when 5390b57cec5SDimitry Andric// encoded in x86_64 instructions. 5400b57cec5SDimitry Andric// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 5410b57cec5SDimitry Andric// 64-bit mode. The main complication is that they cannot be encoded in an 5420b57cec5SDimitry Andric// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 5430b57cec5SDimitry Andric// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 5440b57cec5SDimitry Andric// cannot be encoded. 5450b57cec5SDimitry Andricdef GR8 : RegisterClass<"X86", [i8], 8, 5460b57cec5SDimitry Andric (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 5475f757f3fSDimitry Andric R8B, R9B, R10B, R11B, R16B, R17B, R18B, R19B, R20B, 5485f757f3fSDimitry Andric R21B, R22B, R23B, R24B, R25B, R26B, R27B, R28B, R29B, 5495f757f3fSDimitry Andric R30B, R31B, R14B, R15B, R12B, R13B)> { 5500b57cec5SDimitry Andric let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 5510b57cec5SDimitry Andric let AltOrderSelect = [{ 5520b57cec5SDimitry Andric return MF.getSubtarget<X86Subtarget>().is64Bit(); 5530b57cec5SDimitry Andric }]; 5540b57cec5SDimitry Andric} 5550b57cec5SDimitry Andric 5560b57cec5SDimitry Andriclet isAllocatable = 0 in 5570b57cec5SDimitry Andricdef GRH8 : RegisterClass<"X86", [i8], 8, 5580b57cec5SDimitry Andric (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH, 5595f757f3fSDimitry Andric R12BH, R13BH, R14BH, R15BH, R16BH, R17BH, R18BH, 5605f757f3fSDimitry Andric R19BH, R20BH, R21BH, R22BH, R23BH, R24BH, R25BH, 5615f757f3fSDimitry Andric R26BH, R27BH, R28BH, R29BH, R30BH, R31BH)>; 5620b57cec5SDimitry Andricdef GR16 : RegisterClass<"X86", [i16], 16, 5635f757f3fSDimitry Andric (add AX, CX, DX, SI, DI, BX, BP, SP, R8W, R9W, R10W, 5645f757f3fSDimitry Andric R11W, R16W, R17W, R18W, R19W, R20W, R21W, R22W, R23W, 5655f757f3fSDimitry Andric R24W, R25W, R26W, R27W, R28W, R29W, R30W, R31W, R14W, 5665f757f3fSDimitry Andric R15W, R12W, R13W)>; 5670b57cec5SDimitry Andric 5680b57cec5SDimitry Andriclet isAllocatable = 0 in 5690b57cec5SDimitry Andricdef GRH16 : RegisterClass<"X86", [i16], 16, 5705f757f3fSDimitry Andric (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, R8WH, 5715f757f3fSDimitry Andric R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, R15WH, R16WH, 5725f757f3fSDimitry Andric R17WH, R18WH, R19WH, R20WH, R21WH, R22WH, R23WH, R24WH, 5735f757f3fSDimitry Andric R25WH, R26WH, R27WH, R28WH, R29WH, R30WH, R31WH)>; 5740b57cec5SDimitry Andricdef GR32 : RegisterClass<"X86", [i32], 32, 5755f757f3fSDimitry Andric (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, R8D, R9D, 5765f757f3fSDimitry Andric R10D, R11D, R16D, R17D, R18D, R19D, R20D, R21D, R22D, 5775f757f3fSDimitry Andric R23D, R24D, R25D, R26D, R27D, R28D, R29D, R30D, R31D, 5785f757f3fSDimitry Andric R14D, R15D, R12D, R13D)>; 5790b57cec5SDimitry Andric 5800b57cec5SDimitry Andric// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 5810b57cec5SDimitry Andric// RIP isn't really a register and it can't be used anywhere except in an 5820b57cec5SDimitry Andric// address, but it doesn't cause trouble. 5830b57cec5SDimitry Andric// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra 5840b57cec5SDimitry Andric// tests because of the inclusion of RIP in this register class. 5850b57cec5SDimitry Andricdef GR64 : RegisterClass<"X86", [i64], 64, 5865f757f3fSDimitry Andric (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17, 5875f757f3fSDimitry Andric R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, 5885f757f3fSDimitry Andric R30, R31, RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 5890b57cec5SDimitry Andric 5900eae32dcSDimitry Andric// GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when 5910eae32dcSDimitry Andric// emitting code for intrinsics, which use implict input registers. 5920eae32dcSDimitry Andricdef GR64PLTSafe : RegisterClass<"X86", [i64], 64, 5930eae32dcSDimitry Andric (add RAX, RCX, RDX, RSI, RDI, R8, R9, 5940eae32dcSDimitry Andric RBX, R14, R15, R12, R13, RBP)>; 595349cc55cSDimitry Andric 59606c3fb27SDimitry Andric// It includes the GPR that are used as scratch register for Linux64 calling 59706c3fb27SDimitry Andric// convention. 59806c3fb27SDimitry Andricdef GR64_ArgRef: RegisterClass<"X86", [i64], 64, (add R10, R11)> { 59906c3fb27SDimitry Andric let GeneratePressureSet = 0; 60006c3fb27SDimitry Andric} 60106c3fb27SDimitry Andric 60206c3fb27SDimitry Andric// It includes the GPR that are used as scratch register for Linux32 calling 60306c3fb27SDimitry Andric// convention. 60406c3fb27SDimitry Andricdef GR32_ArgRef: RegisterClass<"X86", [i32], 32, (add ECX, EDX)> { 60506c3fb27SDimitry Andric let GeneratePressureSet = 0; 60606c3fb27SDimitry Andric} 60706c3fb27SDimitry Andric 6080b57cec5SDimitry Andric// Segment registers for use by MOV instructions (and others) that have a 6090b57cec5SDimitry Andric// segment register as one operand. Always contain a 16-bit segment 6100b57cec5SDimitry Andric// descriptor. 6110b57cec5SDimitry Andricdef SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 6120b57cec5SDimitry Andric 6130b57cec5SDimitry Andric// Debug registers. 6140b57cec5SDimitry Andricdef DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; 6150b57cec5SDimitry Andric 6160b57cec5SDimitry Andric// Control registers. 6170b57cec5SDimitry Andricdef CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 6180b57cec5SDimitry Andric 6190b57cec5SDimitry Andric// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 6200b57cec5SDimitry Andric// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 6210b57cec5SDimitry Andric// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 6220b57cec5SDimitry Andric// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 6230b57cec5SDimitry Andric// and GR64_ABCD are classes for registers that support 8-bit h-register 6240b57cec5SDimitry Andric// operations. 6250b57cec5SDimitry Andricdef GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 6260b57cec5SDimitry Andricdef GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 6270b57cec5SDimitry Andricdef GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; 6280b57cec5SDimitry Andricdef GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 6290b57cec5SDimitry Andricdef GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 6300b57cec5SDimitry Andricdef GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>; 6310b57cec5SDimitry Andricdef GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 6320b57cec5SDimitry Andric R8, R9, R11, RIP, RSP)>; 6330b57cec5SDimitry Andricdef GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 6340b57cec5SDimitry Andric R8, R9, R10, R11, 6350b57cec5SDimitry Andric RIP, RSP)>; 6360b57cec5SDimitry Andric 6370b57cec5SDimitry Andric// GR8_NOREX - GR8 registers which do not require a REX prefix. 6380b57cec5SDimitry Andricdef GR8_NOREX : RegisterClass<"X86", [i8], 8, 6390b57cec5SDimitry Andric (add AL, CL, DL, AH, CH, DH, BL, BH)> { 6400b57cec5SDimitry Andric let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 6410b57cec5SDimitry Andric let AltOrderSelect = [{ 6420b57cec5SDimitry Andric return MF.getSubtarget<X86Subtarget>().is64Bit(); 6430b57cec5SDimitry Andric }]; 6440b57cec5SDimitry Andric} 6450b57cec5SDimitry Andric// GR16_NOREX - GR16 registers which do not require a REX prefix. 6460b57cec5SDimitry Andricdef GR16_NOREX : RegisterClass<"X86", [i16], 16, 6470b57cec5SDimitry Andric (add AX, CX, DX, SI, DI, BX, BP, SP)>; 6480b57cec5SDimitry Andric// GR32_NOREX - GR32 registers which do not require a REX prefix. 6490b57cec5SDimitry Andricdef GR32_NOREX : RegisterClass<"X86", [i32], 32, 6500b57cec5SDimitry Andric (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 6510b57cec5SDimitry Andric// GR64_NOREX - GR64 registers which do not require a REX prefix. 6520b57cec5SDimitry Andricdef GR64_NOREX : RegisterClass<"X86", [i64], 64, 6530b57cec5SDimitry Andric (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 6545f757f3fSDimitry Andric// GeneratePressureSet = 0 here is a temporary workaround for lots of 6555f757f3fSDimitry Andric// LIT fail. Whether enabling in the future still needs discussion. 6565f757f3fSDimitry Andriclet GeneratePressureSet = 0 in { 6575f757f3fSDimitry Andric// GR8_NOREX2 - GR8 registers which do not require a REX2 prefix. 6585f757f3fSDimitry Andricdef GR8_NOREX2 : RegisterClass<"X86", [i8], 8, 6595f757f3fSDimitry Andric (sub GR8, (sequence "R%uB", 16, 31))> { 6605f757f3fSDimitry Andric let AltOrders = [(sub GR8_NOREX2, AH, BH, CH, DH)]; 6615f757f3fSDimitry Andric let AltOrderSelect = [{ 6625f757f3fSDimitry Andric return MF.getSubtarget<X86Subtarget>().is64Bit(); 6635f757f3fSDimitry Andric }]; 6645f757f3fSDimitry Andric} 6655f757f3fSDimitry Andric// GR16_NOREX2 - GR16 registers which do not require a REX2 prefix. 6665f757f3fSDimitry Andricdef GR16_NOREX2 : RegisterClass<"X86", [i16], 16, 6675f757f3fSDimitry Andric (sub GR16, (sequence "R%uW", 16, 31))>; 6685f757f3fSDimitry Andric// GR32_NOREX2 - GR32 registers which do not require a REX2 prefix. 6695f757f3fSDimitry Andricdef GR32_NOREX2 : RegisterClass<"X86", [i32], 32, 6705f757f3fSDimitry Andric (sub GR32, (sequence "R%uD", 16, 31))>; 6715f757f3fSDimitry Andric// GR64_NOREX2 - GR64 registers which do not require a REX2 prefix. 6725f757f3fSDimitry Andricdef GR64_NOREX2 : RegisterClass<"X86", [i64], 64, 6735f757f3fSDimitry Andric (sub GR64, (sequence "R%u", 16, 31))>; 6745f757f3fSDimitry Andric} 6750b57cec5SDimitry Andric 6760b57cec5SDimitry Andric// GR32_NOSP - GR32 registers except ESP. 6770b57cec5SDimitry Andricdef GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 6780b57cec5SDimitry Andric 6790b57cec5SDimitry Andric// GR64_NOSP - GR64 registers except RSP (and RIP). 6800b57cec5SDimitry Andricdef GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 6810b57cec5SDimitry Andric 6820b57cec5SDimitry Andric// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 6830b57cec5SDimitry Andric// ESP. 6840b57cec5SDimitry Andricdef GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 6850b57cec5SDimitry Andric (and GR32_NOREX, GR32_NOSP)>; 6860b57cec5SDimitry Andric 6870b57cec5SDimitry Andric// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 6880b57cec5SDimitry Andricdef GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 6890b57cec5SDimitry Andric (and GR64_NOREX, GR64_NOSP)>; 6905f757f3fSDimitry Andriclet GeneratePressureSet = 0 in { 6915f757f3fSDimitry Andric// GR32_NOREX2_NOSP - GR32_NOREX2 registers except ESP. 6925f757f3fSDimitry Andricdef GR32_NOREX2_NOSP : RegisterClass<"X86", [i32], 32, 6935f757f3fSDimitry Andric (sub GR32_NOREX2, ESP)>; 6945f757f3fSDimitry Andric 6955f757f3fSDimitry Andric// GR64_NOREX2_NOSP - GR64_NOREX2 registers except RSP, RIP. 6965f757f3fSDimitry Andricdef GR64_NOREX2_NOSP : RegisterClass<"X86", [i64], 64, 6975f757f3fSDimitry Andric (sub GR64_NOREX2, RSP, RIP)>; 6985f757f3fSDimitry Andric} 6990b57cec5SDimitry Andric 7000b57cec5SDimitry Andric// Register classes used for ABIs that use 32-bit address accesses, 7015f757f3fSDimitry Andric// while using the whole x86_64 ISA. 7020b57cec5SDimitry Andric 7030b57cec5SDimitry Andric// In such cases, it is fine to use RIP as we are sure the 32 high 7040b57cec5SDimitry Andric// bits are not set. We do not need variants for NOSP as RIP is not 7050b57cec5SDimitry Andric// allowed there. 7060b57cec5SDimitry Andric// RIP is not spilled anywhere for now, so stick to 32-bit alignment 7070b57cec5SDimitry Andric// to save on memory space. 7080b57cec5SDimitry Andric// FIXME: We could allow all 64bit registers, but we would need 7090b57cec5SDimitry Andric// something to check that the 32 high bits are not set, 7100b57cec5SDimitry Andric// which we do not have right now. 7110b57cec5SDimitry Andricdef LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; 7120b57cec5SDimitry Andric 7135ffd83dbSDimitry Andric// When RBP is used as a base pointer in a 32-bit addresses environment, 7140b57cec5SDimitry Andric// this is also safe to use the full register to access addresses. 7150b57cec5SDimitry Andric// Since RBP will never be spilled, stick to a 32 alignment to save 7160b57cec5SDimitry Andric// on memory consumption. 7170b57cec5SDimitry Andricdef LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, 7180b57cec5SDimitry Andric (add LOW32_ADDR_ACCESS, RBP)>; 7190b57cec5SDimitry Andric 7200b57cec5SDimitry Andric// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. 7210b57cec5SDimitry Andricdef GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; 7220b57cec5SDimitry Andricdef GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>; 7230b57cec5SDimitry Andric 7240b57cec5SDimitry Andric// Classes to support the 64-bit assembler constraint tied to a fixed 7250b57cec5SDimitry Andric// register in 32-bit mode. The second register is always the next in 7260b57cec5SDimitry Andric// the list. Wrap around causes an error. 7270b57cec5SDimitry Andricdef GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>; 7280b57cec5SDimitry Andricdef GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>; 7290b57cec5SDimitry Andricdef GR32_BSI : RegisterClass<"X86", [i32], 32, (add EBX, ESI)>; 7300b57cec5SDimitry Andricdef GR32_SIDI : RegisterClass<"X86", [i32], 32, (add ESI, EDI)>; 7310b57cec5SDimitry Andricdef GR32_DIBP : RegisterClass<"X86", [i32], 32, (add EDI, EBP)>; 7320b57cec5SDimitry Andricdef GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>; 7330b57cec5SDimitry Andric 7340b57cec5SDimitry Andric// Scalar SSE2 floating point registers. 7350b57cec5SDimitry Andricdef FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 7360b57cec5SDimitry Andric 7370b57cec5SDimitry Andricdef FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 7380b57cec5SDimitry Andric 73981ad6265SDimitry Andricdef FR16 : RegisterClass<"X86", [f16], 16, (add FR32)> {let Size = 32;} 74081ad6265SDimitry Andric 7410b57cec5SDimitry Andric 7420b57cec5SDimitry Andric// FIXME: This sets up the floating point register files as though they are f64 7430b57cec5SDimitry Andric// values, though they really are f80 values. This will cause us to spill 7440b57cec5SDimitry Andric// values as 64-bit quantities instead of 80-bit quantities, which is much much 7450b57cec5SDimitry Andric// faster on common hardware. In reality, this should be controlled by a 7460b57cec5SDimitry Andric// command line option or something. 7470b57cec5SDimitry Andric 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andricdef RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 7500b57cec5SDimitry Andricdef RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 7510b57cec5SDimitry Andricdef RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 7520b57cec5SDimitry Andric 7530b57cec5SDimitry Andric// st(7) may be is not allocatable. 7540b57cec5SDimitry Andricdef RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> { 7550b57cec5SDimitry Andric let isAllocatable = 0; 7560b57cec5SDimitry Andric} 7570b57cec5SDimitry Andric 7580b57cec5SDimitry Andric// Floating point stack registers (these are not allocatable by the 7590b57cec5SDimitry Andric// register allocator - the floating point stackifier is responsible 7600b57cec5SDimitry Andric// for transforming FPn allocations to STn registers) 7610b57cec5SDimitry Andricdef RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 7620b57cec5SDimitry Andric let isAllocatable = 0; 7630b57cec5SDimitry Andric} 7640b57cec5SDimitry Andric 7650b57cec5SDimitry Andric// Helper to allow %st to print as %st(0) when its encoded in the instruction. 7660b57cec5SDimitry Andricdef RSTi : RegisterOperand<RST, "printSTiRegOperand">; 7670b57cec5SDimitry Andric 7680b57cec5SDimitry Andric// Generic vector registers: VR64 and VR128. 7690b57cec5SDimitry Andric// Ensure that float types are declared first - only float is legal on SSE1. 7700b57cec5SDimitry Andricdef VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 771bdd1243dSDimitry Andricdef VR128 : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128], 7720b57cec5SDimitry Andric 128, (add FR32)>; 773bdd1243dSDimitry Andricdef VR256 : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64], 7740b57cec5SDimitry Andric 256, (sequence "YMM%u", 0, 15)>; 7750b57cec5SDimitry Andric 7760b57cec5SDimitry Andric// Status flags registers. 7770b57cec5SDimitry Andricdef CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 7780b57cec5SDimitry Andric let CopyCost = -1; // Don't allow copying of status registers. 7790b57cec5SDimitry Andric let isAllocatable = 0; 7800b57cec5SDimitry Andric} 7810b57cec5SDimitry Andricdef FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { 7820b57cec5SDimitry Andric let CopyCost = -1; // Don't allow copying of status registers. 7830b57cec5SDimitry Andric let isAllocatable = 0; 7840b57cec5SDimitry Andric} 7850b57cec5SDimitry Andricdef DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> { 7860b57cec5SDimitry Andric let CopyCost = -1; // Don't allow copying of status registers. 7870b57cec5SDimitry Andric let isAllocatable = 0; 7880b57cec5SDimitry Andric} 7890b57cec5SDimitry Andric 7900b57cec5SDimitry Andric// AVX-512 vector/mask registers. 791bdd1243dSDimitry Andricdef VR512 : RegisterClass<"X86", [v16f32, v8f64, v32f16, v32bf16, v64i8, v32i16, v16i32, v8i64], 7920b57cec5SDimitry Andric 512, (sequence "ZMM%u", 0, 31)>; 7930b57cec5SDimitry Andric 7940b57cec5SDimitry Andric// Represents the lower 16 registers that have VEX/legacy encodable subregs. 7950b57cec5SDimitry Andricdef VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 7960b57cec5SDimitry Andric 512, (sequence "ZMM%u", 0, 15)>; 7970b57cec5SDimitry Andric 7980b57cec5SDimitry Andric// Scalar AVX-512 floating point registers. 7990b57cec5SDimitry Andricdef FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; 8000b57cec5SDimitry Andric 8010b57cec5SDimitry Andricdef FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; 8020b57cec5SDimitry Andric 80381ad6265SDimitry Andricdef FR16X : RegisterClass<"X86", [f16], 16, (add FR32X)> {let Size = 32;} 804349cc55cSDimitry Andric 8050b57cec5SDimitry Andric// Extended VR128 and VR256 for AVX-512 instructions 806bdd1243dSDimitry Andricdef VR128X : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128], 8070b57cec5SDimitry Andric 128, (add FR32X)>; 808bdd1243dSDimitry Andricdef VR256X : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64], 8090b57cec5SDimitry Andric 256, (sequence "YMM%u", 0, 31)>; 8100b57cec5SDimitry Andric 8110b57cec5SDimitry Andric// Mask registers 8120b57cec5SDimitry Andricdef VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} 8130b57cec5SDimitry Andricdef VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} 8140b57cec5SDimitry Andricdef VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} 8150b57cec5SDimitry Andricdef VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} 8160b57cec5SDimitry Andricdef VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} 8170b57cec5SDimitry Andricdef VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} 8180b57cec5SDimitry Andricdef VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} 8190b57cec5SDimitry Andric 8200b57cec5SDimitry Andricdef VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 8210b57cec5SDimitry Andricdef VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 8220b57cec5SDimitry Andricdef VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 8230b57cec5SDimitry Andricdef VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 8240b57cec5SDimitry Andricdef VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 8250b57cec5SDimitry Andric 8260b57cec5SDimitry Andricdef VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;} 8270b57cec5SDimitry Andricdef VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} 8280b57cec5SDimitry Andricdef VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} 8290b57cec5SDimitry Andricdef VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} 8300b57cec5SDimitry Andricdef VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} 8310b57cec5SDimitry Andricdef VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} 8320b57cec5SDimitry Andricdef VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} 8330b57cec5SDimitry Andric 8345ffd83dbSDimitry Andric// Tiles 835e8d8bef9SDimitry Andriclet CopyCost = -1 in // Don't allow copying of tile registers 836e8d8bef9SDimitry Andricdef TILE : RegisterClass<"X86", [x86amx], 8192, 8375ffd83dbSDimitry Andric (sequence "TMM%u", 0, 7)> {let Size = 8192;} 83881ad6265SDimitry Andric 83981ad6265SDimitry Andric//===----------------------------------------------------------------------===// 84081ad6265SDimitry Andric// Register categories. 84181ad6265SDimitry Andric// 84281ad6265SDimitry Andric 84381ad6265SDimitry Andric// The TILE and VK*PAIR registers may not be "fixed", but we don't want them 84481ad6265SDimitry Andric// anyway. 84581ad6265SDimitry Andricdef FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR, 84681ad6265SDimitry Andric DFCCR, TILE, VK1PAIR, VK2PAIR, VK4PAIR, 84781ad6265SDimitry Andric VK8PAIR, VK16PAIR]>; 84881ad6265SDimitry Andricdef GeneralPurposeRegisters : RegisterCategory<[GR64, GR32, GR16, GR8]>; 849