10b57cec5SDimitry Andric//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file describes the X86 Register file, defining the registers themselves, 100b57cec5SDimitry Andric// aliases between the registers, and the register classes built out of the 110b57cec5SDimitry Andric// registers. 120b57cec5SDimitry Andric// 130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andricclass X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { 160b57cec5SDimitry Andric let Namespace = "X86"; 170b57cec5SDimitry Andric let HWEncoding = Enc; 180b57cec5SDimitry Andric let SubRegs = subregs; 190b57cec5SDimitry Andric} 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric// Subregister indices. 220b57cec5SDimitry Andriclet Namespace = "X86" in { 230b57cec5SDimitry Andric def sub_8bit : SubRegIndex<8>; 240b57cec5SDimitry Andric def sub_8bit_hi : SubRegIndex<8, 8>; 250b57cec5SDimitry Andric def sub_8bit_hi_phony : SubRegIndex<8, 8>; 260b57cec5SDimitry Andric def sub_16bit : SubRegIndex<16>; 270b57cec5SDimitry Andric def sub_16bit_hi : SubRegIndex<16, 16>; 280b57cec5SDimitry Andric def sub_32bit : SubRegIndex<32>; 290b57cec5SDimitry Andric def sub_xmm : SubRegIndex<128>; 300b57cec5SDimitry Andric def sub_ymm : SubRegIndex<256>; 310b57cec5SDimitry Andric def sub_mask_0 : SubRegIndex<-1>; 320b57cec5SDimitry Andric def sub_mask_1 : SubRegIndex<-1, -1>; 330b57cec5SDimitry Andric} 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 360b57cec5SDimitry Andric// Register definitions... 370b57cec5SDimitry Andric// 380b57cec5SDimitry Andric 390b57cec5SDimitry Andric// In the register alias definitions below, we define which registers alias 400b57cec5SDimitry Andric// which others. We only specify which registers the small registers alias, 410b57cec5SDimitry Andric// because the register file generator is smart enough to figure out that 420b57cec5SDimitry Andric// AL aliases AX if we tell it that AX aliased AL (for example). 430b57cec5SDimitry Andric 440b57cec5SDimitry Andric// Dwarf numbering is different for 32-bit and 64-bit, and there are 450b57cec5SDimitry Andric// variations by target as well. Currently the first entry is for X86-64, 460b57cec5SDimitry Andric// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 470b57cec5SDimitry Andric// and debug information on X86-32/Darwin) 480b57cec5SDimitry Andric 490b57cec5SDimitry Andric// 8-bit registers 500b57cec5SDimitry Andric// Low registers 510b57cec5SDimitry Andricdef AL : X86Reg<"al", 0>; 520b57cec5SDimitry Andricdef DL : X86Reg<"dl", 2>; 530b57cec5SDimitry Andricdef CL : X86Reg<"cl", 1>; 540b57cec5SDimitry Andricdef BL : X86Reg<"bl", 3>; 550b57cec5SDimitry Andric 560b57cec5SDimitry Andric// High registers. On x86-64, these cannot be used in any instruction 570b57cec5SDimitry Andric// with a REX prefix. 580b57cec5SDimitry Andricdef AH : X86Reg<"ah", 4>; 590b57cec5SDimitry Andricdef DH : X86Reg<"dh", 6>; 600b57cec5SDimitry Andricdef CH : X86Reg<"ch", 5>; 610b57cec5SDimitry Andricdef BH : X86Reg<"bh", 7>; 620b57cec5SDimitry Andric 630b57cec5SDimitry Andric// X86-64 only, requires REX. 640b57cec5SDimitry Andriclet CostPerUse = 1 in { 650b57cec5SDimitry Andricdef SIL : X86Reg<"sil", 6>; 660b57cec5SDimitry Andricdef DIL : X86Reg<"dil", 7>; 670b57cec5SDimitry Andricdef BPL : X86Reg<"bpl", 5>; 680b57cec5SDimitry Andricdef SPL : X86Reg<"spl", 4>; 690b57cec5SDimitry Andricdef R8B : X86Reg<"r8b", 8>; 700b57cec5SDimitry Andricdef R9B : X86Reg<"r9b", 9>; 710b57cec5SDimitry Andricdef R10B : X86Reg<"r10b", 10>; 720b57cec5SDimitry Andricdef R11B : X86Reg<"r11b", 11>; 730b57cec5SDimitry Andricdef R12B : X86Reg<"r12b", 12>; 740b57cec5SDimitry Andricdef R13B : X86Reg<"r13b", 13>; 750b57cec5SDimitry Andricdef R14B : X86Reg<"r14b", 14>; 760b57cec5SDimitry Andricdef R15B : X86Reg<"r15b", 15>; 770b57cec5SDimitry Andric} 780b57cec5SDimitry Andric 790b57cec5SDimitry Andriclet isArtificial = 1 in { 800b57cec5SDimitry Andric// High byte of the low 16 bits of the super-register: 810b57cec5SDimitry Andricdef SIH : X86Reg<"", -1>; 820b57cec5SDimitry Andricdef DIH : X86Reg<"", -1>; 830b57cec5SDimitry Andricdef BPH : X86Reg<"", -1>; 840b57cec5SDimitry Andricdef SPH : X86Reg<"", -1>; 850b57cec5SDimitry Andricdef R8BH : X86Reg<"", -1>; 860b57cec5SDimitry Andricdef R9BH : X86Reg<"", -1>; 870b57cec5SDimitry Andricdef R10BH : X86Reg<"", -1>; 880b57cec5SDimitry Andricdef R11BH : X86Reg<"", -1>; 890b57cec5SDimitry Andricdef R12BH : X86Reg<"", -1>; 900b57cec5SDimitry Andricdef R13BH : X86Reg<"", -1>; 910b57cec5SDimitry Andricdef R14BH : X86Reg<"", -1>; 920b57cec5SDimitry Andricdef R15BH : X86Reg<"", -1>; 930b57cec5SDimitry Andric// High word of the low 32 bits of the super-register: 940b57cec5SDimitry Andricdef HAX : X86Reg<"", -1>; 950b57cec5SDimitry Andricdef HDX : X86Reg<"", -1>; 960b57cec5SDimitry Andricdef HCX : X86Reg<"", -1>; 970b57cec5SDimitry Andricdef HBX : X86Reg<"", -1>; 980b57cec5SDimitry Andricdef HSI : X86Reg<"", -1>; 990b57cec5SDimitry Andricdef HDI : X86Reg<"", -1>; 1000b57cec5SDimitry Andricdef HBP : X86Reg<"", -1>; 1010b57cec5SDimitry Andricdef HSP : X86Reg<"", -1>; 1020b57cec5SDimitry Andricdef HIP : X86Reg<"", -1>; 1030b57cec5SDimitry Andricdef R8WH : X86Reg<"", -1>; 1040b57cec5SDimitry Andricdef R9WH : X86Reg<"", -1>; 1050b57cec5SDimitry Andricdef R10WH : X86Reg<"", -1>; 1060b57cec5SDimitry Andricdef R11WH : X86Reg<"", -1>; 1070b57cec5SDimitry Andricdef R12WH : X86Reg<"", -1>; 1080b57cec5SDimitry Andricdef R13WH : X86Reg<"", -1>; 1090b57cec5SDimitry Andricdef R14WH : X86Reg<"", -1>; 1100b57cec5SDimitry Andricdef R15WH : X86Reg<"", -1>; 1110b57cec5SDimitry Andric} 1120b57cec5SDimitry Andric 1130b57cec5SDimitry Andric// 16-bit registers 1140b57cec5SDimitry Andriclet SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { 1150b57cec5SDimitry Andricdef AX : X86Reg<"ax", 0, [AL,AH]>; 1160b57cec5SDimitry Andricdef DX : X86Reg<"dx", 2, [DL,DH]>; 1170b57cec5SDimitry Andricdef CX : X86Reg<"cx", 1, [CL,CH]>; 1180b57cec5SDimitry Andricdef BX : X86Reg<"bx", 3, [BL,BH]>; 1190b57cec5SDimitry Andric} 1200b57cec5SDimitry Andriclet SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 1210b57cec5SDimitry Andricdef SI : X86Reg<"si", 6, [SIL,SIH]>; 1220b57cec5SDimitry Andricdef DI : X86Reg<"di", 7, [DIL,DIH]>; 1230b57cec5SDimitry Andricdef BP : X86Reg<"bp", 5, [BPL,BPH]>; 1240b57cec5SDimitry Andricdef SP : X86Reg<"sp", 4, [SPL,SPH]>; 1250b57cec5SDimitry Andric} 1260b57cec5SDimitry Andricdef IP : X86Reg<"ip", 0>; 1270b57cec5SDimitry Andric 1280b57cec5SDimitry Andric// X86-64 only, requires REX. 1290b57cec5SDimitry Andriclet SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = 1, 1300b57cec5SDimitry Andric CoveredBySubRegs = 1 in { 1310b57cec5SDimitry Andricdef R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; 1320b57cec5SDimitry Andricdef R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; 1330b57cec5SDimitry Andricdef R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; 1340b57cec5SDimitry Andricdef R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; 1350b57cec5SDimitry Andricdef R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; 1360b57cec5SDimitry Andricdef R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; 1370b57cec5SDimitry Andricdef R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; 1380b57cec5SDimitry Andricdef R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; 1390b57cec5SDimitry Andric} 1400b57cec5SDimitry Andric 1410b57cec5SDimitry Andric// 32-bit registers 1420b57cec5SDimitry Andriclet SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 1430b57cec5SDimitry Andricdef EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; 1440b57cec5SDimitry Andricdef EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; 1450b57cec5SDimitry Andricdef ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; 1460b57cec5SDimitry Andricdef EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; 1470b57cec5SDimitry Andricdef ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; 1480b57cec5SDimitry Andricdef EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; 1490b57cec5SDimitry Andricdef EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; 1500b57cec5SDimitry Andricdef ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; 1510b57cec5SDimitry Andricdef EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; 1520b57cec5SDimitry Andric} 1530b57cec5SDimitry Andric 1540b57cec5SDimitry Andric// X86-64 only, requires REX 1550b57cec5SDimitry Andriclet SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = 1, 1560b57cec5SDimitry Andric CoveredBySubRegs = 1 in { 1570b57cec5SDimitry Andricdef R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; 1580b57cec5SDimitry Andricdef R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; 1590b57cec5SDimitry Andricdef R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; 1600b57cec5SDimitry Andricdef R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; 1610b57cec5SDimitry Andricdef R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; 1620b57cec5SDimitry Andricdef R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; 1630b57cec5SDimitry Andricdef R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; 1640b57cec5SDimitry Andricdef R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; 1650b57cec5SDimitry Andric} 1660b57cec5SDimitry Andric 1670b57cec5SDimitry Andric// 64-bit registers, X86-64 only 1680b57cec5SDimitry Andriclet SubRegIndices = [sub_32bit] in { 1690b57cec5SDimitry Andricdef RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; 1700b57cec5SDimitry Andricdef RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; 1710b57cec5SDimitry Andricdef RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; 1720b57cec5SDimitry Andricdef RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; 1730b57cec5SDimitry Andricdef RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; 1740b57cec5SDimitry Andricdef RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; 1750b57cec5SDimitry Andricdef RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; 1760b57cec5SDimitry Andricdef RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; 1770b57cec5SDimitry Andric 1780b57cec5SDimitry Andric// These also require REX. 1790b57cec5SDimitry Andriclet CostPerUse = 1 in { 1800b57cec5SDimitry Andricdef R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; 1810b57cec5SDimitry Andricdef R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; 1820b57cec5SDimitry Andricdef R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; 1830b57cec5SDimitry Andricdef R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; 1840b57cec5SDimitry Andricdef R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; 1850b57cec5SDimitry Andricdef R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; 1860b57cec5SDimitry Andricdef R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; 1870b57cec5SDimitry Andricdef R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; 1880b57cec5SDimitry Andricdef RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; 1890b57cec5SDimitry Andric}} 1900b57cec5SDimitry Andric 1910b57cec5SDimitry Andric// MMX Registers. These are actually aliased to ST0 .. ST7 1920b57cec5SDimitry Andricdef MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; 1930b57cec5SDimitry Andricdef MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; 1940b57cec5SDimitry Andricdef MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; 1950b57cec5SDimitry Andricdef MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; 1960b57cec5SDimitry Andricdef MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; 1970b57cec5SDimitry Andricdef MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; 1980b57cec5SDimitry Andricdef MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; 1990b57cec5SDimitry Andricdef MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; 2000b57cec5SDimitry Andric 2010b57cec5SDimitry Andric// Pseudo Floating Point registers 2020b57cec5SDimitry Andricdef FP0 : X86Reg<"fp0", 0>; 2030b57cec5SDimitry Andricdef FP1 : X86Reg<"fp1", 0>; 2040b57cec5SDimitry Andricdef FP2 : X86Reg<"fp2", 0>; 2050b57cec5SDimitry Andricdef FP3 : X86Reg<"fp3", 0>; 2060b57cec5SDimitry Andricdef FP4 : X86Reg<"fp4", 0>; 2070b57cec5SDimitry Andricdef FP5 : X86Reg<"fp5", 0>; 2080b57cec5SDimitry Andricdef FP6 : X86Reg<"fp6", 0>; 2090b57cec5SDimitry Andricdef FP7 : X86Reg<"fp7", 0>; 2100b57cec5SDimitry Andric 2110b57cec5SDimitry Andric// XMM Registers, used by the various SSE instruction set extensions. 2120b57cec5SDimitry Andricdef XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; 2130b57cec5SDimitry Andricdef XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; 2140b57cec5SDimitry Andricdef XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; 2150b57cec5SDimitry Andricdef XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; 2160b57cec5SDimitry Andricdef XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; 2170b57cec5SDimitry Andricdef XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; 2180b57cec5SDimitry Andricdef XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; 2190b57cec5SDimitry Andricdef XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; 2200b57cec5SDimitry Andric 2210b57cec5SDimitry Andric// X86-64 only 2220b57cec5SDimitry Andriclet CostPerUse = 1 in { 2230b57cec5SDimitry Andricdef XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; 2240b57cec5SDimitry Andricdef XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; 2250b57cec5SDimitry Andricdef XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; 2260b57cec5SDimitry Andricdef XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; 2270b57cec5SDimitry Andricdef XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; 2280b57cec5SDimitry Andricdef XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; 2290b57cec5SDimitry Andricdef XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; 2300b57cec5SDimitry Andricdef XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; 2310b57cec5SDimitry Andric 2320b57cec5SDimitry Andricdef XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>; 2330b57cec5SDimitry Andricdef XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>; 2340b57cec5SDimitry Andricdef XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>; 2350b57cec5SDimitry Andricdef XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>; 2360b57cec5SDimitry Andricdef XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>; 2370b57cec5SDimitry Andricdef XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>; 2380b57cec5SDimitry Andricdef XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>; 2390b57cec5SDimitry Andricdef XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>; 2400b57cec5SDimitry Andricdef XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>; 2410b57cec5SDimitry Andricdef XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; 2420b57cec5SDimitry Andricdef XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; 2430b57cec5SDimitry Andricdef XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; 2440b57cec5SDimitry Andricdef XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; 2450b57cec5SDimitry Andricdef XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; 2460b57cec5SDimitry Andricdef XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; 2470b57cec5SDimitry Andricdef XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; 2480b57cec5SDimitry Andric 2490b57cec5SDimitry Andric} // CostPerUse 2500b57cec5SDimitry Andric 2510b57cec5SDimitry Andric// YMM0-15 registers, used by AVX instructions and 2520b57cec5SDimitry Andric// YMM16-31 registers, used by AVX-512 instructions. 2530b57cec5SDimitry Andriclet SubRegIndices = [sub_xmm] in { 2540b57cec5SDimitry Andric foreach Index = 0-31 in { 2550b57cec5SDimitry Andric def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, 2560b57cec5SDimitry Andric DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 2570b57cec5SDimitry Andric } 2580b57cec5SDimitry Andric} 2590b57cec5SDimitry Andric 2600b57cec5SDimitry Andric// ZMM Registers, used by AVX-512 instructions. 2610b57cec5SDimitry Andriclet SubRegIndices = [sub_ymm] in { 2620b57cec5SDimitry Andric foreach Index = 0-31 in { 2630b57cec5SDimitry Andric def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>, 2640b57cec5SDimitry Andric DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 2650b57cec5SDimitry Andric } 2660b57cec5SDimitry Andric} 2670b57cec5SDimitry Andric 2680b57cec5SDimitry Andric// Mask Registers, used by AVX-512 instructions. 2690b57cec5SDimitry Andricdef K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; 2700b57cec5SDimitry Andricdef K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; 2710b57cec5SDimitry Andricdef K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; 2720b57cec5SDimitry Andricdef K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; 2730b57cec5SDimitry Andricdef K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; 2740b57cec5SDimitry Andricdef K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; 2750b57cec5SDimitry Andricdef K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; 2760b57cec5SDimitry Andricdef K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; 2770b57cec5SDimitry Andric 2780b57cec5SDimitry Andric// Floating point stack registers. These don't map one-to-one to the FP 2790b57cec5SDimitry Andric// pseudo registers, but we still mark them as aliasing FP registers. That 2800b57cec5SDimitry Andric// way both kinds can be live without exceeding the stack depth. ST registers 2810b57cec5SDimitry Andric// are only live around inline assembly. 2820b57cec5SDimitry Andricdef ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>; 2830b57cec5SDimitry Andricdef ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; 2840b57cec5SDimitry Andricdef ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; 2850b57cec5SDimitry Andricdef ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; 2860b57cec5SDimitry Andricdef ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; 2870b57cec5SDimitry Andricdef ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; 2880b57cec5SDimitry Andricdef ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; 2890b57cec5SDimitry Andricdef ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; 2900b57cec5SDimitry Andric 2910b57cec5SDimitry Andric// Floating-point status word 2920b57cec5SDimitry Andricdef FPSW : X86Reg<"fpsr", 0>; 2930b57cec5SDimitry Andric 2940b57cec5SDimitry Andric// Floating-point control word 2950b57cec5SDimitry Andricdef FPCW : X86Reg<"fpcr", 0>; 2960b57cec5SDimitry Andric 2970b57cec5SDimitry Andric// Status flags register. 2980b57cec5SDimitry Andric// 2990b57cec5SDimitry Andric// Note that some flags that are commonly thought of as part of the status 3000b57cec5SDimitry Andric// flags register are modeled separately. Typically this is due to instructions 3010b57cec5SDimitry Andric// reading and updating those flags independently of all the others. We don't 3020b57cec5SDimitry Andric// want to create false dependencies between these instructions and so we use 3030b57cec5SDimitry Andric// a separate register to model them. 3040b57cec5SDimitry Andricdef EFLAGS : X86Reg<"flags", 0>; 3050b57cec5SDimitry Andric 3060b57cec5SDimitry Andric// The direction flag. 3070b57cec5SDimitry Andricdef DF : X86Reg<"dirflag", 0>; 3080b57cec5SDimitry Andric 3090b57cec5SDimitry Andric 3100b57cec5SDimitry Andric// Segment registers 3110b57cec5SDimitry Andricdef CS : X86Reg<"cs", 1>; 3120b57cec5SDimitry Andricdef DS : X86Reg<"ds", 3>; 3130b57cec5SDimitry Andricdef SS : X86Reg<"ss", 2>; 3140b57cec5SDimitry Andricdef ES : X86Reg<"es", 0>; 3150b57cec5SDimitry Andricdef FS : X86Reg<"fs", 4>; 3160b57cec5SDimitry Andricdef GS : X86Reg<"gs", 5>; 3170b57cec5SDimitry Andric 3180b57cec5SDimitry Andric// Debug registers 3190b57cec5SDimitry Andricdef DR0 : X86Reg<"dr0", 0>; 3200b57cec5SDimitry Andricdef DR1 : X86Reg<"dr1", 1>; 3210b57cec5SDimitry Andricdef DR2 : X86Reg<"dr2", 2>; 3220b57cec5SDimitry Andricdef DR3 : X86Reg<"dr3", 3>; 3230b57cec5SDimitry Andricdef DR4 : X86Reg<"dr4", 4>; 3240b57cec5SDimitry Andricdef DR5 : X86Reg<"dr5", 5>; 3250b57cec5SDimitry Andricdef DR6 : X86Reg<"dr6", 6>; 3260b57cec5SDimitry Andricdef DR7 : X86Reg<"dr7", 7>; 3270b57cec5SDimitry Andricdef DR8 : X86Reg<"dr8", 8>; 3280b57cec5SDimitry Andricdef DR9 : X86Reg<"dr9", 9>; 3290b57cec5SDimitry Andricdef DR10 : X86Reg<"dr10", 10>; 3300b57cec5SDimitry Andricdef DR11 : X86Reg<"dr11", 11>; 3310b57cec5SDimitry Andricdef DR12 : X86Reg<"dr12", 12>; 3320b57cec5SDimitry Andricdef DR13 : X86Reg<"dr13", 13>; 3330b57cec5SDimitry Andricdef DR14 : X86Reg<"dr14", 14>; 3340b57cec5SDimitry Andricdef DR15 : X86Reg<"dr15", 15>; 3350b57cec5SDimitry Andric 3360b57cec5SDimitry Andric// Control registers 3370b57cec5SDimitry Andricdef CR0 : X86Reg<"cr0", 0>; 3380b57cec5SDimitry Andricdef CR1 : X86Reg<"cr1", 1>; 3390b57cec5SDimitry Andricdef CR2 : X86Reg<"cr2", 2>; 3400b57cec5SDimitry Andricdef CR3 : X86Reg<"cr3", 3>; 3410b57cec5SDimitry Andricdef CR4 : X86Reg<"cr4", 4>; 3420b57cec5SDimitry Andricdef CR5 : X86Reg<"cr5", 5>; 3430b57cec5SDimitry Andricdef CR6 : X86Reg<"cr6", 6>; 3440b57cec5SDimitry Andricdef CR7 : X86Reg<"cr7", 7>; 3450b57cec5SDimitry Andricdef CR8 : X86Reg<"cr8", 8>; 3460b57cec5SDimitry Andricdef CR9 : X86Reg<"cr9", 9>; 3470b57cec5SDimitry Andricdef CR10 : X86Reg<"cr10", 10>; 3480b57cec5SDimitry Andricdef CR11 : X86Reg<"cr11", 11>; 3490b57cec5SDimitry Andricdef CR12 : X86Reg<"cr12", 12>; 3500b57cec5SDimitry Andricdef CR13 : X86Reg<"cr13", 13>; 3510b57cec5SDimitry Andricdef CR14 : X86Reg<"cr14", 14>; 3520b57cec5SDimitry Andricdef CR15 : X86Reg<"cr15", 15>; 3530b57cec5SDimitry Andric 3540b57cec5SDimitry Andric// Pseudo index registers 3550b57cec5SDimitry Andricdef EIZ : X86Reg<"eiz", 4>; 3560b57cec5SDimitry Andricdef RIZ : X86Reg<"riz", 4>; 3570b57cec5SDimitry Andric 3580b57cec5SDimitry Andric// Bound registers, used in MPX instructions 3590b57cec5SDimitry Andricdef BND0 : X86Reg<"bnd0", 0>; 3600b57cec5SDimitry Andricdef BND1 : X86Reg<"bnd1", 1>; 3610b57cec5SDimitry Andricdef BND2 : X86Reg<"bnd2", 2>; 3620b57cec5SDimitry Andricdef BND3 : X86Reg<"bnd3", 3>; 3630b57cec5SDimitry Andric 3640b57cec5SDimitry Andric// CET registers - Shadow Stack Pointer 3650b57cec5SDimitry Andricdef SSP : X86Reg<"ssp", 0>; 3660b57cec5SDimitry Andric 3670b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 3680b57cec5SDimitry Andric// Register Class Definitions... now that we have all of the pieces, define the 3690b57cec5SDimitry Andric// top-level register classes. The order specified in the register list is 3700b57cec5SDimitry Andric// implicitly defined to be the register allocation order. 3710b57cec5SDimitry Andric// 3720b57cec5SDimitry Andric 3730b57cec5SDimitry Andric// List call-clobbered registers before callee-save registers. RBX, RBP, (and 3740b57cec5SDimitry Andric// R12, R13, R14, and R15 for X86-64) are callee-save registers. 3750b57cec5SDimitry Andric// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 3760b57cec5SDimitry Andric// R8B, ... R15B. 3770b57cec5SDimitry Andric// Allocate R12 and R13 last, as these require an extra byte when 3780b57cec5SDimitry Andric// encoded in x86_64 instructions. 3790b57cec5SDimitry Andric// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 3800b57cec5SDimitry Andric// 64-bit mode. The main complication is that they cannot be encoded in an 3810b57cec5SDimitry Andric// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 3820b57cec5SDimitry Andric// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 3830b57cec5SDimitry Andric// cannot be encoded. 3840b57cec5SDimitry Andricdef GR8 : RegisterClass<"X86", [i8], 8, 3850b57cec5SDimitry Andric (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 3860b57cec5SDimitry Andric R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { 3870b57cec5SDimitry Andric let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 3880b57cec5SDimitry Andric let AltOrderSelect = [{ 3890b57cec5SDimitry Andric return MF.getSubtarget<X86Subtarget>().is64Bit(); 3900b57cec5SDimitry Andric }]; 3910b57cec5SDimitry Andric} 3920b57cec5SDimitry Andric 3930b57cec5SDimitry Andriclet isAllocatable = 0 in 3940b57cec5SDimitry Andricdef GRH8 : RegisterClass<"X86", [i8], 8, 3950b57cec5SDimitry Andric (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH, 3960b57cec5SDimitry Andric R12BH, R13BH, R14BH, R15BH)>; 3970b57cec5SDimitry Andric 3980b57cec5SDimitry Andricdef GR16 : RegisterClass<"X86", [i16], 16, 3990b57cec5SDimitry Andric (add AX, CX, DX, SI, DI, BX, BP, SP, 4000b57cec5SDimitry Andric R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; 4010b57cec5SDimitry Andric 4020b57cec5SDimitry Andriclet isAllocatable = 0 in 4030b57cec5SDimitry Andricdef GRH16 : RegisterClass<"X86", [i16], 16, 4040b57cec5SDimitry Andric (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, 4050b57cec5SDimitry Andric R8WH, R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, 4060b57cec5SDimitry Andric R15WH)>; 4070b57cec5SDimitry Andric 4080b57cec5SDimitry Andricdef GR32 : RegisterClass<"X86", [i32], 32, 4090b57cec5SDimitry Andric (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 4100b57cec5SDimitry Andric R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; 4110b57cec5SDimitry Andric 4120b57cec5SDimitry Andric// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 4130b57cec5SDimitry Andric// RIP isn't really a register and it can't be used anywhere except in an 4140b57cec5SDimitry Andric// address, but it doesn't cause trouble. 4150b57cec5SDimitry Andric// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra 4160b57cec5SDimitry Andric// tests because of the inclusion of RIP in this register class. 4170b57cec5SDimitry Andricdef GR64 : RegisterClass<"X86", [i64], 64, 4180b57cec5SDimitry Andric (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 4190b57cec5SDimitry Andric RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 4200b57cec5SDimitry Andric 4210b57cec5SDimitry Andric// Segment registers for use by MOV instructions (and others) that have a 4220b57cec5SDimitry Andric// segment register as one operand. Always contain a 16-bit segment 4230b57cec5SDimitry Andric// descriptor. 4240b57cec5SDimitry Andricdef SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 4250b57cec5SDimitry Andric 4260b57cec5SDimitry Andric// Debug registers. 4270b57cec5SDimitry Andricdef DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; 4280b57cec5SDimitry Andric 4290b57cec5SDimitry Andric// Control registers. 4300b57cec5SDimitry Andricdef CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 4310b57cec5SDimitry Andric 4320b57cec5SDimitry Andric// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 4330b57cec5SDimitry Andric// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 4340b57cec5SDimitry Andric// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 4350b57cec5SDimitry Andric// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 4360b57cec5SDimitry Andric// and GR64_ABCD are classes for registers that support 8-bit h-register 4370b57cec5SDimitry Andric// operations. 4380b57cec5SDimitry Andricdef GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 4390b57cec5SDimitry Andricdef GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 4400b57cec5SDimitry Andricdef GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; 4410b57cec5SDimitry Andricdef GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 4420b57cec5SDimitry Andricdef GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 4430b57cec5SDimitry Andricdef GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>; 4440b57cec5SDimitry Andricdef GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 4450b57cec5SDimitry Andric R8, R9, R11, RIP, RSP)>; 4460b57cec5SDimitry Andricdef GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 4470b57cec5SDimitry Andric R8, R9, R10, R11, 4480b57cec5SDimitry Andric RIP, RSP)>; 4490b57cec5SDimitry Andric 4500b57cec5SDimitry Andric// GR8_NOREX - GR8 registers which do not require a REX prefix. 4510b57cec5SDimitry Andricdef GR8_NOREX : RegisterClass<"X86", [i8], 8, 4520b57cec5SDimitry Andric (add AL, CL, DL, AH, CH, DH, BL, BH)> { 4530b57cec5SDimitry Andric let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 4540b57cec5SDimitry Andric let AltOrderSelect = [{ 4550b57cec5SDimitry Andric return MF.getSubtarget<X86Subtarget>().is64Bit(); 4560b57cec5SDimitry Andric }]; 4570b57cec5SDimitry Andric} 4580b57cec5SDimitry Andric// GR16_NOREX - GR16 registers which do not require a REX prefix. 4590b57cec5SDimitry Andricdef GR16_NOREX : RegisterClass<"X86", [i16], 16, 4600b57cec5SDimitry Andric (add AX, CX, DX, SI, DI, BX, BP, SP)>; 4610b57cec5SDimitry Andric// GR32_NOREX - GR32 registers which do not require a REX prefix. 4620b57cec5SDimitry Andricdef GR32_NOREX : RegisterClass<"X86", [i32], 32, 4630b57cec5SDimitry Andric (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 4640b57cec5SDimitry Andric// GR64_NOREX - GR64 registers which do not require a REX prefix. 4650b57cec5SDimitry Andricdef GR64_NOREX : RegisterClass<"X86", [i64], 64, 4660b57cec5SDimitry Andric (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 4670b57cec5SDimitry Andric 4680b57cec5SDimitry Andric// GR32_NOSP - GR32 registers except ESP. 4690b57cec5SDimitry Andricdef GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 4700b57cec5SDimitry Andric 4710b57cec5SDimitry Andric// GR64_NOSP - GR64 registers except RSP (and RIP). 4720b57cec5SDimitry Andricdef GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 4730b57cec5SDimitry Andric 4740b57cec5SDimitry Andric// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 4750b57cec5SDimitry Andric// ESP. 4760b57cec5SDimitry Andricdef GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 4770b57cec5SDimitry Andric (and GR32_NOREX, GR32_NOSP)>; 4780b57cec5SDimitry Andric 4790b57cec5SDimitry Andric// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 4800b57cec5SDimitry Andricdef GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 4810b57cec5SDimitry Andric (and GR64_NOREX, GR64_NOSP)>; 4820b57cec5SDimitry Andric 4830b57cec5SDimitry Andric// Register classes used for ABIs that use 32-bit address accesses, 4840b57cec5SDimitry Andric// while using the whole x84_64 ISA. 4850b57cec5SDimitry Andric 4860b57cec5SDimitry Andric// In such cases, it is fine to use RIP as we are sure the 32 high 4870b57cec5SDimitry Andric// bits are not set. We do not need variants for NOSP as RIP is not 4880b57cec5SDimitry Andric// allowed there. 4890b57cec5SDimitry Andric// RIP is not spilled anywhere for now, so stick to 32-bit alignment 4900b57cec5SDimitry Andric// to save on memory space. 4910b57cec5SDimitry Andric// FIXME: We could allow all 64bit registers, but we would need 4920b57cec5SDimitry Andric// something to check that the 32 high bits are not set, 4930b57cec5SDimitry Andric// which we do not have right now. 4940b57cec5SDimitry Andricdef LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; 4950b57cec5SDimitry Andric 4960b57cec5SDimitry Andric// When RBP is used as a base pointer in a 32-bit addresses environement, 4970b57cec5SDimitry Andric// this is also safe to use the full register to access addresses. 4980b57cec5SDimitry Andric// Since RBP will never be spilled, stick to a 32 alignment to save 4990b57cec5SDimitry Andric// on memory consumption. 5000b57cec5SDimitry Andricdef LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, 5010b57cec5SDimitry Andric (add LOW32_ADDR_ACCESS, RBP)>; 5020b57cec5SDimitry Andric 5030b57cec5SDimitry Andric// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. 5040b57cec5SDimitry Andricdef GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; 5050b57cec5SDimitry Andricdef GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>; 5060b57cec5SDimitry Andric 5070b57cec5SDimitry Andric// Classes to support the 64-bit assembler constraint tied to a fixed 5080b57cec5SDimitry Andric// register in 32-bit mode. The second register is always the next in 5090b57cec5SDimitry Andric// the list. Wrap around causes an error. 5100b57cec5SDimitry Andricdef GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>; 5110b57cec5SDimitry Andricdef GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>; 5120b57cec5SDimitry Andricdef GR32_BSI : RegisterClass<"X86", [i32], 32, (add EBX, ESI)>; 5130b57cec5SDimitry Andricdef GR32_SIDI : RegisterClass<"X86", [i32], 32, (add ESI, EDI)>; 5140b57cec5SDimitry Andricdef GR32_DIBP : RegisterClass<"X86", [i32], 32, (add EDI, EBP)>; 5150b57cec5SDimitry Andricdef GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>; 5160b57cec5SDimitry Andric 5170b57cec5SDimitry Andric// Scalar SSE2 floating point registers. 5180b57cec5SDimitry Andricdef FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 5190b57cec5SDimitry Andric 5200b57cec5SDimitry Andricdef FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 5210b57cec5SDimitry Andric 5220b57cec5SDimitry Andric 5230b57cec5SDimitry Andric// FIXME: This sets up the floating point register files as though they are f64 5240b57cec5SDimitry Andric// values, though they really are f80 values. This will cause us to spill 5250b57cec5SDimitry Andric// values as 64-bit quantities instead of 80-bit quantities, which is much much 5260b57cec5SDimitry Andric// faster on common hardware. In reality, this should be controlled by a 5270b57cec5SDimitry Andric// command line option or something. 5280b57cec5SDimitry Andric 5290b57cec5SDimitry Andric 5300b57cec5SDimitry Andricdef RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 5310b57cec5SDimitry Andricdef RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 5320b57cec5SDimitry Andricdef RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 5330b57cec5SDimitry Andric 5340b57cec5SDimitry Andric// st(7) may be is not allocatable. 5350b57cec5SDimitry Andricdef RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> { 5360b57cec5SDimitry Andric let isAllocatable = 0; 5370b57cec5SDimitry Andric} 5380b57cec5SDimitry Andric 5390b57cec5SDimitry Andric// Floating point stack registers (these are not allocatable by the 5400b57cec5SDimitry Andric// register allocator - the floating point stackifier is responsible 5410b57cec5SDimitry Andric// for transforming FPn allocations to STn registers) 5420b57cec5SDimitry Andricdef RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 5430b57cec5SDimitry Andric let isAllocatable = 0; 5440b57cec5SDimitry Andric} 5450b57cec5SDimitry Andric 5460b57cec5SDimitry Andric// Helper to allow %st to print as %st(0) when its encoded in the instruction. 5470b57cec5SDimitry Andricdef RSTi : RegisterOperand<RST, "printSTiRegOperand">; 5480b57cec5SDimitry Andric 5490b57cec5SDimitry Andric// Generic vector registers: VR64 and VR128. 5500b57cec5SDimitry Andric// Ensure that float types are declared first - only float is legal on SSE1. 5510b57cec5SDimitry Andricdef VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 5520b57cec5SDimitry Andricdef VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 5530b57cec5SDimitry Andric 128, (add FR32)>; 5540b57cec5SDimitry Andricdef VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 5550b57cec5SDimitry Andric 256, (sequence "YMM%u", 0, 15)>; 5560b57cec5SDimitry Andric 5570b57cec5SDimitry Andric// Status flags registers. 5580b57cec5SDimitry Andricdef CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 5590b57cec5SDimitry Andric let CopyCost = -1; // Don't allow copying of status registers. 5600b57cec5SDimitry Andric let isAllocatable = 0; 5610b57cec5SDimitry Andric} 5620b57cec5SDimitry Andricdef FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { 5630b57cec5SDimitry Andric let CopyCost = -1; // Don't allow copying of status registers. 5640b57cec5SDimitry Andric let isAllocatable = 0; 5650b57cec5SDimitry Andric} 5660b57cec5SDimitry Andricdef DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> { 5670b57cec5SDimitry Andric let CopyCost = -1; // Don't allow copying of status registers. 5680b57cec5SDimitry Andric let isAllocatable = 0; 5690b57cec5SDimitry Andric} 5700b57cec5SDimitry Andric 5710b57cec5SDimitry Andric// AVX-512 vector/mask registers. 5720b57cec5SDimitry Andricdef VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 5730b57cec5SDimitry Andric 512, (sequence "ZMM%u", 0, 31)>; 5740b57cec5SDimitry Andric 5750b57cec5SDimitry Andric// Represents the lower 16 registers that have VEX/legacy encodable subregs. 5760b57cec5SDimitry Andricdef VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 5770b57cec5SDimitry Andric 512, (sequence "ZMM%u", 0, 15)>; 5780b57cec5SDimitry Andric 5790b57cec5SDimitry Andric// Scalar AVX-512 floating point registers. 5800b57cec5SDimitry Andricdef FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; 5810b57cec5SDimitry Andric 5820b57cec5SDimitry Andricdef FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; 5830b57cec5SDimitry Andric 5840b57cec5SDimitry Andric// Extended VR128 and VR256 for AVX-512 instructions 5850b57cec5SDimitry Andricdef VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 5860b57cec5SDimitry Andric 128, (add FR32X)>; 5870b57cec5SDimitry Andricdef VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 5880b57cec5SDimitry Andric 256, (sequence "YMM%u", 0, 31)>; 5890b57cec5SDimitry Andric 5900b57cec5SDimitry Andric// Mask registers 5910b57cec5SDimitry Andricdef VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} 5920b57cec5SDimitry Andricdef VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} 5930b57cec5SDimitry Andricdef VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} 5940b57cec5SDimitry Andricdef VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} 5950b57cec5SDimitry Andricdef VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} 5960b57cec5SDimitry Andricdef VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} 5970b57cec5SDimitry Andricdef VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} 5980b57cec5SDimitry Andric 5990b57cec5SDimitry Andric// Mask register pairs 6000b57cec5SDimitry Andricdef KPAIRS : RegisterTuples<[sub_mask_0, sub_mask_1], 6010b57cec5SDimitry Andric [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>; 6020b57cec5SDimitry Andric 6030b57cec5SDimitry Andricdef VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 6040b57cec5SDimitry Andricdef VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 6050b57cec5SDimitry Andricdef VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 6060b57cec5SDimitry Andricdef VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 6070b57cec5SDimitry Andricdef VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 6080b57cec5SDimitry Andric 6090b57cec5SDimitry Andricdef VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;} 6100b57cec5SDimitry Andricdef VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} 6110b57cec5SDimitry Andricdef VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} 6120b57cec5SDimitry Andricdef VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} 6130b57cec5SDimitry Andricdef VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} 6140b57cec5SDimitry Andricdef VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} 6150b57cec5SDimitry Andricdef VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} 6160b57cec5SDimitry Andric 6170b57cec5SDimitry Andric// Bound registers 6180b57cec5SDimitry Andricdef BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; 619