1//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 Register file, defining the registers themselves, 10// aliases between the registers, and the register classes built out of the 11// registers. 12// 13//===----------------------------------------------------------------------===// 14 15class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { 16 let Namespace = "X86"; 17 let HWEncoding = Enc; 18 let SubRegs = subregs; 19} 20 21// Subregister indices. 22let Namespace = "X86" in { 23 def sub_8bit : SubRegIndex<8>; 24 def sub_8bit_hi : SubRegIndex<8, 8>; 25 def sub_8bit_hi_phony : SubRegIndex<8, 8>; 26 def sub_16bit : SubRegIndex<16>; 27 def sub_16bit_hi : SubRegIndex<16, 16>; 28 def sub_32bit : SubRegIndex<32>; 29 def sub_xmm : SubRegIndex<128>; 30 def sub_ymm : SubRegIndex<256>; 31 def sub_mask_0 : SubRegIndex<-1>; 32 def sub_mask_1 : SubRegIndex<-1, -1>; 33} 34 35//===----------------------------------------------------------------------===// 36// Register definitions... 37// 38 39// In the register alias definitions below, we define which registers alias 40// which others. We only specify which registers the small registers alias, 41// because the register file generator is smart enough to figure out that 42// AL aliases AX if we tell it that AX aliased AL (for example). 43 44// Dwarf numbering is different for 32-bit and 64-bit, and there are 45// variations by target as well. Currently the first entry is for X86-64, 46// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 47// and debug information on X86-32/Darwin) 48 49// 8-bit registers 50// Low registers 51def AL : X86Reg<"al", 0>; 52def DL : X86Reg<"dl", 2>; 53def CL : X86Reg<"cl", 1>; 54def BL : X86Reg<"bl", 3>; 55 56// High registers. On x86-64, these cannot be used in any instruction 57// with a REX prefix. 58def AH : X86Reg<"ah", 4>; 59def DH : X86Reg<"dh", 6>; 60def CH : X86Reg<"ch", 5>; 61def BH : X86Reg<"bh", 7>; 62 63// X86-64 only, requires REX. 64def SIL : X86Reg<"sil", 6>; 65def DIL : X86Reg<"dil", 7>; 66def BPL : X86Reg<"bpl", 5>; 67def SPL : X86Reg<"spl", 4>; 68def R8B : X86Reg<"r8b", 8>; 69def R9B : X86Reg<"r9b", 9>; 70def R10B : X86Reg<"r10b", 10>; 71def R11B : X86Reg<"r11b", 11>; 72def R12B : X86Reg<"r12b", 12>; 73def R13B : X86Reg<"r13b", 13>; 74def R14B : X86Reg<"r14b", 14>; 75def R15B : X86Reg<"r15b", 15>; 76 77let isArtificial = 1 in { 78// High byte of the low 16 bits of the super-register: 79def SIH : X86Reg<"", -1>; 80def DIH : X86Reg<"", -1>; 81def BPH : X86Reg<"", -1>; 82def SPH : X86Reg<"", -1>; 83def R8BH : X86Reg<"", -1>; 84def R9BH : X86Reg<"", -1>; 85def R10BH : X86Reg<"", -1>; 86def R11BH : X86Reg<"", -1>; 87def R12BH : X86Reg<"", -1>; 88def R13BH : X86Reg<"", -1>; 89def R14BH : X86Reg<"", -1>; 90def R15BH : X86Reg<"", -1>; 91// High word of the low 32 bits of the super-register: 92def HAX : X86Reg<"", -1>; 93def HDX : X86Reg<"", -1>; 94def HCX : X86Reg<"", -1>; 95def HBX : X86Reg<"", -1>; 96def HSI : X86Reg<"", -1>; 97def HDI : X86Reg<"", -1>; 98def HBP : X86Reg<"", -1>; 99def HSP : X86Reg<"", -1>; 100def HIP : X86Reg<"", -1>; 101def R8WH : X86Reg<"", -1>; 102def R9WH : X86Reg<"", -1>; 103def R10WH : X86Reg<"", -1>; 104def R11WH : X86Reg<"", -1>; 105def R12WH : X86Reg<"", -1>; 106def R13WH : X86Reg<"", -1>; 107def R14WH : X86Reg<"", -1>; 108def R15WH : X86Reg<"", -1>; 109} 110 111// 16-bit registers 112let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { 113def AX : X86Reg<"ax", 0, [AL,AH]>; 114def DX : X86Reg<"dx", 2, [DL,DH]>; 115def CX : X86Reg<"cx", 1, [CL,CH]>; 116def BX : X86Reg<"bx", 3, [BL,BH]>; 117} 118let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 119def SI : X86Reg<"si", 6, [SIL,SIH]>; 120def DI : X86Reg<"di", 7, [DIL,DIH]>; 121def BP : X86Reg<"bp", 5, [BPL,BPH]>; 122def SP : X86Reg<"sp", 4, [SPL,SPH]>; 123} 124def IP : X86Reg<"ip", 0>; 125 126// X86-64 only, requires REX. 127let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 128def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; 129def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; 130def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; 131def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; 132def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; 133def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; 134def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; 135def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; 136} 137 138// 32-bit registers 139let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 140def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; 141def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; 142def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; 143def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; 144def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; 145def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; 146def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; 147def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; 148def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; 149} 150 151// X86-64 only, requires REX 152let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 153def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; 154def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; 155def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; 156def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; 157def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; 158def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; 159def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; 160def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; 161} 162 163// 64-bit registers, X86-64 only 164let SubRegIndices = [sub_32bit] in { 165def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; 166def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; 167def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; 168def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; 169def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; 170def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; 171def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; 172def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; 173 174// These also require REX. 175def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; 176def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; 177def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; 178def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; 179def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; 180def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; 181def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; 182def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; 183def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; 184} 185 186// MMX Registers. These are actually aliased to ST0 .. ST7 187def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; 188def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; 189def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; 190def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; 191def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; 192def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; 193def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; 194def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; 195 196// Pseudo Floating Point registers 197def FP0 : X86Reg<"fp0", 0>; 198def FP1 : X86Reg<"fp1", 0>; 199def FP2 : X86Reg<"fp2", 0>; 200def FP3 : X86Reg<"fp3", 0>; 201def FP4 : X86Reg<"fp4", 0>; 202def FP5 : X86Reg<"fp5", 0>; 203def FP6 : X86Reg<"fp6", 0>; 204def FP7 : X86Reg<"fp7", 0>; 205 206// XMM Registers, used by the various SSE instruction set extensions. 207def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; 208def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; 209def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; 210def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; 211def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; 212def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; 213def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; 214def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; 215 216// X86-64 only 217def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; 218def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; 219def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; 220def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; 221def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; 222def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; 223def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; 224def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; 225 226def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>; 227def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>; 228def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>; 229def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>; 230def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>; 231def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>; 232def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>; 233def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>; 234def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>; 235def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; 236def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; 237def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; 238def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; 239def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; 240def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; 241def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; 242 243// YMM0-15 registers, used by AVX instructions and 244// YMM16-31 registers, used by AVX-512 instructions. 245let SubRegIndices = [sub_xmm] in { 246 foreach Index = 0-31 in { 247 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, 248 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 249 } 250} 251 252// ZMM Registers, used by AVX-512 instructions. 253let SubRegIndices = [sub_ymm] in { 254 foreach Index = 0-31 in { 255 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>, 256 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 257 } 258} 259 260// Tile config registers. 261def TMMCFG: X86Reg<"tmmcfg", 0>; 262 263// Tile "registers". 264def TMM0: X86Reg<"tmm0", 0>; 265def TMM1: X86Reg<"tmm1", 1>; 266def TMM2: X86Reg<"tmm2", 2>; 267def TMM3: X86Reg<"tmm3", 3>; 268def TMM4: X86Reg<"tmm4", 4>; 269def TMM5: X86Reg<"tmm5", 5>; 270def TMM6: X86Reg<"tmm6", 6>; 271def TMM7: X86Reg<"tmm7", 7>; 272 273// Mask Registers, used by AVX-512 instructions. 274def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; 275def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; 276def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; 277def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; 278def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; 279def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; 280def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; 281def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; 282 283// Floating point stack registers. These don't map one-to-one to the FP 284// pseudo registers, but we still mark them as aliasing FP registers. That 285// way both kinds can be live without exceeding the stack depth. ST registers 286// are only live around inline assembly. 287def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>; 288def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; 289def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; 290def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; 291def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; 292def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; 293def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; 294def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; 295 296// Floating-point status word 297def FPSW : X86Reg<"fpsr", 0>; 298 299// Floating-point control word 300def FPCW : X86Reg<"fpcr", 0>; 301 302// SIMD Floating-point control register. 303// Note: We only model the "Uses" of the control bits: current rounding modes, 304// DAZ, FTZ and exception masks. We don't model the "Defs" of flag bits. 305def MXCSR : X86Reg<"mxcsr", 0>; 306 307// Status flags register. 308// 309// Note that some flags that are commonly thought of as part of the status 310// flags register are modeled separately. Typically this is due to instructions 311// reading and updating those flags independently of all the others. We don't 312// want to create false dependencies between these instructions and so we use 313// a separate register to model them. 314def EFLAGS : X86Reg<"flags", 0>, DwarfRegNum<[49, 9, 9]>; 315def _EFLAGS : X86Reg<"eflags", 0>, DwarfRegAlias<EFLAGS>; 316def RFLAGS : X86Reg<"rflags", 0>, DwarfRegNum<[49, -2, -2]>; 317 318// The direction flag. 319def DF : X86Reg<"dirflag", 0>; 320 321 322// Segment registers 323def CS : X86Reg<"cs", 1>, DwarfRegNum<[51, -2, 41]>; 324def DS : X86Reg<"ds", 3>, DwarfRegNum<[53, -2, 43]>; 325def SS : X86Reg<"ss", 2>, DwarfRegNum<[52, -2, 42]>; 326def ES : X86Reg<"es", 0>, DwarfRegNum<[50, -2, 40]>; 327def FS : X86Reg<"fs", 4>, DwarfRegNum<[54, -2, 44]>; 328def GS : X86Reg<"gs", 5>, DwarfRegNum<[55, -2, 45]>; 329 330def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>; 331def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>; 332 333// Debug registers 334def DR0 : X86Reg<"dr0", 0>; 335def DR1 : X86Reg<"dr1", 1>; 336def DR2 : X86Reg<"dr2", 2>; 337def DR3 : X86Reg<"dr3", 3>; 338def DR4 : X86Reg<"dr4", 4>; 339def DR5 : X86Reg<"dr5", 5>; 340def DR6 : X86Reg<"dr6", 6>; 341def DR7 : X86Reg<"dr7", 7>; 342def DR8 : X86Reg<"dr8", 8>; 343def DR9 : X86Reg<"dr9", 9>; 344def DR10 : X86Reg<"dr10", 10>; 345def DR11 : X86Reg<"dr11", 11>; 346def DR12 : X86Reg<"dr12", 12>; 347def DR13 : X86Reg<"dr13", 13>; 348def DR14 : X86Reg<"dr14", 14>; 349def DR15 : X86Reg<"dr15", 15>; 350 351// Control registers 352def CR0 : X86Reg<"cr0", 0>; 353def CR1 : X86Reg<"cr1", 1>; 354def CR2 : X86Reg<"cr2", 2>; 355def CR3 : X86Reg<"cr3", 3>; 356def CR4 : X86Reg<"cr4", 4>; 357def CR5 : X86Reg<"cr5", 5>; 358def CR6 : X86Reg<"cr6", 6>; 359def CR7 : X86Reg<"cr7", 7>; 360def CR8 : X86Reg<"cr8", 8>; 361def CR9 : X86Reg<"cr9", 9>; 362def CR10 : X86Reg<"cr10", 10>; 363def CR11 : X86Reg<"cr11", 11>; 364def CR12 : X86Reg<"cr12", 12>; 365def CR13 : X86Reg<"cr13", 13>; 366def CR14 : X86Reg<"cr14", 14>; 367def CR15 : X86Reg<"cr15", 15>; 368 369// Pseudo index registers 370def EIZ : X86Reg<"eiz", 4>; 371def RIZ : X86Reg<"riz", 4>; 372 373// CET registers - Shadow Stack Pointer 374def SSP : X86Reg<"ssp", 0>; 375 376//===----------------------------------------------------------------------===// 377// Register Class Definitions... now that we have all of the pieces, define the 378// top-level register classes. The order specified in the register list is 379// implicitly defined to be the register allocation order. 380// 381 382// List call-clobbered registers before callee-save registers. RBX, RBP, (and 383// R12, R13, R14, and R15 for X86-64) are callee-save registers. 384// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 385// R8B, ... R15B. 386// Allocate R12 and R13 last, as these require an extra byte when 387// encoded in x86_64 instructions. 388// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 389// 64-bit mode. The main complication is that they cannot be encoded in an 390// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 391// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 392// cannot be encoded. 393def GR8 : RegisterClass<"X86", [i8], 8, 394 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 395 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { 396 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 397 let AltOrderSelect = [{ 398 return MF.getSubtarget<X86Subtarget>().is64Bit(); 399 }]; 400} 401 402let isAllocatable = 0 in 403def GRH8 : RegisterClass<"X86", [i8], 8, 404 (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH, 405 R12BH, R13BH, R14BH, R15BH)>; 406 407def GR16 : RegisterClass<"X86", [i16], 16, 408 (add AX, CX, DX, SI, DI, BX, BP, SP, 409 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; 410 411let isAllocatable = 0 in 412def GRH16 : RegisterClass<"X86", [i16], 16, 413 (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, 414 R8WH, R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, 415 R15WH)>; 416 417def GR32 : RegisterClass<"X86", [i32], 32, 418 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 419 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; 420 421// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 422// RIP isn't really a register and it can't be used anywhere except in an 423// address, but it doesn't cause trouble. 424// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra 425// tests because of the inclusion of RIP in this register class. 426def GR64 : RegisterClass<"X86", [i64], 64, 427 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 428 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 429 430// GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when 431// emitting code for intrinsics, which use implict input registers. 432def GR64PLTSafe : RegisterClass<"X86", [i64], 64, 433 (add RAX, RCX, RDX, RSI, RDI, R8, R9, 434 RBX, R14, R15, R12, R13, RBP)>; 435 436// It includes the GPR that are used as scratch register for Linux64 calling 437// convention. 438def GR64_ArgRef: RegisterClass<"X86", [i64], 64, (add R10, R11)> { 439 let GeneratePressureSet = 0; 440} 441 442// It includes the GPR that are used as scratch register for Linux32 calling 443// convention. 444def GR32_ArgRef: RegisterClass<"X86", [i32], 32, (add ECX, EDX)> { 445 let GeneratePressureSet = 0; 446} 447 448// Segment registers for use by MOV instructions (and others) that have a 449// segment register as one operand. Always contain a 16-bit segment 450// descriptor. 451def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 452 453// Debug registers. 454def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; 455 456// Control registers. 457def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 458 459// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 460// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 461// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 462// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 463// and GR64_ABCD are classes for registers that support 8-bit h-register 464// operations. 465def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 466def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 467def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; 468def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 469def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 470def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>; 471def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 472 R8, R9, R11, RIP, RSP)>; 473def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 474 R8, R9, R10, R11, 475 RIP, RSP)>; 476 477// GR8_NOREX - GR8 registers which do not require a REX prefix. 478def GR8_NOREX : RegisterClass<"X86", [i8], 8, 479 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 480 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 481 let AltOrderSelect = [{ 482 return MF.getSubtarget<X86Subtarget>().is64Bit(); 483 }]; 484} 485// GR16_NOREX - GR16 registers which do not require a REX prefix. 486def GR16_NOREX : RegisterClass<"X86", [i16], 16, 487 (add AX, CX, DX, SI, DI, BX, BP, SP)>; 488// GR32_NOREX - GR32 registers which do not require a REX prefix. 489def GR32_NOREX : RegisterClass<"X86", [i32], 32, 490 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 491// GR64_NOREX - GR64 registers which do not require a REX prefix. 492def GR64_NOREX : RegisterClass<"X86", [i64], 64, 493 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 494 495// GR32_NOSP - GR32 registers except ESP. 496def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 497 498// GR64_NOSP - GR64 registers except RSP (and RIP). 499def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 500 501// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 502// ESP. 503def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 504 (and GR32_NOREX, GR32_NOSP)>; 505 506// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 507def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 508 (and GR64_NOREX, GR64_NOSP)>; 509 510// Register classes used for ABIs that use 32-bit address accesses, 511// while using the whole x84_64 ISA. 512 513// In such cases, it is fine to use RIP as we are sure the 32 high 514// bits are not set. We do not need variants for NOSP as RIP is not 515// allowed there. 516// RIP is not spilled anywhere for now, so stick to 32-bit alignment 517// to save on memory space. 518// FIXME: We could allow all 64bit registers, but we would need 519// something to check that the 32 high bits are not set, 520// which we do not have right now. 521def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; 522 523// When RBP is used as a base pointer in a 32-bit addresses environment, 524// this is also safe to use the full register to access addresses. 525// Since RBP will never be spilled, stick to a 32 alignment to save 526// on memory consumption. 527def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, 528 (add LOW32_ADDR_ACCESS, RBP)>; 529 530// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. 531def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; 532def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>; 533 534// Classes to support the 64-bit assembler constraint tied to a fixed 535// register in 32-bit mode. The second register is always the next in 536// the list. Wrap around causes an error. 537def GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>; 538def GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>; 539def GR32_BSI : RegisterClass<"X86", [i32], 32, (add EBX, ESI)>; 540def GR32_SIDI : RegisterClass<"X86", [i32], 32, (add ESI, EDI)>; 541def GR32_DIBP : RegisterClass<"X86", [i32], 32, (add EDI, EBP)>; 542def GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>; 543 544// Scalar SSE2 floating point registers. 545def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 546 547def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 548 549def FR16 : RegisterClass<"X86", [f16], 16, (add FR32)> {let Size = 32;} 550 551 552// FIXME: This sets up the floating point register files as though they are f64 553// values, though they really are f80 values. This will cause us to spill 554// values as 64-bit quantities instead of 80-bit quantities, which is much much 555// faster on common hardware. In reality, this should be controlled by a 556// command line option or something. 557 558 559def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 560def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 561def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 562 563// st(7) may be is not allocatable. 564def RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> { 565 let isAllocatable = 0; 566} 567 568// Floating point stack registers (these are not allocatable by the 569// register allocator - the floating point stackifier is responsible 570// for transforming FPn allocations to STn registers) 571def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 572 let isAllocatable = 0; 573} 574 575// Helper to allow %st to print as %st(0) when its encoded in the instruction. 576def RSTi : RegisterOperand<RST, "printSTiRegOperand">; 577 578// Generic vector registers: VR64 and VR128. 579// Ensure that float types are declared first - only float is legal on SSE1. 580def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 581def VR128 : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128], 582 128, (add FR32)>; 583def VR256 : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64], 584 256, (sequence "YMM%u", 0, 15)>; 585 586// Status flags registers. 587def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 588 let CopyCost = -1; // Don't allow copying of status registers. 589 let isAllocatable = 0; 590} 591def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { 592 let CopyCost = -1; // Don't allow copying of status registers. 593 let isAllocatable = 0; 594} 595def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> { 596 let CopyCost = -1; // Don't allow copying of status registers. 597 let isAllocatable = 0; 598} 599 600// AVX-512 vector/mask registers. 601def VR512 : RegisterClass<"X86", [v16f32, v8f64, v32f16, v32bf16, v64i8, v32i16, v16i32, v8i64], 602 512, (sequence "ZMM%u", 0, 31)>; 603 604// Represents the lower 16 registers that have VEX/legacy encodable subregs. 605def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 606 512, (sequence "ZMM%u", 0, 15)>; 607 608// Scalar AVX-512 floating point registers. 609def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; 610 611def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; 612 613def FR16X : RegisterClass<"X86", [f16], 16, (add FR32X)> {let Size = 32;} 614 615// Extended VR128 and VR256 for AVX-512 instructions 616def VR128X : RegisterClass<"X86", [v4f32, v2f64, v8f16, v8bf16, v16i8, v8i16, v4i32, v2i64, f128], 617 128, (add FR32X)>; 618def VR256X : RegisterClass<"X86", [v8f32, v4f64, v16f16, v16bf16, v32i8, v16i16, v8i32, v4i64], 619 256, (sequence "YMM%u", 0, 31)>; 620 621// Mask registers 622def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} 623def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} 624def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} 625def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} 626def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} 627def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} 628def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} 629 630// Mask register pairs 631def KPAIRS : RegisterTuples<[sub_mask_0, sub_mask_1], 632 [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>; 633 634def VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 635def VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 636def VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 637def VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 638def VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 639 640def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;} 641def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} 642def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} 643def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} 644def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} 645def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} 646def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} 647 648// Tiles 649let CopyCost = -1 in // Don't allow copying of tile registers 650def TILE : RegisterClass<"X86", [x86amx], 8192, 651 (sequence "TMM%u", 0, 7)> {let Size = 8192;} 652 653//===----------------------------------------------------------------------===// 654// Register categories. 655// 656 657// The TILE and VK*PAIR registers may not be "fixed", but we don't want them 658// anyway. 659def FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR, 660 DFCCR, TILE, VK1PAIR, VK2PAIR, VK4PAIR, 661 VK8PAIR, VK16PAIR]>; 662def GeneralPurposeRegisters : RegisterCategory<[GR64, GR32, GR16, GR8]>; 663