1//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 Register file, defining the registers themselves, 10// aliases between the registers, and the register classes built out of the 11// registers. 12// 13//===----------------------------------------------------------------------===// 14 15class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { 16 let Namespace = "X86"; 17 let HWEncoding = Enc; 18 let SubRegs = subregs; 19} 20 21// Subregister indices. 22let Namespace = "X86" in { 23 def sub_8bit : SubRegIndex<8>; 24 def sub_8bit_hi : SubRegIndex<8, 8>; 25 def sub_8bit_hi_phony : SubRegIndex<8, 8>; 26 def sub_16bit : SubRegIndex<16>; 27 def sub_16bit_hi : SubRegIndex<16, 16>; 28 def sub_32bit : SubRegIndex<32>; 29 def sub_xmm : SubRegIndex<128>; 30 def sub_ymm : SubRegIndex<256>; 31 def sub_mask_0 : SubRegIndex<-1>; 32 def sub_mask_1 : SubRegIndex<-1, -1>; 33} 34 35//===----------------------------------------------------------------------===// 36// Register definitions... 37// 38 39// In the register alias definitions below, we define which registers alias 40// which others. We only specify which registers the small registers alias, 41// because the register file generator is smart enough to figure out that 42// AL aliases AX if we tell it that AX aliased AL (for example). 43 44// Dwarf numbering is different for 32-bit and 64-bit, and there are 45// variations by target as well. Currently the first entry is for X86-64, 46// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 47// and debug information on X86-32/Darwin) 48 49// 8-bit registers 50// Low registers 51def AL : X86Reg<"al", 0>; 52def DL : X86Reg<"dl", 2>; 53def CL : X86Reg<"cl", 1>; 54def BL : X86Reg<"bl", 3>; 55 56// High registers. On x86-64, these cannot be used in any instruction 57// with a REX prefix. 58def AH : X86Reg<"ah", 4>; 59def DH : X86Reg<"dh", 6>; 60def CH : X86Reg<"ch", 5>; 61def BH : X86Reg<"bh", 7>; 62 63// X86-64 only, requires REX. 64let CostPerUse = 1 in { 65def SIL : X86Reg<"sil", 6>; 66def DIL : X86Reg<"dil", 7>; 67def BPL : X86Reg<"bpl", 5>; 68def SPL : X86Reg<"spl", 4>; 69def R8B : X86Reg<"r8b", 8>; 70def R9B : X86Reg<"r9b", 9>; 71def R10B : X86Reg<"r10b", 10>; 72def R11B : X86Reg<"r11b", 11>; 73def R12B : X86Reg<"r12b", 12>; 74def R13B : X86Reg<"r13b", 13>; 75def R14B : X86Reg<"r14b", 14>; 76def R15B : X86Reg<"r15b", 15>; 77} 78 79let isArtificial = 1 in { 80// High byte of the low 16 bits of the super-register: 81def SIH : X86Reg<"", -1>; 82def DIH : X86Reg<"", -1>; 83def BPH : X86Reg<"", -1>; 84def SPH : X86Reg<"", -1>; 85def R8BH : X86Reg<"", -1>; 86def R9BH : X86Reg<"", -1>; 87def R10BH : X86Reg<"", -1>; 88def R11BH : X86Reg<"", -1>; 89def R12BH : X86Reg<"", -1>; 90def R13BH : X86Reg<"", -1>; 91def R14BH : X86Reg<"", -1>; 92def R15BH : X86Reg<"", -1>; 93// High word of the low 32 bits of the super-register: 94def HAX : X86Reg<"", -1>; 95def HDX : X86Reg<"", -1>; 96def HCX : X86Reg<"", -1>; 97def HBX : X86Reg<"", -1>; 98def HSI : X86Reg<"", -1>; 99def HDI : X86Reg<"", -1>; 100def HBP : X86Reg<"", -1>; 101def HSP : X86Reg<"", -1>; 102def HIP : X86Reg<"", -1>; 103def R8WH : X86Reg<"", -1>; 104def R9WH : X86Reg<"", -1>; 105def R10WH : X86Reg<"", -1>; 106def R11WH : X86Reg<"", -1>; 107def R12WH : X86Reg<"", -1>; 108def R13WH : X86Reg<"", -1>; 109def R14WH : X86Reg<"", -1>; 110def R15WH : X86Reg<"", -1>; 111} 112 113// 16-bit registers 114let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { 115def AX : X86Reg<"ax", 0, [AL,AH]>; 116def DX : X86Reg<"dx", 2, [DL,DH]>; 117def CX : X86Reg<"cx", 1, [CL,CH]>; 118def BX : X86Reg<"bx", 3, [BL,BH]>; 119} 120let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 121def SI : X86Reg<"si", 6, [SIL,SIH]>; 122def DI : X86Reg<"di", 7, [DIL,DIH]>; 123def BP : X86Reg<"bp", 5, [BPL,BPH]>; 124def SP : X86Reg<"sp", 4, [SPL,SPH]>; 125} 126def IP : X86Reg<"ip", 0>; 127 128// X86-64 only, requires REX. 129let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = 1, 130 CoveredBySubRegs = 1 in { 131def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; 132def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; 133def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; 134def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; 135def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; 136def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; 137def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; 138def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; 139} 140 141// 32-bit registers 142let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 143def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; 144def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; 145def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; 146def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; 147def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; 148def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; 149def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; 150def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; 151def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; 152} 153 154// X86-64 only, requires REX 155let SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = 1, 156 CoveredBySubRegs = 1 in { 157def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; 158def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; 159def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; 160def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; 161def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; 162def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; 163def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; 164def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; 165} 166 167// 64-bit registers, X86-64 only 168let SubRegIndices = [sub_32bit] in { 169def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; 170def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; 171def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; 172def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; 173def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; 174def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; 175def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; 176def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; 177 178// These also require REX. 179let CostPerUse = 1 in { 180def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; 181def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; 182def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; 183def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; 184def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; 185def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; 186def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; 187def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; 188def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; 189}} 190 191// MMX Registers. These are actually aliased to ST0 .. ST7 192def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; 193def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; 194def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; 195def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; 196def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; 197def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; 198def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; 199def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; 200 201// Pseudo Floating Point registers 202def FP0 : X86Reg<"fp0", 0>; 203def FP1 : X86Reg<"fp1", 0>; 204def FP2 : X86Reg<"fp2", 0>; 205def FP3 : X86Reg<"fp3", 0>; 206def FP4 : X86Reg<"fp4", 0>; 207def FP5 : X86Reg<"fp5", 0>; 208def FP6 : X86Reg<"fp6", 0>; 209def FP7 : X86Reg<"fp7", 0>; 210 211// XMM Registers, used by the various SSE instruction set extensions. 212def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; 213def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; 214def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; 215def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; 216def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; 217def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; 218def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; 219def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; 220 221// X86-64 only 222let CostPerUse = 1 in { 223def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; 224def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; 225def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; 226def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; 227def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; 228def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; 229def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; 230def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; 231 232def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>; 233def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>; 234def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>; 235def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>; 236def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>; 237def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>; 238def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>; 239def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>; 240def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>; 241def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; 242def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; 243def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; 244def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; 245def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; 246def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; 247def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; 248 249} // CostPerUse 250 251// YMM0-15 registers, used by AVX instructions and 252// YMM16-31 registers, used by AVX-512 instructions. 253let SubRegIndices = [sub_xmm] in { 254 foreach Index = 0-31 in { 255 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, 256 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 257 } 258} 259 260// ZMM Registers, used by AVX-512 instructions. 261let SubRegIndices = [sub_ymm] in { 262 foreach Index = 0-31 in { 263 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>, 264 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 265 } 266} 267 268// Mask Registers, used by AVX-512 instructions. 269def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; 270def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; 271def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; 272def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; 273def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; 274def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; 275def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; 276def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; 277 278// Floating point stack registers. These don't map one-to-one to the FP 279// pseudo registers, but we still mark them as aliasing FP registers. That 280// way both kinds can be live without exceeding the stack depth. ST registers 281// are only live around inline assembly. 282def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>; 283def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; 284def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; 285def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; 286def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; 287def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; 288def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; 289def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; 290 291// Floating-point status word 292def FPSW : X86Reg<"fpsr", 0>; 293 294// Floating-point control word 295def FPCW : X86Reg<"fpcr", 0>; 296 297// SIMD Floating-point control register. 298// Note: We only model the "Uses" of the control bits: current rounding modes, 299// DAZ, FTZ and exception masks. We don't model the "Defs" of flag bits. 300def MXCSR : X86Reg<"mxcsr", 0>; 301 302// Status flags register. 303// 304// Note that some flags that are commonly thought of as part of the status 305// flags register are modeled separately. Typically this is due to instructions 306// reading and updating those flags independently of all the others. We don't 307// want to create false dependencies between these instructions and so we use 308// a separate register to model them. 309def EFLAGS : X86Reg<"flags", 0>; 310 311// The direction flag. 312def DF : X86Reg<"dirflag", 0>; 313 314 315// Segment registers 316def CS : X86Reg<"cs", 1>; 317def DS : X86Reg<"ds", 3>; 318def SS : X86Reg<"ss", 2>; 319def ES : X86Reg<"es", 0>; 320def FS : X86Reg<"fs", 4>; 321def GS : X86Reg<"gs", 5>; 322 323// Debug registers 324def DR0 : X86Reg<"dr0", 0>; 325def DR1 : X86Reg<"dr1", 1>; 326def DR2 : X86Reg<"dr2", 2>; 327def DR3 : X86Reg<"dr3", 3>; 328def DR4 : X86Reg<"dr4", 4>; 329def DR5 : X86Reg<"dr5", 5>; 330def DR6 : X86Reg<"dr6", 6>; 331def DR7 : X86Reg<"dr7", 7>; 332def DR8 : X86Reg<"dr8", 8>; 333def DR9 : X86Reg<"dr9", 9>; 334def DR10 : X86Reg<"dr10", 10>; 335def DR11 : X86Reg<"dr11", 11>; 336def DR12 : X86Reg<"dr12", 12>; 337def DR13 : X86Reg<"dr13", 13>; 338def DR14 : X86Reg<"dr14", 14>; 339def DR15 : X86Reg<"dr15", 15>; 340 341// Control registers 342def CR0 : X86Reg<"cr0", 0>; 343def CR1 : X86Reg<"cr1", 1>; 344def CR2 : X86Reg<"cr2", 2>; 345def CR3 : X86Reg<"cr3", 3>; 346def CR4 : X86Reg<"cr4", 4>; 347def CR5 : X86Reg<"cr5", 5>; 348def CR6 : X86Reg<"cr6", 6>; 349def CR7 : X86Reg<"cr7", 7>; 350def CR8 : X86Reg<"cr8", 8>; 351def CR9 : X86Reg<"cr9", 9>; 352def CR10 : X86Reg<"cr10", 10>; 353def CR11 : X86Reg<"cr11", 11>; 354def CR12 : X86Reg<"cr12", 12>; 355def CR13 : X86Reg<"cr13", 13>; 356def CR14 : X86Reg<"cr14", 14>; 357def CR15 : X86Reg<"cr15", 15>; 358 359// Pseudo index registers 360def EIZ : X86Reg<"eiz", 4>; 361def RIZ : X86Reg<"riz", 4>; 362 363// Bound registers, used in MPX instructions 364def BND0 : X86Reg<"bnd0", 0>; 365def BND1 : X86Reg<"bnd1", 1>; 366def BND2 : X86Reg<"bnd2", 2>; 367def BND3 : X86Reg<"bnd3", 3>; 368 369// CET registers - Shadow Stack Pointer 370def SSP : X86Reg<"ssp", 0>; 371 372//===----------------------------------------------------------------------===// 373// Register Class Definitions... now that we have all of the pieces, define the 374// top-level register classes. The order specified in the register list is 375// implicitly defined to be the register allocation order. 376// 377 378// List call-clobbered registers before callee-save registers. RBX, RBP, (and 379// R12, R13, R14, and R15 for X86-64) are callee-save registers. 380// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 381// R8B, ... R15B. 382// Allocate R12 and R13 last, as these require an extra byte when 383// encoded in x86_64 instructions. 384// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 385// 64-bit mode. The main complication is that they cannot be encoded in an 386// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 387// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 388// cannot be encoded. 389def GR8 : RegisterClass<"X86", [i8], 8, 390 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 391 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { 392 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 393 let AltOrderSelect = [{ 394 return MF.getSubtarget<X86Subtarget>().is64Bit(); 395 }]; 396} 397 398let isAllocatable = 0 in 399def GRH8 : RegisterClass<"X86", [i8], 8, 400 (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH, 401 R12BH, R13BH, R14BH, R15BH)>; 402 403def GR16 : RegisterClass<"X86", [i16], 16, 404 (add AX, CX, DX, SI, DI, BX, BP, SP, 405 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; 406 407let isAllocatable = 0 in 408def GRH16 : RegisterClass<"X86", [i16], 16, 409 (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, 410 R8WH, R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, 411 R15WH)>; 412 413def GR32 : RegisterClass<"X86", [i32], 32, 414 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 415 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; 416 417// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 418// RIP isn't really a register and it can't be used anywhere except in an 419// address, but it doesn't cause trouble. 420// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra 421// tests because of the inclusion of RIP in this register class. 422def GR64 : RegisterClass<"X86", [i64], 64, 423 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 424 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 425 426// Segment registers for use by MOV instructions (and others) that have a 427// segment register as one operand. Always contain a 16-bit segment 428// descriptor. 429def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 430 431// Debug registers. 432def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; 433 434// Control registers. 435def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 436 437// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 438// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 439// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 440// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 441// and GR64_ABCD are classes for registers that support 8-bit h-register 442// operations. 443def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 444def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 445def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; 446def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 447def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 448def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>; 449def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 450 R8, R9, R11, RIP, RSP)>; 451def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 452 R8, R9, R10, R11, 453 RIP, RSP)>; 454 455// GR8_NOREX - GR8 registers which do not require a REX prefix. 456def GR8_NOREX : RegisterClass<"X86", [i8], 8, 457 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 458 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 459 let AltOrderSelect = [{ 460 return MF.getSubtarget<X86Subtarget>().is64Bit(); 461 }]; 462} 463// GR16_NOREX - GR16 registers which do not require a REX prefix. 464def GR16_NOREX : RegisterClass<"X86", [i16], 16, 465 (add AX, CX, DX, SI, DI, BX, BP, SP)>; 466// GR32_NOREX - GR32 registers which do not require a REX prefix. 467def GR32_NOREX : RegisterClass<"X86", [i32], 32, 468 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 469// GR64_NOREX - GR64 registers which do not require a REX prefix. 470def GR64_NOREX : RegisterClass<"X86", [i64], 64, 471 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 472 473// GR32_NOSP - GR32 registers except ESP. 474def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 475 476// GR64_NOSP - GR64 registers except RSP (and RIP). 477def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 478 479// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 480// ESP. 481def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 482 (and GR32_NOREX, GR32_NOSP)>; 483 484// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 485def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 486 (and GR64_NOREX, GR64_NOSP)>; 487 488// Register classes used for ABIs that use 32-bit address accesses, 489// while using the whole x84_64 ISA. 490 491// In such cases, it is fine to use RIP as we are sure the 32 high 492// bits are not set. We do not need variants for NOSP as RIP is not 493// allowed there. 494// RIP is not spilled anywhere for now, so stick to 32-bit alignment 495// to save on memory space. 496// FIXME: We could allow all 64bit registers, but we would need 497// something to check that the 32 high bits are not set, 498// which we do not have right now. 499def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; 500 501// When RBP is used as a base pointer in a 32-bit addresses environement, 502// this is also safe to use the full register to access addresses. 503// Since RBP will never be spilled, stick to a 32 alignment to save 504// on memory consumption. 505def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, 506 (add LOW32_ADDR_ACCESS, RBP)>; 507 508// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. 509def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; 510def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>; 511 512// Classes to support the 64-bit assembler constraint tied to a fixed 513// register in 32-bit mode. The second register is always the next in 514// the list. Wrap around causes an error. 515def GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>; 516def GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>; 517def GR32_BSI : RegisterClass<"X86", [i32], 32, (add EBX, ESI)>; 518def GR32_SIDI : RegisterClass<"X86", [i32], 32, (add ESI, EDI)>; 519def GR32_DIBP : RegisterClass<"X86", [i32], 32, (add EDI, EBP)>; 520def GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>; 521 522// Scalar SSE2 floating point registers. 523def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 524 525def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 526 527 528// FIXME: This sets up the floating point register files as though they are f64 529// values, though they really are f80 values. This will cause us to spill 530// values as 64-bit quantities instead of 80-bit quantities, which is much much 531// faster on common hardware. In reality, this should be controlled by a 532// command line option or something. 533 534 535def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 536def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 537def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 538 539// st(7) may be is not allocatable. 540def RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> { 541 let isAllocatable = 0; 542} 543 544// Floating point stack registers (these are not allocatable by the 545// register allocator - the floating point stackifier is responsible 546// for transforming FPn allocations to STn registers) 547def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 548 let isAllocatable = 0; 549} 550 551// Helper to allow %st to print as %st(0) when its encoded in the instruction. 552def RSTi : RegisterOperand<RST, "printSTiRegOperand">; 553 554// Generic vector registers: VR64 and VR128. 555// Ensure that float types are declared first - only float is legal on SSE1. 556def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 557def VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 558 128, (add FR32)>; 559def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 560 256, (sequence "YMM%u", 0, 15)>; 561 562// Status flags registers. 563def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 564 let CopyCost = -1; // Don't allow copying of status registers. 565 let isAllocatable = 0; 566} 567def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { 568 let CopyCost = -1; // Don't allow copying of status registers. 569 let isAllocatable = 0; 570} 571def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> { 572 let CopyCost = -1; // Don't allow copying of status registers. 573 let isAllocatable = 0; 574} 575 576// AVX-512 vector/mask registers. 577def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 578 512, (sequence "ZMM%u", 0, 31)>; 579 580// Represents the lower 16 registers that have VEX/legacy encodable subregs. 581def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 582 512, (sequence "ZMM%u", 0, 15)>; 583 584// Scalar AVX-512 floating point registers. 585def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; 586 587def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; 588 589// Extended VR128 and VR256 for AVX-512 instructions 590def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 591 128, (add FR32X)>; 592def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 593 256, (sequence "YMM%u", 0, 31)>; 594 595// Mask registers 596def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} 597def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} 598def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} 599def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} 600def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} 601def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} 602def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} 603 604// Mask register pairs 605def KPAIRS : RegisterTuples<[sub_mask_0, sub_mask_1], 606 [(add K0, K2, K4, K6), (add K1, K3, K5, K7)]>; 607 608def VK1PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 609def VK2PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 610def VK4PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 611def VK8PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 612def VK16PAIR : RegisterClass<"X86", [untyped], 16, (add KPAIRS)> {let Size = 32;} 613 614def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;} 615def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} 616def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} 617def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} 618def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} 619def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} 620def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} 621 622// Bound registers 623def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; 624