10b57cec5SDimitry Andric//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines the machine model for Haswell to support instruction 100b57cec5SDimitry Andric// scheduling and other instruction cost heuristics. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric// Note that we define some instructions here that are not supported by haswell, 130b57cec5SDimitry Andric// but we still have to define them because KNL uses the HSW model. 140b57cec5SDimitry Andric// They are currently tagged with a comment `Unsupported = 1`. 150b57cec5SDimitry Andric// FIXME: Use Unsupported = 1 once KNL has its own model. 160b57cec5SDimitry Andric// 170b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 180b57cec5SDimitry Andric 190b57cec5SDimitry Andricdef HaswellModel : SchedMachineModel { 200b57cec5SDimitry Andric // All x86 instructions are modeled as a single micro-op, and HW can decode 4 210b57cec5SDimitry Andric // instructions per cycle. 220b57cec5SDimitry Andric let IssueWidth = 4; 230b57cec5SDimitry Andric let MicroOpBufferSize = 192; // Based on the reorder buffer. 240b57cec5SDimitry Andric let LoadLatency = 5; 250b57cec5SDimitry Andric let MispredictPenalty = 16; 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric // Based on the LSD (loop-stream detector) queue size and benchmarking data. 280b57cec5SDimitry Andric let LoopMicroOpBufferSize = 50; 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric // This flag is set to allow the scheduler to assign a default model to 310b57cec5SDimitry Andric // unrecognized opcodes. 320b57cec5SDimitry Andric let CompleteModel = 0; 330b57cec5SDimitry Andric} 340b57cec5SDimitry Andric 350b57cec5SDimitry Andriclet SchedModel = HaswellModel in { 360b57cec5SDimitry Andric 370b57cec5SDimitry Andric// Haswell can issue micro-ops to 8 different ports in one cycle. 380b57cec5SDimitry Andric 390b57cec5SDimitry Andric// Ports 0, 1, 5, and 6 handle all computation. 400b57cec5SDimitry Andric// Port 4 gets the data half of stores. Store data can be available later than 410b57cec5SDimitry Andric// the store address, but since we don't model the latency of stores, we can 420b57cec5SDimitry Andric// ignore that. 430b57cec5SDimitry Andric// Ports 2 and 3 are identical. They handle loads and the address half of 440b57cec5SDimitry Andric// stores. Port 7 can handle address calculations. 450b57cec5SDimitry Andricdef HWPort0 : ProcResource<1>; 460b57cec5SDimitry Andricdef HWPort1 : ProcResource<1>; 470b57cec5SDimitry Andricdef HWPort2 : ProcResource<1>; 480b57cec5SDimitry Andricdef HWPort3 : ProcResource<1>; 490b57cec5SDimitry Andricdef HWPort4 : ProcResource<1>; 500b57cec5SDimitry Andricdef HWPort5 : ProcResource<1>; 510b57cec5SDimitry Andricdef HWPort6 : ProcResource<1>; 520b57cec5SDimitry Andricdef HWPort7 : ProcResource<1>; 530b57cec5SDimitry Andric 540b57cec5SDimitry Andric// Many micro-ops are capable of issuing on multiple ports. 550b57cec5SDimitry Andricdef HWPort01 : ProcResGroup<[HWPort0, HWPort1]>; 560b57cec5SDimitry Andricdef HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; 570b57cec5SDimitry Andricdef HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; 580b57cec5SDimitry Andricdef HWPort04 : ProcResGroup<[HWPort0, HWPort4]>; 590b57cec5SDimitry Andricdef HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; 600b57cec5SDimitry Andricdef HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; 610b57cec5SDimitry Andricdef HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; 620b57cec5SDimitry Andricdef HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; 630b57cec5SDimitry Andricdef HWPort56 : ProcResGroup<[HWPort5, HWPort6]>; 640b57cec5SDimitry Andricdef HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; 650b57cec5SDimitry Andricdef HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; 660b57cec5SDimitry Andricdef HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; 670b57cec5SDimitry Andric 680b57cec5SDimitry Andric// 60 Entry Unified Scheduler 690b57cec5SDimitry Andricdef HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, 700b57cec5SDimitry Andric HWPort5, HWPort6, HWPort7]> { 710b57cec5SDimitry Andric let BufferSize=60; 720b57cec5SDimitry Andric} 730b57cec5SDimitry Andric 740b57cec5SDimitry Andric// Integer division issued on port 0. 750b57cec5SDimitry Andricdef HWDivider : ProcResource<1>; 760b57cec5SDimitry Andric// FP division and sqrt on port 0. 770b57cec5SDimitry Andricdef HWFPDivider : ProcResource<1>; 780b57cec5SDimitry Andric 790b57cec5SDimitry Andric// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 800b57cec5SDimitry Andric// cycles after the memory operand. 810b57cec5SDimitry Andricdef : ReadAdvance<ReadAfterLd, 5>; 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 840b57cec5SDimitry Andric// until 5/6/7 cycles after the memory operand. 850b57cec5SDimitry Andricdef : ReadAdvance<ReadAfterVecLd, 5>; 860b57cec5SDimitry Andricdef : ReadAdvance<ReadAfterVecXLd, 6>; 870b57cec5SDimitry Andricdef : ReadAdvance<ReadAfterVecYLd, 7>; 880b57cec5SDimitry Andric 890b57cec5SDimitry Andricdef : ReadAdvance<ReadInt2Fpu, 0>; 900b57cec5SDimitry Andric 910b57cec5SDimitry Andric// Many SchedWrites are defined in pairs with and without a folded load. 920b57cec5SDimitry Andric// Instructions with folded loads are usually micro-fused, so they only appear 930b57cec5SDimitry Andric// as two micro-ops when queued in the reservation station. 940b57cec5SDimitry Andric// This multiclass defines the resource usage for variants with and without 950b57cec5SDimitry Andric// folded loads. 960b57cec5SDimitry Andricmulticlass HWWriteResPair<X86FoldableSchedWrite SchedRW, 970b57cec5SDimitry Andric list<ProcResourceKind> ExePorts, 980b57cec5SDimitry Andric int Lat, list<int> Res = [1], int UOps = 1, 99bdd1243dSDimitry Andric int LoadLat = 5, int LoadUOps = 1> { 1000b57cec5SDimitry Andric // Register variant is using a single cycle on ExePort. 1010b57cec5SDimitry Andric def : WriteRes<SchedRW, ExePorts> { 1020b57cec5SDimitry Andric let Latency = Lat; 1035f757f3fSDimitry Andric let ReleaseAtCycles = Res; 1040b57cec5SDimitry Andric let NumMicroOps = UOps; 1050b57cec5SDimitry Andric } 1060b57cec5SDimitry Andric 1070b57cec5SDimitry Andric // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 1080b57cec5SDimitry Andric // the latency (default = 5). 1090b57cec5SDimitry Andric def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> { 1100b57cec5SDimitry Andric let Latency = !add(Lat, LoadLat); 1115f757f3fSDimitry Andric let ReleaseAtCycles = !listconcat([1], Res); 112bdd1243dSDimitry Andric let NumMicroOps = !add(UOps, LoadUOps); 1130b57cec5SDimitry Andric } 1140b57cec5SDimitry Andric} 1150b57cec5SDimitry Andric 1160b57cec5SDimitry Andric// A folded store needs a cycle on port 4 for the store data, and an extra port 1170b57cec5SDimitry Andric// 2/3/7 cycle to recompute the address. 1180b57cec5SDimitry Andricdef : WriteRes<WriteRMW, [HWPort237,HWPort4]>; 1190b57cec5SDimitry Andric 120349cc55cSDimitry Andric// Loads, stores, and moves, not folded with other operations. 1210b57cec5SDimitry Andric// Store_addr on 237. 1220b57cec5SDimitry Andric// Store_data on 4. 1230b57cec5SDimitry Andricdefm : X86WriteRes<WriteStore, [HWPort237, HWPort4], 1, [1,1], 1>; 1240b57cec5SDimitry Andricdefm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>; 1250b57cec5SDimitry Andricdefm : X86WriteRes<WriteLoad, [HWPort23], 5, [1], 1>; 1260b57cec5SDimitry Andricdefm : X86WriteRes<WriteMove, [HWPort0156], 1, [1], 1>; 127349cc55cSDimitry Andric 128349cc55cSDimitry Andric// Idioms that clear a register, like xorps %xmm0, %xmm0. 129349cc55cSDimitry Andric// These can often bypass execution ports completely. 1300b57cec5SDimitry Andricdef : WriteRes<WriteZero, []>; 1310b57cec5SDimitry Andric 132fe6060f1SDimitry Andric// Model the effect of clobbering the read-write mask operand of the GATHER operation. 133fe6060f1SDimitry Andric// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 134fe6060f1SDimitry Andricdefm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 135fe6060f1SDimitry Andric 1360b57cec5SDimitry Andric// Arithmetic. 1370b57cec5SDimitry Andricdefm : HWWriteResPair<WriteALU, [HWPort0156], 1>; 1380b57cec5SDimitry Andricdefm : HWWriteResPair<WriteADC, [HWPort06, HWPort0156], 2, [1,1], 2>; 1390b57cec5SDimitry Andric 1400b57cec5SDimitry Andric// Integer multiplication. 1410b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul8, [HWPort1], 3>; 1420b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul16, [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>; 1430b57cec5SDimitry Andricdefm : X86WriteRes<WriteIMul16Imm, [HWPort1,HWPort0156], 4, [1,1], 2>; 1440b57cec5SDimitry Andricdefm : X86WriteRes<WriteIMul16ImmLd, [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>; 1450b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul16Reg, [HWPort1], 3>; 1460b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>; 147349cc55cSDimitry Andricdefm : HWWriteResPair<WriteMULX32, [HWPort1,HWPort06,HWPort0156], 3, [1,1,1], 3>; 1480b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul32Imm, [HWPort1], 3>; 1490b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul32Reg, [HWPort1], 3>; 1500b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul64, [HWPort1,HWPort6], 4, [1,1], 2>; 151349cc55cSDimitry Andricdefm : HWWriteResPair<WriteMULX64, [HWPort1,HWPort6], 3, [1,1], 2>; 1520b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul64Imm, [HWPort1], 3>; 1530b57cec5SDimitry Andricdefm : HWWriteResPair<WriteIMul64Reg, [HWPort1], 3>; 154349cc55cSDimitry Andricdef HWWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 155349cc55cSDimitry Andricdef : WriteRes<WriteIMulHLd, []> { 156349cc55cSDimitry Andric let Latency = !add(HWWriteIMulH.Latency, HaswellModel.LoadLatency); 157349cc55cSDimitry Andric} 1580b57cec5SDimitry Andric 1590b57cec5SDimitry Andricdefm : X86WriteRes<WriteBSWAP32, [HWPort15], 1, [1], 1>; 1600b57cec5SDimitry Andricdefm : X86WriteRes<WriteBSWAP64, [HWPort06, HWPort15], 2, [1,1], 2>; 1610b57cec5SDimitry Andricdefm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>; 1620b57cec5SDimitry Andricdefm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>; 1630b57cec5SDimitry Andricdefm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>; 1640b57cec5SDimitry Andric 1650b57cec5SDimitry Andric// Integer shifts and rotates. 1660b57cec5SDimitry Andricdefm : HWWriteResPair<WriteShift, [HWPort06], 1>; 1670b57cec5SDimitry Andricdefm : HWWriteResPair<WriteShiftCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 1680b57cec5SDimitry Andricdefm : HWWriteResPair<WriteRotate, [HWPort06], 1, [1], 1>; 1690b57cec5SDimitry Andricdefm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 1700b57cec5SDimitry Andric 1710b57cec5SDimitry Andric// SHLD/SHRD. 1720b57cec5SDimitry Andricdefm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>; 1730b57cec5SDimitry Andricdefm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>; 1740b57cec5SDimitry Andricdefm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>; 1750b57cec5SDimitry Andricdefm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>; 1760b57cec5SDimitry Andric 177349cc55cSDimitry Andric// Branches don't produce values, so they have no latency, but they still 178349cc55cSDimitry Andric// consume resources. Indirect branches can fold loads. 1790b57cec5SDimitry Andricdefm : HWWriteResPair<WriteJump, [HWPort06], 1>; 180349cc55cSDimitry Andric 1810b57cec5SDimitry Andricdefm : HWWriteResPair<WriteCRC32, [HWPort1], 3>; 1820b57cec5SDimitry Andric 1830b57cec5SDimitry Andricdefm : HWWriteResPair<WriteCMOV, [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move. 1840b57cec5SDimitry Andricdefm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move. 185349cc55cSDimitry Andric 1860b57cec5SDimitry Andricdef : WriteRes<WriteSETCC, [HWPort06]>; // Setcc. 1870b57cec5SDimitry Andricdef : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> { 1880b57cec5SDimitry Andric let Latency = 2; 1890b57cec5SDimitry Andric let NumMicroOps = 3; 1900b57cec5SDimitry Andric} 1910b57cec5SDimitry Andric 1920b57cec5SDimitry Andricdefm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>; 1930b57cec5SDimitry Andricdefm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>; 1940b57cec5SDimitry Andricdefm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>; 1950b57cec5SDimitry Andricdefm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>; 1960b57cec5SDimitry Andricdefm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>; 1970b57cec5SDimitry Andricdefm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>; 1980b57cec5SDimitry Andric//defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>; 1990b57cec5SDimitry Andric 2000b57cec5SDimitry Andric// This is for simple LEAs with one or two input operands. 2010b57cec5SDimitry Andric// The complex ones can only execute on port 1, and they require two cycles on 2020b57cec5SDimitry Andric// the port to read all inputs. We don't model that. 2030b57cec5SDimitry Andricdef : WriteRes<WriteLEA, [HWPort15]>; 2040b57cec5SDimitry Andric 2050b57cec5SDimitry Andric// Bit counts. 2060b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBSF, [HWPort1], 3>; 2070b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBSR, [HWPort1], 3>; 2080b57cec5SDimitry Andricdefm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>; 2090b57cec5SDimitry Andricdefm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>; 2100b57cec5SDimitry Andricdefm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>; 2110b57cec5SDimitry Andric 2120b57cec5SDimitry Andric// BMI1 BEXTR/BLS, BMI2 BZHI 2130b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>; 2140b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBLS, [HWPort15], 1>; 2150b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBZHI, [HWPort15], 1>; 2160b57cec5SDimitry Andric 2170b57cec5SDimitry Andric// TODO: Why isn't the HWDivider used? 2180b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>; 2190b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 2200b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 2210b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 2220b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2230b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2240b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2250b57cec5SDimitry Andricdefm : X86WriteRes<WriteDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2260b57cec5SDimitry Andric 2270b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>; 2280b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 2290b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 2300b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 2310b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2320b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2330b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2340b57cec5SDimitry Andricdefm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 2350b57cec5SDimitry Andric 236349cc55cSDimitry Andric// Floating point. This covers both scalar and vector operations. 2370b57cec5SDimitry Andricdefm : X86WriteRes<WriteFLD0, [HWPort01], 1, [1], 1>; 2380b57cec5SDimitry Andricdefm : X86WriteRes<WriteFLD1, [HWPort01], 1, [2], 2>; 2390b57cec5SDimitry Andricdefm : X86WriteRes<WriteFLDC, [HWPort01], 1, [2], 2>; 2400b57cec5SDimitry Andricdefm : X86WriteRes<WriteFLoad, [HWPort23], 5, [1], 1>; 2410b57cec5SDimitry Andricdefm : X86WriteRes<WriteFLoadX, [HWPort23], 6, [1], 1>; 2420b57cec5SDimitry Andricdefm : X86WriteRes<WriteFLoadY, [HWPort23], 7, [1], 1>; 2430b57cec5SDimitry Andricdefm : X86WriteRes<WriteFMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 2440b57cec5SDimitry Andricdefm : X86WriteRes<WriteFMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 2450b57cec5SDimitry Andricdefm : X86WriteRes<WriteFStore, [HWPort237,HWPort4], 1, [1,1], 2>; 2460b57cec5SDimitry Andricdefm : X86WriteRes<WriteFStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 2470b57cec5SDimitry Andricdefm : X86WriteRes<WriteFStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 2480b57cec5SDimitry Andricdefm : X86WriteRes<WriteFStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 2490b57cec5SDimitry Andricdefm : X86WriteRes<WriteFStoreNTX, [HWPort237,HWPort4], 1, [1,1], 2>; 2500b57cec5SDimitry Andricdefm : X86WriteRes<WriteFStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 2518bcb0991SDimitry Andric 2528bcb0991SDimitry Andricdefm : X86WriteRes<WriteFMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 2538bcb0991SDimitry Andricdefm : X86WriteRes<WriteFMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 2548bcb0991SDimitry Andricdefm : X86WriteRes<WriteFMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 2558bcb0991SDimitry Andricdefm : X86WriteRes<WriteFMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 2568bcb0991SDimitry Andric 2570b57cec5SDimitry Andricdefm : X86WriteRes<WriteFMove, [HWPort5], 1, [1], 1>; 2580b57cec5SDimitry Andricdefm : X86WriteRes<WriteFMoveX, [HWPort5], 1, [1], 1>; 2590b57cec5SDimitry Andricdefm : X86WriteRes<WriteFMoveY, [HWPort5], 1, [1], 1>; 260bdd1243dSDimitry Andricdefm : X86WriteRes<WriteFMoveZ, [HWPort5], 1, [1], 1>; // Unsupported = 1 2610b57cec5SDimitry Andricdefm : X86WriteRes<WriteEMMS, [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>; 2620b57cec5SDimitry Andric 2630b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>; 2640b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAddX, [HWPort1], 3, [1], 1, 6>; 2650b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>; 2660b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAddZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 2670b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAdd64, [HWPort1], 3, [1], 1, 5>; 2680b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAdd64X, [HWPort1], 3, [1], 1, 6>; 2690b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAdd64Y, [HWPort1], 3, [1], 1, 7>; 2700b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFAdd64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 2710b57cec5SDimitry Andric 2720b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 5>; 2730b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmpX, [HWPort1], 3, [1], 1, 6>; 2740b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>; 2750b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmpZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 2760b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmp64, [HWPort1], 3, [1], 1, 5>; 2770b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmp64X, [HWPort1], 3, [1], 1, 6>; 2780b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmp64Y, [HWPort1], 3, [1], 1, 7>; 2790b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCmp64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 2800b57cec5SDimitry Andric 2810b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFCom, [HWPort1], 3>; 2825ffd83dbSDimitry Andricdefm : HWWriteResPair<WriteFComX, [HWPort1], 3>; 2830b57cec5SDimitry Andric 2840b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 5>; 2850b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMulX, [HWPort01], 5, [1], 1, 6>; 2860b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>; 2870b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMulZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 2880b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMul64, [HWPort01], 5, [1], 1, 5>; 2890b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMul64X, [HWPort01], 5, [1], 1, 6>; 2900b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMul64Y, [HWPort01], 5, [1], 1, 7>; 2910b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMul64Z, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 2920b57cec5SDimitry Andric 2930b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDiv, [HWPort0,HWFPDivider], 13, [1,7], 1, 5>; 2940b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDivX, [HWPort0,HWFPDivider], 13, [1,7], 1, 6>; 2950b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDivY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 2960b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDivZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 2970b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDiv64, [HWPort0,HWFPDivider], 20, [1,14], 1, 5>; 2980b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>; 2990b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 3000b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 3010b57cec5SDimitry Andric 3020b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRcp, [HWPort0], 5, [1], 1, 5>; 3030b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRcpX, [HWPort0], 5, [1], 1, 6>; 3040b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRcpY, [HWPort0,HWPort015], 11, [2,1], 3, 7>; 3050b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRcpZ, [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 3060b57cec5SDimitry Andric 3070b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5, [1], 1, 5>; 3080b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRsqrtX,[HWPort0], 5, [1], 1, 6>; 3090b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>; 3100b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 3110b57cec5SDimitry Andric 3120b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrt, [HWPort0,HWFPDivider], 11, [1,7], 1, 5>; 3130b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrtX, [HWPort0,HWFPDivider], 11, [1,7], 1, 6>; 3140b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrtY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 3150b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrtZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 3160b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrt64, [HWPort0,HWFPDivider], 16, [1,14], 1, 5>; 3170b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>; 3180b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 3190b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 3200b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSqrt80, [HWPort0,HWFPDivider], 23, [1,17]>; 3210b57cec5SDimitry Andric 3220b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMA, [HWPort01], 5, [1], 1, 5>; 3230b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMAX, [HWPort01], 5, [1], 1, 6>; 3240b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMAY, [HWPort01], 5, [1], 1, 7>; 3250b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFMAZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 3260b57cec5SDimitry Andricdefm : HWWriteResPair<WriteDPPD, [HWPort0,HWPort1,HWPort5], 9, [1,1,1], 3, 6>; 3270b57cec5SDimitry Andricdefm : HWWriteResPair<WriteDPPS, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>; 3280b57cec5SDimitry Andricdefm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; 3290b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFSign, [HWPort0], 1>; 3300b57cec5SDimitry Andricdefm : X86WriteRes<WriteFRnd, [HWPort23], 6, [1], 1>; 3310b57cec5SDimitry Andricdefm : X86WriteRes<WriteFRndY, [HWPort23], 6, [1], 1>; 3320b57cec5SDimitry Andricdefm : X86WriteRes<WriteFRndZ, [HWPort23], 6, [1], 1>; // Unsupported = 1 3330b57cec5SDimitry Andricdefm : X86WriteRes<WriteFRndLd, [HWPort1,HWPort23], 12, [2,1], 3>; 3340b57cec5SDimitry Andricdefm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>; 3350b57cec5SDimitry Andricdefm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1 3360b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>; 3370b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>; 3380b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 3390b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFTest, [HWPort0], 1, [1], 1, 6>; 3400b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFTestY, [HWPort0], 1, [1], 1, 7>; 3410b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFTestZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 3420b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFShuffle, [HWPort5], 1, [1], 1, 6>; 3430b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>; 3440b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 3450b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1, [1], 1, 6>; 3460b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>; 3470b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 3480b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFBlend, [HWPort015], 1, [1], 1, 6>; 3490b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>; 3500b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1 3510b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>; 3520b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>; 3530b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2], 2, 6>; 3540b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>; 3550b57cec5SDimitry Andricdefm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 3560b57cec5SDimitry Andric 3570b57cec5SDimitry Andric// Conversion between integer and float. 358bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtSD2I, [HWPort1,HWPort0], 4, [1,1], 2, 5>; 359bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPD2I, [HWPort1,HWPort5], 4, [1,1], 2, 6>; 360bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPD2IY, [HWPort1,HWPort5], 6, [1,1], 2, 6>; 361bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPD2IZ, [HWPort1,HWPort5], 6, [1,1], 2, 6>; // Unsupported = 1 362bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtSS2I, [HWPort1,HWPort0], 4, [1,1], 2, 5>; 363bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPS2I, [HWPort1], 3, [1], 1, 6>; 364bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3, [1], 1, 7>; 365bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 3660b57cec5SDimitry Andric 367bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtI2SD, [HWPort1,HWPort5], 4, [1,1], 2>; 368bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtI2SDLd, [HWPort1,HWPort23], 9, [1,1], 2>; 369bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtI2PD, [HWPort1,HWPort5], 4, [1,1], 2, 6>; 370bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtI2PDY, [HWPort1,HWPort5], 6, [1,1], 2, 6>; 371bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1,HWPort5], 6, [1,1], 2, 6>; // Unsupported = 1 372bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtI2SS, [HWPort1,HWPort5], 4, [1,1], 2>; 373bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtI2SSLd, [HWPort1,HWPort23], 9, [1,1], 2>; 374bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtI2PS, [HWPort1], 3, [1], 1, 6>; 375bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtI2PSY, [HWPort1], 3, [1], 1, 7>; 376bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtI2PSZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 3770b57cec5SDimitry Andric 378bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtSS2SD, [HWPort0,HWPort5], 2, [1,1], 2>; 379bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtSS2SDLd, [HWPort0,HWPort23], 7, [1,1], 2>; 380bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtPS2PD, [HWPort0,HWPort5], 2, [1,1], 2>; 381bdd1243dSDimitry Andricdefm : X86WriteRes<WriteCvtPS2PDLd, [HWPort0,HWPort23], 6, [1,1], 2>; 382bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPS2PDY, [HWPort0,HWPort5], 4, [1,1], 2, 6>; 383bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort0,HWPort5], 4, [1,1], 2, 6>; // Unsupported = 1 384bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtSD2SS, [HWPort1,HWPort5], 4, [1,1], 2, 5>; 385bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPD2PS, [HWPort1,HWPort5], 4, [1,1], 2, 6>; 386bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1,HWPort5], 6, [1,1], 2, 6>; 387bdd1243dSDimitry Andricdefm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1,HWPort5], 4, [1,1], 2, 6>; // Unsupported = 1 3880b57cec5SDimitry Andric 3890b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPH2PS, [HWPort0,HWPort5], 2, [1,1], 2>; 3900b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPH2PSY, [HWPort0,HWPort5], 2, [1,1], 2>; 3910b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPH2PSZ, [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1 3920b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPH2PSLd, [HWPort0,HWPort23], 6, [1,1], 2>; 3930b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>; 3940b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1 3950b57cec5SDimitry Andric 3960b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPS2PH, [HWPort1,HWPort5], 4, [1,1], 2>; 3970b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPS2PHY, [HWPort1,HWPort5], 6, [1,1], 2>; 3980b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPS2PHZ, [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1 3990b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPS2PHSt, [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>; 4000b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; 4010b57cec5SDimitry Andricdefm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1 4020b57cec5SDimitry Andric 4030b57cec5SDimitry Andric// Vector integer operations. 4040b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecLoad, [HWPort23], 5, [1], 1>; 4050b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecLoadX, [HWPort23], 6, [1], 1>; 4060b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecLoadY, [HWPort23], 7, [1], 1>; 4070b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecLoadNT, [HWPort23], 6, [1], 1>; 4080b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecLoadNTY, [HWPort23], 7, [1], 1>; 4090b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 4100b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 4110b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecStore, [HWPort237,HWPort4], 1, [1,1], 2>; 4120b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 4130b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 4140b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 4150b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 4165ffd83dbSDimitry Andricdefm : X86WriteRes<WriteVecMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 4175ffd83dbSDimitry Andricdefm : X86WriteRes<WriteVecMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 4185ffd83dbSDimitry Andricdefm : X86WriteRes<WriteVecMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 4195ffd83dbSDimitry Andricdefm : X86WriteRes<WriteVecMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 4200b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecMove, [HWPort015], 1, [1], 1>; 4210b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecMoveX, [HWPort015], 1, [1], 1>; 4220b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecMoveY, [HWPort015], 1, [1], 1>; 423bdd1243dSDimitry Andricdefm : X86WriteRes<WriteVecMoveZ, [HWPort015], 1, [1], 1>; // Unsupported = 1 4240b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecMoveToGpr, [HWPort0], 1, [1], 1>; 4250b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecMoveFromGpr, [HWPort5], 1, [1], 1>; 4260b57cec5SDimitry Andric 4270b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>; 4280b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>; 4290b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>; 4300b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1 4310b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecTest, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 4320b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>; 4330b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1 4340b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 5>; 4350b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecALUX, [HWPort15], 1, [1], 1, 6>; 4360b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>; 4370b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecALUZ, [HWPort15], 1, [1], 1, 7>; // Unsupported = 1 4380b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>; 4390b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecIMulX, [HWPort0], 5, [1], 1, 6>; 4400b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecIMulY, [HWPort0], 5, [1], 1, 7>; 4410b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecIMulZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 4420b57cec5SDimitry Andricdefm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>; 4430b57cec5SDimitry Andricdefm : HWWriteResPair<WritePMULLDY, [HWPort0], 10, [2], 2, 7>; 4440b57cec5SDimitry Andricdefm : HWWriteResPair<WritePMULLDZ, [HWPort0], 10, [2], 2, 7>; // Unsupported = 1 4450b57cec5SDimitry Andricdefm : HWWriteResPair<WriteShuffle, [HWPort5], 1, [1], 1, 5>; 4460b57cec5SDimitry Andricdefm : HWWriteResPair<WriteShuffleX, [HWPort5], 1, [1], 1, 6>; 4470b57cec5SDimitry Andricdefm : HWWriteResPair<WriteShuffleY, [HWPort5], 1, [1], 1, 7>; 4480b57cec5SDimitry Andricdefm : HWWriteResPair<WriteShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 4490b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>; 4500b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>; 4510b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>; 4520b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1 4530b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>; 4540b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>; 4550b57cec5SDimitry Andricdefm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 4560b57cec5SDimitry Andricdefm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>; 457fe6060f1SDimitry Andricdefm : HWWriteResPair<WriteVPMOV256, [HWPort5], 3, [1], 1, 7>; 4580b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>; 4590b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>; 4600b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>; 4610b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 4620b57cec5SDimitry Andricdefm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>; 4630b57cec5SDimitry Andricdefm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; 4640b57cec5SDimitry Andricdefm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1 4650b57cec5SDimitry Andricdefm : HWWriteResPair<WritePSADBW, [HWPort0], 5, [1], 1, 5>; 4660b57cec5SDimitry Andricdefm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>; 4670b57cec5SDimitry Andricdefm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>; 4680b57cec5SDimitry Andricdefm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 4690b57cec5SDimitry Andricdefm : HWWriteResPair<WritePHMINPOS, [HWPort0], 5, [1], 1, 6>; 4700b57cec5SDimitry Andric 4710b57cec5SDimitry Andric// Vector integer shifts. 4720b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecShift, [HWPort0], 1, [1], 1, 5>; 4730b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecShiftX, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 4740b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecShiftY, [HWPort0,HWPort5], 4, [1,1], 2>; 4750b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecShiftZ, [HWPort0,HWPort5], 4, [1,1], 2>; // Unsupported = 1 4760b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecShiftYLd, [HWPort0,HWPort23], 8, [1,1], 2>; 4770b57cec5SDimitry Andricdefm : X86WriteRes<WriteVecShiftZLd, [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1 4780b57cec5SDimitry Andric 4790b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecShiftImm, [HWPort0], 1, [1], 1, 5>; 4800b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>; 4810b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>; 4820b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 4830b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 3, [2,1], 3, 6>; 4840b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>; 4850b57cec5SDimitry Andricdefm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1 4860b57cec5SDimitry Andric 4870b57cec5SDimitry Andric// Vector insert/extract operations. 4880b57cec5SDimitry Andricdef : WriteRes<WriteVecInsert, [HWPort5]> { 4890b57cec5SDimitry Andric let Latency = 2; 4900b57cec5SDimitry Andric let NumMicroOps = 2; 4915f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 4920b57cec5SDimitry Andric} 4930b57cec5SDimitry Andricdef : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> { 4940b57cec5SDimitry Andric let Latency = 6; 4950b57cec5SDimitry Andric let NumMicroOps = 2; 4960b57cec5SDimitry Andric} 4970b57cec5SDimitry Andricdef: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 4980b57cec5SDimitry Andric 4990b57cec5SDimitry Andricdef : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> { 5000b57cec5SDimitry Andric let Latency = 2; 5010b57cec5SDimitry Andric let NumMicroOps = 2; 5020b57cec5SDimitry Andric} 5030b57cec5SDimitry Andricdef : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> { 5040b57cec5SDimitry Andric let Latency = 2; 5050b57cec5SDimitry Andric let NumMicroOps = 3; 5060b57cec5SDimitry Andric} 5070b57cec5SDimitry Andric 5080b57cec5SDimitry Andric// String instructions. 5090b57cec5SDimitry Andric 5100b57cec5SDimitry Andric// Packed Compare Implicit Length Strings, Return Mask 5110b57cec5SDimitry Andricdef : WriteRes<WritePCmpIStrM, [HWPort0]> { 5120b57cec5SDimitry Andric let Latency = 11; 5130b57cec5SDimitry Andric let NumMicroOps = 3; 5145f757f3fSDimitry Andric let ReleaseAtCycles = [3]; 5150b57cec5SDimitry Andric} 5160b57cec5SDimitry Andricdef : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> { 5170b57cec5SDimitry Andric let Latency = 17; 5180b57cec5SDimitry Andric let NumMicroOps = 4; 5195f757f3fSDimitry Andric let ReleaseAtCycles = [3,1]; 5200b57cec5SDimitry Andric} 5210b57cec5SDimitry Andric 5220b57cec5SDimitry Andric// Packed Compare Explicit Length Strings, Return Mask 5230b57cec5SDimitry Andricdef : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> { 5240b57cec5SDimitry Andric let Latency = 19; 5250b57cec5SDimitry Andric let NumMicroOps = 9; 5265f757f3fSDimitry Andric let ReleaseAtCycles = [4,3,1,1]; 5270b57cec5SDimitry Andric} 5280b57cec5SDimitry Andricdef : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> { 5290b57cec5SDimitry Andric let Latency = 25; 5300b57cec5SDimitry Andric let NumMicroOps = 10; 5315f757f3fSDimitry Andric let ReleaseAtCycles = [4,3,1,1,1]; 5320b57cec5SDimitry Andric} 5330b57cec5SDimitry Andric 5340b57cec5SDimitry Andric// Packed Compare Implicit Length Strings, Return Index 5350b57cec5SDimitry Andricdef : WriteRes<WritePCmpIStrI, [HWPort0]> { 5360b57cec5SDimitry Andric let Latency = 11; 5370b57cec5SDimitry Andric let NumMicroOps = 3; 5385f757f3fSDimitry Andric let ReleaseAtCycles = [3]; 5390b57cec5SDimitry Andric} 5400b57cec5SDimitry Andricdef : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> { 5410b57cec5SDimitry Andric let Latency = 17; 5420b57cec5SDimitry Andric let NumMicroOps = 4; 5435f757f3fSDimitry Andric let ReleaseAtCycles = [3,1]; 5440b57cec5SDimitry Andric} 5450b57cec5SDimitry Andric 5460b57cec5SDimitry Andric// Packed Compare Explicit Length Strings, Return Index 5470b57cec5SDimitry Andricdef : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> { 5480b57cec5SDimitry Andric let Latency = 18; 5490b57cec5SDimitry Andric let NumMicroOps = 8; 5505f757f3fSDimitry Andric let ReleaseAtCycles = [4,3,1]; 5510b57cec5SDimitry Andric} 5520b57cec5SDimitry Andricdef : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> { 5530b57cec5SDimitry Andric let Latency = 24; 5540b57cec5SDimitry Andric let NumMicroOps = 9; 5555f757f3fSDimitry Andric let ReleaseAtCycles = [4,3,1,1]; 5560b57cec5SDimitry Andric} 5570b57cec5SDimitry Andric 5580b57cec5SDimitry Andric// MOVMSK Instructions. 5590b57cec5SDimitry Andricdef : WriteRes<WriteFMOVMSK, [HWPort0]> { let Latency = 3; } 5600b57cec5SDimitry Andricdef : WriteRes<WriteVecMOVMSK, [HWPort0]> { let Latency = 3; } 5610b57cec5SDimitry Andricdef : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; } 5620b57cec5SDimitry Andricdef : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; } 5630b57cec5SDimitry Andric 5640b57cec5SDimitry Andric// AES Instructions. 5650b57cec5SDimitry Andricdef : WriteRes<WriteAESDecEnc, [HWPort5]> { 5660b57cec5SDimitry Andric let Latency = 7; 5670b57cec5SDimitry Andric let NumMicroOps = 1; 5685f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 5690b57cec5SDimitry Andric} 5700b57cec5SDimitry Andricdef : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> { 5710b57cec5SDimitry Andric let Latency = 13; 5720b57cec5SDimitry Andric let NumMicroOps = 2; 5735f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 5740b57cec5SDimitry Andric} 5750b57cec5SDimitry Andric 5760b57cec5SDimitry Andricdef : WriteRes<WriteAESIMC, [HWPort5]> { 5770b57cec5SDimitry Andric let Latency = 14; 5780b57cec5SDimitry Andric let NumMicroOps = 2; 5795f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 5800b57cec5SDimitry Andric} 5810b57cec5SDimitry Andricdef : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> { 5820b57cec5SDimitry Andric let Latency = 20; 5830b57cec5SDimitry Andric let NumMicroOps = 3; 5845f757f3fSDimitry Andric let ReleaseAtCycles = [2,1]; 5850b57cec5SDimitry Andric} 5860b57cec5SDimitry Andric 5870b57cec5SDimitry Andricdef : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> { 5880b57cec5SDimitry Andric let Latency = 29; 5890b57cec5SDimitry Andric let NumMicroOps = 11; 5905f757f3fSDimitry Andric let ReleaseAtCycles = [2,7,2]; 5910b57cec5SDimitry Andric} 5920b57cec5SDimitry Andricdef : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> { 5930b57cec5SDimitry Andric let Latency = 34; 5940b57cec5SDimitry Andric let NumMicroOps = 11; 5955f757f3fSDimitry Andric let ReleaseAtCycles = [2,7,1,1]; 5960b57cec5SDimitry Andric} 5970b57cec5SDimitry Andric 5980b57cec5SDimitry Andric// Carry-less multiplication instructions. 5990b57cec5SDimitry Andricdef : WriteRes<WriteCLMul, [HWPort0, HWPort5]> { 6000b57cec5SDimitry Andric let Latency = 11; 6010b57cec5SDimitry Andric let NumMicroOps = 3; 6025f757f3fSDimitry Andric let ReleaseAtCycles = [2,1]; 6030b57cec5SDimitry Andric} 6040b57cec5SDimitry Andricdef : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> { 6050b57cec5SDimitry Andric let Latency = 17; 6060b57cec5SDimitry Andric let NumMicroOps = 4; 6075f757f3fSDimitry Andric let ReleaseAtCycles = [2,1,1]; 6080b57cec5SDimitry Andric} 6090b57cec5SDimitry Andric 6100b57cec5SDimitry Andric// Load/store MXCSR. 6115f757f3fSDimitry Andricdef : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 6125f757f3fSDimitry Andricdef : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 6130b57cec5SDimitry Andric 614349cc55cSDimitry Andric// Catch-all for expensive system instructions. 6150b57cec5SDimitry Andricdef : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; } 616349cc55cSDimitry Andric 617349cc55cSDimitry Andric// Old microcoded instructions that nobody use. 6180b57cec5SDimitry Andricdef : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } 619349cc55cSDimitry Andric 620349cc55cSDimitry Andric// Fence instructions. 6210b57cec5SDimitry Andricdef : WriteRes<WriteFence, [HWPort23, HWPort4]>; 622349cc55cSDimitry Andric 623349cc55cSDimitry Andric// Nop, not very useful expect it provides a model for nops! 6240b57cec5SDimitry Andricdef : WriteRes<WriteNop, []>; 6250b57cec5SDimitry Andric 626349cc55cSDimitry Andric//////////////////////////////////////////////////////////////////////////////// 627349cc55cSDimitry Andric// Horizontal add/sub instructions. 628349cc55cSDimitry Andric//////////////////////////////////////////////////////////////////////////////// 629349cc55cSDimitry Andric 630349cc55cSDimitry Andricdefm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1,2], 3, 6>; 631349cc55cSDimitry Andricdefm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>; 632349cc55cSDimitry Andricdefm : HWWriteResPair<WritePHAdd, [HWPort5, HWPort15], 3, [2,1], 3, 5>; 633349cc55cSDimitry Andricdefm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>; 634349cc55cSDimitry Andricdefm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>; 635349cc55cSDimitry Andric 6360b57cec5SDimitry Andric//================ Exceptions ================// 6370b57cec5SDimitry Andric 6380b57cec5SDimitry Andric//-- Specific Scheduling Models --// 6390b57cec5SDimitry Andric 6400b57cec5SDimitry Andric// Starting with P0. 6410b57cec5SDimitry Andricdef HWWriteP0 : SchedWriteRes<[HWPort0]>; 6420b57cec5SDimitry Andric 6430b57cec5SDimitry Andricdef HWWriteP01 : SchedWriteRes<[HWPort01]>; 6440b57cec5SDimitry Andric 6450b57cec5SDimitry Andricdef HWWrite2P01 : SchedWriteRes<[HWPort01]> { 6460b57cec5SDimitry Andric let NumMicroOps = 2; 6470b57cec5SDimitry Andric} 6480b57cec5SDimitry Andricdef HWWrite3P01 : SchedWriteRes<[HWPort01]> { 6490b57cec5SDimitry Andric let NumMicroOps = 3; 6500b57cec5SDimitry Andric} 6510b57cec5SDimitry Andric 6520b57cec5SDimitry Andricdef HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 6530b57cec5SDimitry Andric let NumMicroOps = 2; 6540b57cec5SDimitry Andric} 6550b57cec5SDimitry Andric 6560b57cec5SDimitry Andricdef HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 6570b57cec5SDimitry Andric let NumMicroOps = 3; 6585f757f3fSDimitry Andric let ReleaseAtCycles = [2, 1]; 6590b57cec5SDimitry Andric} 6600b57cec5SDimitry Andric 6610b57cec5SDimitry Andric// Starting with P1. 6620b57cec5SDimitry Andricdef HWWriteP1 : SchedWriteRes<[HWPort1]>; 6630b57cec5SDimitry Andric 6640b57cec5SDimitry Andric 6650b57cec5SDimitry Andricdef HWWrite2P1 : SchedWriteRes<[HWPort1]> { 6660b57cec5SDimitry Andric let NumMicroOps = 2; 6675f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 6680b57cec5SDimitry Andric} 6690b57cec5SDimitry Andric 6700b57cec5SDimitry Andric// Notation: 6710b57cec5SDimitry Andric// - r: register. 6720b57cec5SDimitry Andric// - mm: 64 bit mmx register. 6730b57cec5SDimitry Andric// - x = 128 bit xmm register. 6740b57cec5SDimitry Andric// - (x)mm = mmx or xmm register. 6750b57cec5SDimitry Andric// - y = 256 bit ymm register. 6760b57cec5SDimitry Andric// - v = any vector register. 6770b57cec5SDimitry Andric// - m = memory. 6780b57cec5SDimitry Andric 6790b57cec5SDimitry Andric//=== Integer Instructions ===// 6800b57cec5SDimitry Andric//-- Move instructions --// 6810b57cec5SDimitry Andric 6820b57cec5SDimitry Andric// XLAT. 6830b57cec5SDimitry Andricdef HWWriteXLAT : SchedWriteRes<[]> { 6840b57cec5SDimitry Andric let Latency = 7; 6850b57cec5SDimitry Andric let NumMicroOps = 3; 6860b57cec5SDimitry Andric} 6870b57cec5SDimitry Andricdef : InstRW<[HWWriteXLAT], (instrs XLAT)>; 6880b57cec5SDimitry Andric 6890b57cec5SDimitry Andric// PUSHA. 6900b57cec5SDimitry Andricdef HWWritePushA : SchedWriteRes<[]> { 6910b57cec5SDimitry Andric let NumMicroOps = 19; 6920b57cec5SDimitry Andric} 6930b57cec5SDimitry Andricdef : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>; 6940b57cec5SDimitry Andric 6950b57cec5SDimitry Andric// POPA. 6960b57cec5SDimitry Andricdef HWWritePopA : SchedWriteRes<[]> { 6970b57cec5SDimitry Andric let NumMicroOps = 18; 6980b57cec5SDimitry Andric} 6990b57cec5SDimitry Andricdef : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>; 7000b57cec5SDimitry Andric 7010b57cec5SDimitry Andric//-- Arithmetic instructions --// 7020b57cec5SDimitry Andric 7030b57cec5SDimitry Andric// BTR BTS BTC. 7040b57cec5SDimitry Andric// m,r. 7050b57cec5SDimitry Andricdef HWWriteBTRSCmr : SchedWriteRes<[]> { 7060b57cec5SDimitry Andric let NumMicroOps = 11; 7070b57cec5SDimitry Andric} 7080b57cec5SDimitry Andricdef : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>; 7090b57cec5SDimitry Andric 7100b57cec5SDimitry Andric//-- Control transfer instructions --// 7110b57cec5SDimitry Andric 7120b57cec5SDimitry Andric// CALL. 7130b57cec5SDimitry Andric// i. 7140b57cec5SDimitry Andricdef HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { 7150b57cec5SDimitry Andric let NumMicroOps = 4; 7165f757f3fSDimitry Andric let ReleaseAtCycles = [1, 2, 1]; 7170b57cec5SDimitry Andric} 718349cc55cSDimitry Andricdef : InstRW<[HWWriteRETI], (instregex "RETI(16|32|64)", "LRETI(16|32|64)")>; 7190b57cec5SDimitry Andric 7200b57cec5SDimitry Andric// BOUND. 7210b57cec5SDimitry Andric// r,m. 7220b57cec5SDimitry Andricdef HWWriteBOUND : SchedWriteRes<[]> { 7230b57cec5SDimitry Andric let NumMicroOps = 15; 7240b57cec5SDimitry Andric} 7250b57cec5SDimitry Andricdef : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; 7260b57cec5SDimitry Andric 7270b57cec5SDimitry Andric// INTO. 7280b57cec5SDimitry Andricdef HWWriteINTO : SchedWriteRes<[]> { 7290b57cec5SDimitry Andric let NumMicroOps = 4; 7300b57cec5SDimitry Andric} 7310b57cec5SDimitry Andricdef : InstRW<[HWWriteINTO], (instrs INTO)>; 7320b57cec5SDimitry Andric 7330b57cec5SDimitry Andric//-- String instructions --// 7340b57cec5SDimitry Andric 7350b57cec5SDimitry Andric// LODSB/W. 7360b57cec5SDimitry Andricdef : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>; 7370b57cec5SDimitry Andric 7380b57cec5SDimitry Andric// LODSD/Q. 7390b57cec5SDimitry Andricdef : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>; 7400b57cec5SDimitry Andric 7410b57cec5SDimitry Andric// MOVS. 7420b57cec5SDimitry Andricdef HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { 7430b57cec5SDimitry Andric let Latency = 4; 7440b57cec5SDimitry Andric let NumMicroOps = 5; 7455f757f3fSDimitry Andric let ReleaseAtCycles = [2, 1, 2]; 7460b57cec5SDimitry Andric} 7470b57cec5SDimitry Andricdef : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 7480b57cec5SDimitry Andric 7490b57cec5SDimitry Andric// CMPS. 7500b57cec5SDimitry Andricdef HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { 7510b57cec5SDimitry Andric let Latency = 4; 7520b57cec5SDimitry Andric let NumMicroOps = 5; 7535f757f3fSDimitry Andric let ReleaseAtCycles = [2, 3]; 7540b57cec5SDimitry Andric} 7550b57cec5SDimitry Andricdef : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>; 7560b57cec5SDimitry Andric 7570b57cec5SDimitry Andric//-- Other --// 7580b57cec5SDimitry Andric 7590b57cec5SDimitry Andric// RDPMC.f 7600b57cec5SDimitry Andricdef HWWriteRDPMC : SchedWriteRes<[]> { 7610b57cec5SDimitry Andric let NumMicroOps = 34; 7620b57cec5SDimitry Andric} 7630b57cec5SDimitry Andricdef : InstRW<[HWWriteRDPMC], (instrs RDPMC)>; 7640b57cec5SDimitry Andric 7650b57cec5SDimitry Andric// RDRAND. 7660b57cec5SDimitry Andricdef HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { 7670b57cec5SDimitry Andric let NumMicroOps = 17; 7685f757f3fSDimitry Andric let ReleaseAtCycles = [1, 16]; 7690b57cec5SDimitry Andric} 7700b57cec5SDimitry Andricdef : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 7710b57cec5SDimitry Andric 7720b57cec5SDimitry Andric//=== Floating Point x87 Instructions ===// 7730b57cec5SDimitry Andric//-- Move instructions --// 7740b57cec5SDimitry Andric 7750b57cec5SDimitry Andric// FLD. 7760b57cec5SDimitry Andric// m80. 7770b57cec5SDimitry Andricdef : InstRW<[HWWriteP01], (instrs LD_Frr)>; 7780b57cec5SDimitry Andric 7790b57cec5SDimitry Andric// FBLD. 7800b57cec5SDimitry Andric// m80. 7810b57cec5SDimitry Andricdef HWWriteFBLD : SchedWriteRes<[]> { 7820b57cec5SDimitry Andric let Latency = 47; 7830b57cec5SDimitry Andric let NumMicroOps = 43; 7840b57cec5SDimitry Andric} 7850b57cec5SDimitry Andricdef : InstRW<[HWWriteFBLD], (instrs FBLDm)>; 7860b57cec5SDimitry Andric 7870b57cec5SDimitry Andric// FST(P). 7880b57cec5SDimitry Andric// r. 7890b57cec5SDimitry Andricdef : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>; 7900b57cec5SDimitry Andric 7910b57cec5SDimitry Andric// FFREE. 7920b57cec5SDimitry Andricdef : InstRW<[HWWriteP01], (instregex "FFREE")>; 7930b57cec5SDimitry Andric 7940b57cec5SDimitry Andric// FNSAVE. 7950b57cec5SDimitry Andricdef HWWriteFNSAVE : SchedWriteRes<[]> { 7960b57cec5SDimitry Andric let NumMicroOps = 147; 7970b57cec5SDimitry Andric} 7980b57cec5SDimitry Andricdef : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>; 7990b57cec5SDimitry Andric 8000b57cec5SDimitry Andric// FRSTOR. 8010b57cec5SDimitry Andricdef HWWriteFRSTOR : SchedWriteRes<[]> { 8020b57cec5SDimitry Andric let NumMicroOps = 90; 8030b57cec5SDimitry Andric} 8040b57cec5SDimitry Andricdef : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>; 8050b57cec5SDimitry Andric 8060b57cec5SDimitry Andric//-- Arithmetic instructions --// 8070b57cec5SDimitry Andric 8080b57cec5SDimitry Andric// FCOMPP FUCOMPP. 8090b57cec5SDimitry Andric// r. 8100b57cec5SDimitry Andricdef : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>; 8110b57cec5SDimitry Andric 8120b57cec5SDimitry Andric// FCOMI(P) FUCOMI(P). 8130b57cec5SDimitry Andric// m. 8140b57cec5SDimitry Andricdef : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 8150b57cec5SDimitry Andric 8160b57cec5SDimitry Andric// FTST. 8170b57cec5SDimitry Andricdef : InstRW<[HWWriteP1], (instregex "TST_F")>; 8180b57cec5SDimitry Andric 8190b57cec5SDimitry Andric// FXAM. 820fe6060f1SDimitry Andricdef : InstRW<[HWWrite2P1], (instrs XAM_F)>; 8210b57cec5SDimitry Andric 8220b57cec5SDimitry Andric// FPREM. 8230b57cec5SDimitry Andricdef HWWriteFPREM : SchedWriteRes<[]> { 8240b57cec5SDimitry Andric let Latency = 19; 8250b57cec5SDimitry Andric let NumMicroOps = 28; 8260b57cec5SDimitry Andric} 8270b57cec5SDimitry Andricdef : InstRW<[HWWriteFPREM], (instrs FPREM)>; 8280b57cec5SDimitry Andric 8290b57cec5SDimitry Andric// FPREM1. 8300b57cec5SDimitry Andricdef HWWriteFPREM1 : SchedWriteRes<[]> { 8310b57cec5SDimitry Andric let Latency = 27; 8320b57cec5SDimitry Andric let NumMicroOps = 41; 8330b57cec5SDimitry Andric} 8340b57cec5SDimitry Andricdef : InstRW<[HWWriteFPREM1], (instrs FPREM1)>; 8350b57cec5SDimitry Andric 8360b57cec5SDimitry Andric// FRNDINT. 8370b57cec5SDimitry Andricdef HWWriteFRNDINT : SchedWriteRes<[]> { 8380b57cec5SDimitry Andric let Latency = 11; 8390b57cec5SDimitry Andric let NumMicroOps = 17; 8400b57cec5SDimitry Andric} 8410b57cec5SDimitry Andricdef : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>; 8420b57cec5SDimitry Andric 8430b57cec5SDimitry Andric//-- Math instructions --// 8440b57cec5SDimitry Andric 8450b57cec5SDimitry Andric// FSCALE. 8460b57cec5SDimitry Andricdef HWWriteFSCALE : SchedWriteRes<[]> { 8470b57cec5SDimitry Andric let Latency = 75; // 49-125 8480b57cec5SDimitry Andric let NumMicroOps = 50; // 25-75 8490b57cec5SDimitry Andric} 8500b57cec5SDimitry Andricdef : InstRW<[HWWriteFSCALE], (instrs FSCALE)>; 8510b57cec5SDimitry Andric 8520b57cec5SDimitry Andric// FXTRACT. 8530b57cec5SDimitry Andricdef HWWriteFXTRACT : SchedWriteRes<[]> { 8540b57cec5SDimitry Andric let Latency = 15; 8550b57cec5SDimitry Andric let NumMicroOps = 17; 8560b57cec5SDimitry Andric} 8570b57cec5SDimitry Andricdef : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>; 8580b57cec5SDimitry Andric 8590b57cec5SDimitry Andric//=== Floating Point XMM and YMM Instructions ===// 8600b57cec5SDimitry Andric 8610b57cec5SDimitry Andric// Remaining instrs. 8620b57cec5SDimitry Andric 8630b57cec5SDimitry Andricdef HWWriteResGroup0 : SchedWriteRes<[HWPort23]> { 8640b57cec5SDimitry Andric let Latency = 6; 8650b57cec5SDimitry Andric let NumMicroOps = 1; 8665f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 8670b57cec5SDimitry Andric} 8680b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>; 8690b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm", 8700b57cec5SDimitry Andric "(V?)MOVSLDUPrm", 871bdd1243dSDimitry Andric "(V?)MOVDDUPrm", 8720b57cec5SDimitry Andric "VPBROADCAST(D|Q)rm")>; 8730b57cec5SDimitry Andric 8740b57cec5SDimitry Andricdef HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> { 8750b57cec5SDimitry Andric let Latency = 7; 8760b57cec5SDimitry Andric let NumMicroOps = 1; 8775f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 8780b57cec5SDimitry Andric} 8795f757f3fSDimitry Andricdef: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128rm, 8805f757f3fSDimitry Andric VBROADCASTI128rm, 8810b57cec5SDimitry Andric VBROADCASTSDYrm, 8820b57cec5SDimitry Andric VBROADCASTSSYrm, 8830b57cec5SDimitry Andric VMOVDDUPYrm, 8840b57cec5SDimitry Andric VMOVSHDUPYrm, 8850b57cec5SDimitry Andric VMOVSLDUPYrm)>; 8860b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m", 8870b57cec5SDimitry Andric "VPBROADCAST(D|Q)Yrm")>; 8880b57cec5SDimitry Andric 8890b57cec5SDimitry Andricdef HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { 8900b57cec5SDimitry Andric let Latency = 1; 8910b57cec5SDimitry Andric let NumMicroOps = 2; 8925f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 8930b57cec5SDimitry Andric} 8940b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>; 8950b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>; 8960b57cec5SDimitry Andric 8970b57cec5SDimitry Andricdef HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { 8980b57cec5SDimitry Andric let Latency = 1; 8990b57cec5SDimitry Andric let NumMicroOps = 1; 9005f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9010b57cec5SDimitry Andric} 9020b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr", 9030b57cec5SDimitry Andric "VPSRLVQ(Y?)rr")>; 9040b57cec5SDimitry Andric 9050b57cec5SDimitry Andricdef HWWriteResGroup3 : SchedWriteRes<[HWPort1]> { 9060b57cec5SDimitry Andric let Latency = 1; 9070b57cec5SDimitry Andric let NumMicroOps = 1; 9085f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9090b57cec5SDimitry Andric} 9100b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r", 9110b57cec5SDimitry Andric "UCOM_F(P?)r")>; 9120b57cec5SDimitry Andric 9130b57cec5SDimitry Andricdef HWWriteResGroup4 : SchedWriteRes<[HWPort5]> { 9140b57cec5SDimitry Andric let Latency = 1; 9150b57cec5SDimitry Andric let NumMicroOps = 1; 9165f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9170b57cec5SDimitry Andric} 9180b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>; 9190b57cec5SDimitry Andric 9200b57cec5SDimitry Andricdef HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { 9210b57cec5SDimitry Andric let Latency = 1; 9220b57cec5SDimitry Andric let NumMicroOps = 1; 9235f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9240b57cec5SDimitry Andric} 9250b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>; 9260b57cec5SDimitry Andric 9270b57cec5SDimitry Andricdef HWWriteResGroup6 : SchedWriteRes<[HWPort01]> { 9280b57cec5SDimitry Andric let Latency = 1; 9290b57cec5SDimitry Andric let NumMicroOps = 1; 9305f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9310b57cec5SDimitry Andric} 9320b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>; 9330b57cec5SDimitry Andric 9340b57cec5SDimitry Andricdef HWWriteResGroup7 : SchedWriteRes<[HWPort06]> { 9350b57cec5SDimitry Andric let Latency = 1; 9360b57cec5SDimitry Andric let NumMicroOps = 1; 9375f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9380b57cec5SDimitry Andric} 9390b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>; 9400b57cec5SDimitry Andric 9410b57cec5SDimitry Andricdef HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { 9420b57cec5SDimitry Andric let Latency = 1; 9430b57cec5SDimitry Andric let NumMicroOps = 1; 9445f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9450b57cec5SDimitry Andric} 9460b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>; 9470b57cec5SDimitry Andric 9480b57cec5SDimitry Andricdef HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { 9490b57cec5SDimitry Andric let Latency = 1; 9500b57cec5SDimitry Andric let NumMicroOps = 1; 9515f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9520b57cec5SDimitry Andric} 9530b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>; 9540b57cec5SDimitry Andric 9550b57cec5SDimitry Andricdef HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { 9560b57cec5SDimitry Andric let Latency = 1; 9570b57cec5SDimitry Andric let NumMicroOps = 1; 9585f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 9590b57cec5SDimitry Andric} 960bdd1243dSDimitry Andricdef: InstRW<[HWWriteResGroup10], (instrs SGDT64m, 9610b57cec5SDimitry Andric SIDT64m, 9620b57cec5SDimitry Andric SMSW16m, 9630b57cec5SDimitry Andric STRm, 9640b57cec5SDimitry Andric SYSCALL)>; 9650b57cec5SDimitry Andric 9660b57cec5SDimitry Andricdef HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> { 9670b57cec5SDimitry Andric let Latency = 7; 9680b57cec5SDimitry Andric let NumMicroOps = 2; 9695f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 9700b57cec5SDimitry Andric} 9710b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>; 9720b57cec5SDimitry Andric 9730b57cec5SDimitry Andricdef HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> { 9740b57cec5SDimitry Andric let Latency = 8; 9750b57cec5SDimitry Andric let NumMicroOps = 2; 9765f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 9770b57cec5SDimitry Andric} 9780b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>; 9790b57cec5SDimitry Andric 9800b57cec5SDimitry Andricdef HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> { 9810b57cec5SDimitry Andric let Latency = 8; 9820b57cec5SDimitry Andric let NumMicroOps = 2; 9835f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 9840b57cec5SDimitry Andric} 9850eae32dcSDimitry Andricdef: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSrm)>; 9860b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>; 9870b57cec5SDimitry Andric 9880b57cec5SDimitry Andricdef HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> { 9890b57cec5SDimitry Andric let Latency = 6; 9900b57cec5SDimitry Andric let NumMicroOps = 2; 9915f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 9920b57cec5SDimitry Andric} 9930b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm", 9940b57cec5SDimitry Andric "(V?)PMOV(SX|ZX)BQrm", 9950b57cec5SDimitry Andric "(V?)PMOV(SX|ZX)BWrm", 9960b57cec5SDimitry Andric "(V?)PMOV(SX|ZX)DQrm", 9970b57cec5SDimitry Andric "(V?)PMOV(SX|ZX)WDrm", 9980b57cec5SDimitry Andric "(V?)PMOV(SX|ZX)WQrm")>; 9990b57cec5SDimitry Andric 10000b57cec5SDimitry Andricdef HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> { 10010b57cec5SDimitry Andric let Latency = 8; 10020b57cec5SDimitry Andric let NumMicroOps = 2; 10035f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 10040b57cec5SDimitry Andric} 10050b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm, 10060b57cec5SDimitry Andric VPMOVSXBQYrm, 10070b57cec5SDimitry Andric VPMOVSXWQYrm)>; 10080b57cec5SDimitry Andric 10090b57cec5SDimitry Andricdef HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> { 10100b57cec5SDimitry Andric let Latency = 6; 10110b57cec5SDimitry Andric let NumMicroOps = 2; 10125f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 10130b57cec5SDimitry Andric} 10145ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup14], (instrs FARJMP64m)>; 10150b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>; 10160b57cec5SDimitry Andric 10170b57cec5SDimitry Andricdef HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { 10180b57cec5SDimitry Andric let Latency = 6; 10190b57cec5SDimitry Andric let NumMicroOps = 2; 10205f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 10210b57cec5SDimitry Andric} 10220b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm", 10230b57cec5SDimitry Andric "MOVBE(16|32|64)rm")>; 10240b57cec5SDimitry Andric 10250b57cec5SDimitry Andricdef HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> { 10260b57cec5SDimitry Andric let Latency = 7; 10270b57cec5SDimitry Andric let NumMicroOps = 2; 10285f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 10290b57cec5SDimitry Andric} 10300b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm, 10310b57cec5SDimitry Andric VINSERTI128rm, 10320b57cec5SDimitry Andric VPBLENDDrmi)>; 10330b57cec5SDimitry Andric 10340b57cec5SDimitry Andricdef HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> { 10350b57cec5SDimitry Andric let Latency = 8; 10360b57cec5SDimitry Andric let NumMicroOps = 2; 10375f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 10380b57cec5SDimitry Andric} 10390b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>; 10400b57cec5SDimitry Andric 10410b57cec5SDimitry Andricdef HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> { 10420b57cec5SDimitry Andric let Latency = 6; 10430b57cec5SDimitry Andric let NumMicroOps = 2; 10445f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 10450b57cec5SDimitry Andric} 10460b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>; 10470b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>; 10480b57cec5SDimitry Andric 10490b57cec5SDimitry Andricdef HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> { 10500b57cec5SDimitry Andric let Latency = 2; 10510b57cec5SDimitry Andric let NumMicroOps = 2; 10525f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 10530b57cec5SDimitry Andric} 10540b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup19], (instrs SFENCE)>; 10550b57cec5SDimitry Andric 10560b57cec5SDimitry Andricdef HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { 10570b57cec5SDimitry Andric let Latency = 2; 10580b57cec5SDimitry Andric let NumMicroOps = 3; 10595f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 10600b57cec5SDimitry Andric} 10610b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>; 10620b57cec5SDimitry Andric 10630b57cec5SDimitry Andricdef HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { 10640b57cec5SDimitry Andric let Latency = 2; 10650b57cec5SDimitry Andric let NumMicroOps = 3; 10665f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 10670b57cec5SDimitry Andric} 10680b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>; 10690b57cec5SDimitry Andric 10700b57cec5SDimitry Andricdef HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { 10710b57cec5SDimitry Andric let Latency = 2; 10720b57cec5SDimitry Andric let NumMicroOps = 3; 10735f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 10740b57cec5SDimitry Andric} 10750b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>; 10760b57cec5SDimitry Andric 10770b57cec5SDimitry Andricdef HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 10780b57cec5SDimitry Andric let Latency = 2; 10790b57cec5SDimitry Andric let NumMicroOps = 3; 10805f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 10810b57cec5SDimitry Andric} 10820b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 10830b57cec5SDimitry Andric STOSB, STOSL, STOSQ, STOSW)>; 10840b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>; 10850b57cec5SDimitry Andric 10860b57cec5SDimitry Andricdef HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 10870b57cec5SDimitry Andric let Latency = 7; 10880b57cec5SDimitry Andric let NumMicroOps = 4; 10895f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1]; 10900b57cec5SDimitry Andric} 10910b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)", 10920b57cec5SDimitry Andric "SHL(8|16|32|64)m(1|i)", 10930b57cec5SDimitry Andric "SHR(8|16|32|64)m(1|i)")>; 10940b57cec5SDimitry Andric 10950b57cec5SDimitry Andricdef HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 10960b57cec5SDimitry Andric let Latency = 7; 10970b57cec5SDimitry Andric let NumMicroOps = 4; 10985f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1]; 10990b57cec5SDimitry Andric} 11000b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm", 11010b57cec5SDimitry Andric "PUSH(16|32|64)rmm")>; 11020b57cec5SDimitry Andric 11030b57cec5SDimitry Andricdef HWWriteResGroup28 : SchedWriteRes<[HWPort01]> { 11040b57cec5SDimitry Andric let Latency = 2; 11050b57cec5SDimitry Andric let NumMicroOps = 2; 11065f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 11070b57cec5SDimitry Andric} 11080b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>; 11090b57cec5SDimitry Andric 11100b57cec5SDimitry Andricdef HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { 11110b57cec5SDimitry Andric let Latency = 2; 11120b57cec5SDimitry Andric let NumMicroOps = 2; 11135f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 11140b57cec5SDimitry Andric} 11150b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup30], (instrs LFENCE, 11160b57cec5SDimitry Andric MFENCE, 11170b57cec5SDimitry Andric WAIT, 11180b57cec5SDimitry Andric XGETBV)>; 11190b57cec5SDimitry Andric 11200b57cec5SDimitry Andricdef HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> { 11210b57cec5SDimitry Andric let Latency = 2; 11220b57cec5SDimitry Andric let NumMicroOps = 2; 11235f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 11240b57cec5SDimitry Andric} 11250b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>; 11260b57cec5SDimitry Andric 11270b57cec5SDimitry Andricdef HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> { 11280b57cec5SDimitry Andric let Latency = 2; 11290b57cec5SDimitry Andric let NumMicroOps = 2; 11305f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 11310b57cec5SDimitry Andric} 11320b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>; 11330b57cec5SDimitry Andric 11340b57cec5SDimitry Andricdef HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> { 11350b57cec5SDimitry Andric let Latency = 2; 11360b57cec5SDimitry Andric let NumMicroOps = 2; 11375f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 11380b57cec5SDimitry Andric} 11390b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>; 11400b57cec5SDimitry Andric 11410b57cec5SDimitry Andricdef HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> { 11420b57cec5SDimitry Andric let Latency = 7; 11430b57cec5SDimitry Andric let NumMicroOps = 3; 11445f757f3fSDimitry Andric let ReleaseAtCycles = [2,1]; 11450b57cec5SDimitry Andric} 11460eae32dcSDimitry Andricdef: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWrm, 11470eae32dcSDimitry Andric MMX_PACKSSWBrm, 11480eae32dcSDimitry Andric MMX_PACKUSWBrm)>; 11490b57cec5SDimitry Andric 11500b57cec5SDimitry Andricdef HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> { 11510b57cec5SDimitry Andric let Latency = 7; 11520b57cec5SDimitry Andric let NumMicroOps = 3; 11535f757f3fSDimitry Andric let ReleaseAtCycles = [1,2]; 11540b57cec5SDimitry Andric} 11550b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64, 11560b57cec5SDimitry Andric SCASB, SCASL, SCASQ, SCASW)>; 11570b57cec5SDimitry Andric 11580b57cec5SDimitry Andricdef HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> { 11590b57cec5SDimitry Andric let Latency = 7; 11600b57cec5SDimitry Andric let NumMicroOps = 3; 11615f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 11620b57cec5SDimitry Andric} 11630b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>; 11640b57cec5SDimitry Andric 11650b57cec5SDimitry Andricdef HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 11660b57cec5SDimitry Andric let Latency = 7; 11670b57cec5SDimitry Andric let NumMicroOps = 3; 11685f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 11690b57cec5SDimitry Andric} 1170349cc55cSDimitry Andricdef: InstRW<[HWWriteResGroup41], (instrs LRET64, RET32, RET64)>; 11710b57cec5SDimitry Andric 11720b57cec5SDimitry Andricdef HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { 11730b57cec5SDimitry Andric let Latency = 3; 11740b57cec5SDimitry Andric let NumMicroOps = 4; 11755f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1]; 11760b57cec5SDimitry Andric} 11770b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>; 11780b57cec5SDimitry Andric 11790b57cec5SDimitry Andricdef HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 11800b57cec5SDimitry Andric let Latency = 3; 11810b57cec5SDimitry Andric let NumMicroOps = 4; 11825f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1]; 11830b57cec5SDimitry Andric} 11840b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>; 11850b57cec5SDimitry Andric 11860b57cec5SDimitry Andricdef HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 11870b57cec5SDimitry Andric let Latency = 8; 11880b57cec5SDimitry Andric let NumMicroOps = 5; 11895f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,2]; 11900b57cec5SDimitry Andric} 11910b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)", 11920b57cec5SDimitry Andric "ROR(8|16|32|64)m(1|i)")>; 11930b57cec5SDimitry Andric 11940b57cec5SDimitry Andricdef HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> { 11950b57cec5SDimitry Andric let Latency = 2; 11960b57cec5SDimitry Andric let NumMicroOps = 2; 11975f757f3fSDimitry Andric let ReleaseAtCycles = [2]; 11980b57cec5SDimitry Andric} 11990b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 12000b57cec5SDimitry Andric ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 12010b57cec5SDimitry Andric 12020b57cec5SDimitry Andricdef HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 12030b57cec5SDimitry Andric let Latency = 8; 12040b57cec5SDimitry Andric let NumMicroOps = 5; 12055f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,2]; 12060b57cec5SDimitry Andric} 12070b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>; 12080b57cec5SDimitry Andric 12090b57cec5SDimitry Andricdef HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 12100b57cec5SDimitry Andric let Latency = 8; 12110b57cec5SDimitry Andric let NumMicroOps = 5; 12125f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1,1]; 12130b57cec5SDimitry Andric} 12140b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>; 12155ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup48], (instrs FARCALL64m)>; 12160b57cec5SDimitry Andric 12170b57cec5SDimitry Andricdef HWWriteResGroup50 : SchedWriteRes<[HWPort1]> { 12180b57cec5SDimitry Andric let Latency = 3; 12190b57cec5SDimitry Andric let NumMicroOps = 1; 12205f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 12210b57cec5SDimitry Andric} 1222bdd1243dSDimitry Andricdef: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr")>; 12230b57cec5SDimitry Andric 12240b57cec5SDimitry Andricdef HWWriteResGroup51 : SchedWriteRes<[HWPort5]> { 12250b57cec5SDimitry Andric let Latency = 3; 12260b57cec5SDimitry Andric let NumMicroOps = 1; 12275f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 12280b57cec5SDimitry Andric} 12290b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>; 12300b57cec5SDimitry Andric 12310b57cec5SDimitry Andricdef HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> { 12320b57cec5SDimitry Andric let Latency = 10; 12330b57cec5SDimitry Andric let NumMicroOps = 2; 12345f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 12350b57cec5SDimitry Andric} 12360b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 12370b57cec5SDimitry Andric "ILD_F(16|32|64)m")>; 12380b57cec5SDimitry Andric 12390b57cec5SDimitry Andricdef HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> { 12400b57cec5SDimitry Andric let Latency = 9; 12410b57cec5SDimitry Andric let NumMicroOps = 2; 12425f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 12430b57cec5SDimitry Andric} 12440b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm, 12450b57cec5SDimitry Andric VPMOVSXDQYrm, 12460b57cec5SDimitry Andric VPMOVSXWDYrm, 12470b57cec5SDimitry Andric VPMOVZXWDYrm)>; 12480b57cec5SDimitry Andric 12490b57cec5SDimitry Andricdef HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> { 12500b57cec5SDimitry Andric let Latency = 3; 12510b57cec5SDimitry Andric let NumMicroOps = 3; 12525f757f3fSDimitry Andric let ReleaseAtCycles = [2,1]; 12530b57cec5SDimitry Andric} 12540eae32dcSDimitry Andricdef: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWrr, 12550eae32dcSDimitry Andric MMX_PACKSSWBrr, 12560eae32dcSDimitry Andric MMX_PACKUSWBrr)>; 12570b57cec5SDimitry Andric 12580b57cec5SDimitry Andricdef HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> { 12590b57cec5SDimitry Andric let Latency = 3; 12600b57cec5SDimitry Andric let NumMicroOps = 3; 12615f757f3fSDimitry Andric let ReleaseAtCycles = [1,2]; 12620b57cec5SDimitry Andric} 12630b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup58], (instregex "CLD")>; 12640b57cec5SDimitry Andric 12650b57cec5SDimitry Andricdef HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { 126681ad6265SDimitry Andric let Latency = 2; 12670b57cec5SDimitry Andric let NumMicroOps = 3; 12685f757f3fSDimitry Andric let ReleaseAtCycles = [1,2]; 12690b57cec5SDimitry Andric} 127081ad6265SDimitry Andricdef: InstRW<[HWWriteResGroup59], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 127181ad6265SDimitry Andric RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 127281ad6265SDimitry Andric 127381ad6265SDimitry Andricdef HWWriteResGroup60 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { 127481ad6265SDimitry Andric let Latency = 5; 127581ad6265SDimitry Andric let NumMicroOps = 8; 12765f757f3fSDimitry Andric let ReleaseAtCycles = [2,4,2]; 127781ad6265SDimitry Andric} 127881ad6265SDimitry Andricdef: InstRW<[HWWriteResGroup60], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 127981ad6265SDimitry Andric 128081ad6265SDimitry Andricdef HWWriteResGroup60b : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { 128181ad6265SDimitry Andric let Latency = 6; 128281ad6265SDimitry Andric let NumMicroOps = 8; 12835f757f3fSDimitry Andric let ReleaseAtCycles = [2,4,2]; 128481ad6265SDimitry Andric} 128581ad6265SDimitry Andricdef: InstRW<[HWWriteResGroup60b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 12860b57cec5SDimitry Andric 12870b57cec5SDimitry Andricdef HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { 12880b57cec5SDimitry Andric let Latency = 4; 12890b57cec5SDimitry Andric let NumMicroOps = 3; 12905f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 12910b57cec5SDimitry Andric} 12920b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>; 12930b57cec5SDimitry Andric 12940b57cec5SDimitry Andricdef HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> { 12950b57cec5SDimitry Andric let Latency = 4; 12960b57cec5SDimitry Andric let NumMicroOps = 3; 12975f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 12980b57cec5SDimitry Andric} 12990b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m", 13000b57cec5SDimitry Andric "IST_F(16|32)m")>; 13010b57cec5SDimitry Andric 13020b57cec5SDimitry Andricdef HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { 13030b57cec5SDimitry Andric let Latency = 9; 13040b57cec5SDimitry Andric let NumMicroOps = 5; 13055f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,2]; 13060b57cec5SDimitry Andric} 13070b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)", 13080b57cec5SDimitry Andric "RCR(8|16|32|64)m(1|i)")>; 13090b57cec5SDimitry Andric 13100b57cec5SDimitry Andricdef HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 13110b57cec5SDimitry Andric let Latency = 9; 13120b57cec5SDimitry Andric let NumMicroOps = 6; 13135f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,3]; 13140b57cec5SDimitry Andric} 13150b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>; 13160b57cec5SDimitry Andric 13170b57cec5SDimitry Andricdef HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> { 13180b57cec5SDimitry Andric let Latency = 9; 13190b57cec5SDimitry Andric let NumMicroOps = 6; 13205f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,2,1]; 13210b57cec5SDimitry Andric} 13220b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL", 13230b57cec5SDimitry Andric "ROR(8|16|32|64)mCL", 13240b57cec5SDimitry Andric "SAR(8|16|32|64)mCL", 13250b57cec5SDimitry Andric "SHL(8|16|32|64)mCL", 13260b57cec5SDimitry Andric "SHR(8|16|32|64)mCL")>; 13270b57cec5SDimitry Andricdef: SchedAlias<WriteADCRMW, HWWriteResGroup69>; 13280b57cec5SDimitry Andric 13290b57cec5SDimitry Andricdef HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> { 13300b57cec5SDimitry Andric let Latency = 4; 13310b57cec5SDimitry Andric let NumMicroOps = 2; 13325f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 13330b57cec5SDimitry Andric} 13340b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>; 13350b57cec5SDimitry Andric 13360b57cec5SDimitry Andricdef HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> { 13370b57cec5SDimitry Andric let Latency = 4; 13380b57cec5SDimitry Andric let NumMicroOps = 2; 13395f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 13400b57cec5SDimitry Andric} 1341bdd1243dSDimitry Andricdef: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPS2PIrr, 13420eae32dcSDimitry Andric MMX_CVTTPS2PIrr)>; 13430b57cec5SDimitry Andric 13440b57cec5SDimitry Andricdef HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> { 13450b57cec5SDimitry Andric let Latency = 11; 13460b57cec5SDimitry Andric let NumMicroOps = 3; 13475f757f3fSDimitry Andric let ReleaseAtCycles = [2,1]; 13480b57cec5SDimitry Andric} 13490b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>; 13500b57cec5SDimitry Andric 13510b57cec5SDimitry Andricdef HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 13520b57cec5SDimitry Andric let Latency = 9; 13530b57cec5SDimitry Andric let NumMicroOps = 3; 13545f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 13550b57cec5SDimitry Andric} 1356bdd1243dSDimitry Andricdef: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDrm)>; 13570b57cec5SDimitry Andric 13580b57cec5SDimitry Andricdef HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { 13590b57cec5SDimitry Andric let Latency = 9; 13600b57cec5SDimitry Andric let NumMicroOps = 3; 13615f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 13620b57cec5SDimitry Andric} 13630b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>; 13640b57cec5SDimitry Andric 13650b57cec5SDimitry Andricdef HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> { 13660b57cec5SDimitry Andric let Latency = 4; 13670b57cec5SDimitry Andric let NumMicroOps = 4; 13685f757f3fSDimitry Andric let ReleaseAtCycles = [4]; 13690b57cec5SDimitry Andric} 13700b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>; 13710b57cec5SDimitry Andric 13720b57cec5SDimitry Andricdef HWWriteResGroup82 : SchedWriteRes<[]> { 13730b57cec5SDimitry Andric let Latency = 0; 13740b57cec5SDimitry Andric let NumMicroOps = 4; 13755f757f3fSDimitry Andric let ReleaseAtCycles = []; 13760b57cec5SDimitry Andric} 13770b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>; 13780b57cec5SDimitry Andric 13790b57cec5SDimitry Andricdef HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { 13800b57cec5SDimitry Andric let Latency = 4; 13810b57cec5SDimitry Andric let NumMicroOps = 4; 13825f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,2]; 13830b57cec5SDimitry Andric} 13840b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>; 13850b57cec5SDimitry Andric 13860b57cec5SDimitry Andricdef HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> { 13870b57cec5SDimitry Andric let Latency = 9; 13880b57cec5SDimitry Andric let NumMicroOps = 5; 13895f757f3fSDimitry Andric let ReleaseAtCycles = [1,2,1,1]; 13900b57cec5SDimitry Andric} 13910b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm", 13920b57cec5SDimitry Andric "LSL(16|32|64)rm")>; 13930b57cec5SDimitry Andric 13940b57cec5SDimitry Andricdef HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 13950b57cec5SDimitry Andric let Latency = 5; 13960b57cec5SDimitry Andric let NumMicroOps = 6; 13975f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,4]; 13980b57cec5SDimitry Andric} 13990b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>; 14000b57cec5SDimitry Andric 14010b57cec5SDimitry Andricdef HWWriteResGroup89 : SchedWriteRes<[HWPort0]> { 14020b57cec5SDimitry Andric let Latency = 5; 14030b57cec5SDimitry Andric let NumMicroOps = 1; 14045f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 14050b57cec5SDimitry Andric} 14060b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 14070b57cec5SDimitry Andric 14080b57cec5SDimitry Andricdef HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> { 14090b57cec5SDimitry Andric let Latency = 11; 14100b57cec5SDimitry Andric let NumMicroOps = 2; 14115f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 14120b57cec5SDimitry Andric} 14130b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>; 14140b57cec5SDimitry Andric 14150b57cec5SDimitry Andricdef HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> { 14160b57cec5SDimitry Andric let Latency = 12; 14170b57cec5SDimitry Andric let NumMicroOps = 2; 14185f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 14190b57cec5SDimitry Andric} 14200b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>; 14210b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>; 14220b57cec5SDimitry Andric 14230b57cec5SDimitry Andricdef HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> { 14240b57cec5SDimitry Andric let Latency = 5; 14250b57cec5SDimitry Andric let NumMicroOps = 3; 14265f757f3fSDimitry Andric let ReleaseAtCycles = [1,2]; 14270b57cec5SDimitry Andric} 14280b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>; 14290b57cec5SDimitry Andric 14300b57cec5SDimitry Andricdef HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> { 14310b57cec5SDimitry Andric let Latency = 5; 14320b57cec5SDimitry Andric let NumMicroOps = 3; 14335f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 14340b57cec5SDimitry Andric} 14350b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>; 14360b57cec5SDimitry Andric 14370b57cec5SDimitry Andricdef HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { 14380b57cec5SDimitry Andric let Latency = 5; 14390b57cec5SDimitry Andric let NumMicroOps = 5; 14405f757f3fSDimitry Andric let ReleaseAtCycles = [1,4]; 14410b57cec5SDimitry Andric} 14420b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup99], (instrs PAUSE)>; 14430b57cec5SDimitry Andric 14440b57cec5SDimitry Andricdef HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> { 14450b57cec5SDimitry Andric let Latency = 5; 14460b57cec5SDimitry Andric let NumMicroOps = 5; 14475f757f3fSDimitry Andric let ReleaseAtCycles = [1,4]; 14480b57cec5SDimitry Andric} 14490b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup100], (instrs XSETBV)>; 14500b57cec5SDimitry Andric 14510b57cec5SDimitry Andricdef HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { 14520b57cec5SDimitry Andric let Latency = 13; 14530b57cec5SDimitry Andric let NumMicroOps = 3; 14545f757f3fSDimitry Andric let ReleaseAtCycles = [2,1]; 14550b57cec5SDimitry Andric} 14560b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 14570b57cec5SDimitry Andric 14580b57cec5SDimitry Andricdef HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> { 14590b57cec5SDimitry Andric let Latency = 6; 14600b57cec5SDimitry Andric let NumMicroOps = 4; 14615f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1]; 14620b57cec5SDimitry Andric} 14630b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>; 14640b57cec5SDimitry Andric 14650b57cec5SDimitry Andricdef HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> { 14660b57cec5SDimitry Andric let Latency = 6; 14670b57cec5SDimitry Andric let NumMicroOps = 6; 14685f757f3fSDimitry Andric let ReleaseAtCycles = [1,5]; 14690b57cec5SDimitry Andric} 14700b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup108], (instrs STD)>; 14710b57cec5SDimitry Andric 14720b57cec5SDimitry Andricdef HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> { 14730b57cec5SDimitry Andric let Latency = 7; 14740b57cec5SDimitry Andric let NumMicroOps = 7; 14755f757f3fSDimitry Andric let ReleaseAtCycles = [2,2,1,2]; 14760b57cec5SDimitry Andric} 14770b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup114], (instrs LOOP)>; 14780b57cec5SDimitry Andric 14790b57cec5SDimitry Andricdef HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 14800b57cec5SDimitry Andric let Latency = 15; 14810b57cec5SDimitry Andric let NumMicroOps = 3; 14825f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 14830b57cec5SDimitry Andric} 14840b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>; 14850b57cec5SDimitry Andric 14860b57cec5SDimitry Andricdef HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 14870b57cec5SDimitry Andric let Latency = 16; 14880b57cec5SDimitry Andric let NumMicroOps = 10; 14895f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,4,1,2]; 14900b57cec5SDimitry Andric} 14910b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>; 14920b57cec5SDimitry Andric 14930b57cec5SDimitry Andricdef HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { 14940b57cec5SDimitry Andric let Latency = 11; 14950b57cec5SDimitry Andric let NumMicroOps = 7; 14965f757f3fSDimitry Andric let ReleaseAtCycles = [2,2,3]; 14970b57cec5SDimitry Andric} 14980b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL", 14990b57cec5SDimitry Andric "RCR(16|32|64)rCL")>; 15000b57cec5SDimitry Andric 15010b57cec5SDimitry Andricdef HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 15020b57cec5SDimitry Andric let Latency = 11; 15030b57cec5SDimitry Andric let NumMicroOps = 9; 15045f757f3fSDimitry Andric let ReleaseAtCycles = [1,4,1,3]; 15050b57cec5SDimitry Andric} 15060b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>; 15070b57cec5SDimitry Andric 15080b57cec5SDimitry Andricdef HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> { 15090b57cec5SDimitry Andric let Latency = 11; 15100b57cec5SDimitry Andric let NumMicroOps = 11; 15115f757f3fSDimitry Andric let ReleaseAtCycles = [2,9]; 15120b57cec5SDimitry Andric} 15130b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>; 15140b57cec5SDimitry Andric 15150b57cec5SDimitry Andricdef HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 15160b57cec5SDimitry Andric let Latency = 17; 15170b57cec5SDimitry Andric let NumMicroOps = 14; 15185f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,4,2,5]; 15190b57cec5SDimitry Andric} 15200b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>; 15210b57cec5SDimitry Andric 15220b57cec5SDimitry Andricdef HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 15230b57cec5SDimitry Andric let Latency = 19; 15240b57cec5SDimitry Andric let NumMicroOps = 11; 15255f757f3fSDimitry Andric let ReleaseAtCycles = [2,1,1,3,1,3]; 15260b57cec5SDimitry Andric} 15270b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>; 15280b57cec5SDimitry Andric 15290b57cec5SDimitry Andricdef HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 15300b57cec5SDimitry Andric let Latency = 14; 15310b57cec5SDimitry Andric let NumMicroOps = 10; 15325f757f3fSDimitry Andric let ReleaseAtCycles = [2,3,1,4]; 15330b57cec5SDimitry Andric} 15340b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>; 15350b57cec5SDimitry Andric 15360b57cec5SDimitry Andricdef HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> { 15370b57cec5SDimitry Andric let Latency = 19; 15380b57cec5SDimitry Andric let NumMicroOps = 15; 15395f757f3fSDimitry Andric let ReleaseAtCycles = [1,14]; 15400b57cec5SDimitry Andric} 15410b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup143], (instrs POPF16)>; 15420b57cec5SDimitry Andric 15430b57cec5SDimitry Andricdef HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 15440b57cec5SDimitry Andric let Latency = 21; 15450b57cec5SDimitry Andric let NumMicroOps = 8; 15465f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1,1,1,2]; 15470b57cec5SDimitry Andric} 15480b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>; 15490b57cec5SDimitry Andric 15500b57cec5SDimitry Andricdef HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> { 15510b57cec5SDimitry Andric let Latency = 8; 15520b57cec5SDimitry Andric let NumMicroOps = 20; 15535f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 15540b57cec5SDimitry Andric} 15550b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>; 15560b57cec5SDimitry Andric 15570b57cec5SDimitry Andricdef HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> { 15580b57cec5SDimitry Andric let Latency = 22; 15590b57cec5SDimitry Andric let NumMicroOps = 19; 15605f757f3fSDimitry Andric let ReleaseAtCycles = [2,1,4,1,1,4,6]; 15610b57cec5SDimitry Andric} 15620b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>; 15630b57cec5SDimitry Andric 15640b57cec5SDimitry Andricdef HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { 15650b57cec5SDimitry Andric let Latency = 17; 15660b57cec5SDimitry Andric let NumMicroOps = 15; 15675f757f3fSDimitry Andric let ReleaseAtCycles = [2,1,2,4,2,4]; 15680b57cec5SDimitry Andric} 15690b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup147], (instrs XCH_F)>; 15700b57cec5SDimitry Andric 15710b57cec5SDimitry Andricdef HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> { 15720b57cec5SDimitry Andric let Latency = 18; 15730b57cec5SDimitry Andric let NumMicroOps = 8; 15745f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,5]; 15750b57cec5SDimitry Andric} 15760b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>; 15770b57cec5SDimitry Andric 15780b57cec5SDimitry Andricdef HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 15790b57cec5SDimitry Andric let Latency = 23; 15800b57cec5SDimitry Andric let NumMicroOps = 19; 15815f757f3fSDimitry Andric let ReleaseAtCycles = [3,1,15]; 15820b57cec5SDimitry Andric} 15830b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>; 15840b57cec5SDimitry Andric 15850b57cec5SDimitry Andricdef HWWriteResGroup154 : SchedWriteRes<[HWPort0]> { 15860b57cec5SDimitry Andric let Latency = 20; 15870b57cec5SDimitry Andric let NumMicroOps = 1; 15885f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 15890b57cec5SDimitry Andric} 15900b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 15910b57cec5SDimitry Andric 15920b57cec5SDimitry Andricdef HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> { 15930b57cec5SDimitry Andric let Latency = 27; 15940b57cec5SDimitry Andric let NumMicroOps = 2; 15955f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 15960b57cec5SDimitry Andric} 15970b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>; 15980b57cec5SDimitry Andric 15990b57cec5SDimitry Andricdef HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> { 16000b57cec5SDimitry Andric let Latency = 20; 16010b57cec5SDimitry Andric let NumMicroOps = 10; 16025f757f3fSDimitry Andric let ReleaseAtCycles = [1,2,7]; 16030b57cec5SDimitry Andric} 16040b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>; 16050b57cec5SDimitry Andric 16060b57cec5SDimitry Andricdef HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 16070b57cec5SDimitry Andric let Latency = 30; 16080b57cec5SDimitry Andric let NumMicroOps = 3; 16095f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 16100b57cec5SDimitry Andric} 16110b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>; 16120b57cec5SDimitry Andric 16130b57cec5SDimitry Andricdef HWWriteResGroup162 : SchedWriteRes<[HWPort0]> { 16140b57cec5SDimitry Andric let Latency = 24; 16150b57cec5SDimitry Andric let NumMicroOps = 1; 16165f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 16170b57cec5SDimitry Andric} 16180b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 16190b57cec5SDimitry Andric 16200b57cec5SDimitry Andricdef HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> { 16210b57cec5SDimitry Andric let Latency = 31; 16220b57cec5SDimitry Andric let NumMicroOps = 2; 16235f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 16240b57cec5SDimitry Andric} 16250b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>; 16260b57cec5SDimitry Andric 16270b57cec5SDimitry Andricdef HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 16280b57cec5SDimitry Andric let Latency = 30; 16290b57cec5SDimitry Andric let NumMicroOps = 27; 16305f757f3fSDimitry Andric let ReleaseAtCycles = [1,5,1,1,19]; 16310b57cec5SDimitry Andric} 16320b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>; 16330b57cec5SDimitry Andric 16340b57cec5SDimitry Andricdef HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 16350b57cec5SDimitry Andric let Latency = 31; 16360b57cec5SDimitry Andric let NumMicroOps = 28; 16375f757f3fSDimitry Andric let ReleaseAtCycles = [1,6,1,1,19]; 16380b57cec5SDimitry Andric} 16390b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup165], (instrs XSAVE)>; 16400b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 16410b57cec5SDimitry Andric 16420b57cec5SDimitry Andricdef HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 16430b57cec5SDimitry Andric let Latency = 34; 16440b57cec5SDimitry Andric let NumMicroOps = 3; 16455f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1]; 16460b57cec5SDimitry Andric} 16470b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>; 16480b57cec5SDimitry Andric 16490b57cec5SDimitry Andricdef HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> { 16500b57cec5SDimitry Andric let Latency = 35; 16510b57cec5SDimitry Andric let NumMicroOps = 23; 16525f757f3fSDimitry Andric let ReleaseAtCycles = [1,5,3,4,10]; 16530b57cec5SDimitry Andric} 16540b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri", 16550b57cec5SDimitry Andric "IN(8|16|32)rr")>; 16560b57cec5SDimitry Andric 16570b57cec5SDimitry Andricdef HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 16580b57cec5SDimitry Andric let Latency = 36; 16590b57cec5SDimitry Andric let NumMicroOps = 23; 16605f757f3fSDimitry Andric let ReleaseAtCycles = [1,5,2,1,4,10]; 16610b57cec5SDimitry Andric} 16620b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir", 16630b57cec5SDimitry Andric "OUT(8|16|32)rr")>; 16640b57cec5SDimitry Andric 16650b57cec5SDimitry Andricdef HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> { 16660b57cec5SDimitry Andric let Latency = 41; 16670b57cec5SDimitry Andric let NumMicroOps = 18; 16685f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,2,3,1,1,1,8]; 16690b57cec5SDimitry Andric} 16700b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>; 16710b57cec5SDimitry Andric 16720b57cec5SDimitry Andricdef HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> { 16730b57cec5SDimitry Andric let Latency = 42; 16740b57cec5SDimitry Andric let NumMicroOps = 22; 16755f757f3fSDimitry Andric let ReleaseAtCycles = [2,20]; 16760b57cec5SDimitry Andric} 16770b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>; 16780b57cec5SDimitry Andric 16790b57cec5SDimitry Andricdef HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> { 16800b57cec5SDimitry Andric let Latency = 61; 16810b57cec5SDimitry Andric let NumMicroOps = 64; 16825f757f3fSDimitry Andric let ReleaseAtCycles = [2,2,8,1,10,2,39]; 16830b57cec5SDimitry Andric} 16840b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>; 16850b57cec5SDimitry Andric 16860b57cec5SDimitry Andricdef HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 16870b57cec5SDimitry Andric let Latency = 64; 16880b57cec5SDimitry Andric let NumMicroOps = 88; 16895f757f3fSDimitry Andric let ReleaseAtCycles = [4,4,31,1,2,1,45]; 16900b57cec5SDimitry Andric} 16910b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>; 16920b57cec5SDimitry Andric 16930b57cec5SDimitry Andricdef HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 16940b57cec5SDimitry Andric let Latency = 64; 16950b57cec5SDimitry Andric let NumMicroOps = 90; 16965f757f3fSDimitry Andric let ReleaseAtCycles = [4,2,33,1,2,1,47]; 16970b57cec5SDimitry Andric} 16980b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>; 16990b57cec5SDimitry Andric 17000b57cec5SDimitry Andricdef HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> { 17010b57cec5SDimitry Andric let Latency = 75; 17020b57cec5SDimitry Andric let NumMicroOps = 15; 17035f757f3fSDimitry Andric let ReleaseAtCycles = [6,3,6]; 17040b57cec5SDimitry Andric} 17050b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup180], (instrs FNINIT)>; 17060b57cec5SDimitry Andric 17070b57cec5SDimitry Andricdef HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> { 17080b57cec5SDimitry Andric let Latency = 115; 17090b57cec5SDimitry Andric let NumMicroOps = 100; 17105f757f3fSDimitry Andric let ReleaseAtCycles = [9,9,11,8,1,11,21,30]; 17110b57cec5SDimitry Andric} 17120b57cec5SDimitry Andricdef: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>; 17130b57cec5SDimitry Andric 17145ffd83dbSDimitry Andricdef HWWriteResGroup184 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 17155ffd83dbSDimitry Andric let Latency = 14; 17160b57cec5SDimitry Andric let NumMicroOps = 12; 17175f757f3fSDimitry Andric let ReleaseAtCycles = [2,2,2,1,3,2]; 17180b57cec5SDimitry Andric} 17195ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, VPGATHERDQrm)>; 17200b57cec5SDimitry Andric 17210b57cec5SDimitry Andricdef HWWriteResGroup185 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 17225ffd83dbSDimitry Andric let Latency = 17; 17230b57cec5SDimitry Andric let NumMicroOps = 20; 17245f757f3fSDimitry Andric let ReleaseAtCycles = [3,3,4,1,5,4]; 17250b57cec5SDimitry Andric} 17265ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup185], (instrs VGATHERDPDYrm, VPGATHERDQYrm)>; 17270b57cec5SDimitry Andric 17285ffd83dbSDimitry Andricdef HWWriteResGroup186 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 17295ffd83dbSDimitry Andric let Latency = 16; 17305ffd83dbSDimitry Andric let NumMicroOps = 20; 17315f757f3fSDimitry Andric let ReleaseAtCycles = [3,3,4,1,5,4]; 17325ffd83dbSDimitry Andric} 17335ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup186], (instrs VGATHERDPSrm, VPGATHERDDrm)>; 17345ffd83dbSDimitry Andric 17355ffd83dbSDimitry Andricdef HWWriteResGroup187 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 17365ffd83dbSDimitry Andric let Latency = 22; 17370b57cec5SDimitry Andric let NumMicroOps = 34; 17385f757f3fSDimitry Andric let ReleaseAtCycles = [5,3,8,1,9,8]; 17390b57cec5SDimitry Andric} 17405ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup187], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 17410b57cec5SDimitry Andric 17425ffd83dbSDimitry Andricdef HWWriteResGroup188 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 17435ffd83dbSDimitry Andric let Latency = 15; 17440b57cec5SDimitry Andric let NumMicroOps = 14; 17455f757f3fSDimitry Andric let ReleaseAtCycles = [3,3,2,1,3,2]; 17460b57cec5SDimitry Andric} 17475ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup188], (instrs VGATHERQPDrm, VPGATHERQQrm)>; 17480b57cec5SDimitry Andric 17495ffd83dbSDimitry Andricdef HWWriteResGroup189 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 17505ffd83dbSDimitry Andric let Latency = 17; 17515ffd83dbSDimitry Andric let NumMicroOps = 22; 17525f757f3fSDimitry Andric let ReleaseAtCycles = [5,3,4,1,5,4]; 17535ffd83dbSDimitry Andric} 17545ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup189], (instrs VGATHERQPDYrm, VPGATHERQQYrm, 17555ffd83dbSDimitry Andric VGATHERQPSYrm, VPGATHERQDYrm)>; 17565ffd83dbSDimitry Andric 17575ffd83dbSDimitry Andricdef HWWriteResGroup190 : SchedWriteRes<[HWPort0,HWPort5,HWPort06,HWPort15,HWPort015,HWPort23]> { 17585ffd83dbSDimitry Andric let Latency = 16; 17590b57cec5SDimitry Andric let NumMicroOps = 15; 17605f757f3fSDimitry Andric let ReleaseAtCycles = [3,3,2,1,4,2]; 17610b57cec5SDimitry Andric} 17625ffd83dbSDimitry Andricdef: InstRW<[HWWriteResGroup190], (instrs VGATHERQPSrm, VPGATHERQDrm)>; 17630b57cec5SDimitry Andric 17640b57cec5SDimitry Andricdef: InstRW<[WriteZero], (instrs CLC)>; 17650b57cec5SDimitry Andric 17660b57cec5SDimitry Andric 17675ffd83dbSDimitry Andric// Instruction variants handled by the renamer. These might not need execution 17680b57cec5SDimitry Andric// ports in certain conditions. 17690b57cec5SDimitry Andric// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 17700b57cec5SDimitry Andric// section "Haswell and Broadwell Pipeline" > "Register allocation and 17710b57cec5SDimitry Andric// renaming". 17720b57cec5SDimitry Andric// These can be investigated with llvm-exegesis, e.g. 17730b57cec5SDimitry Andric// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 17740b57cec5SDimitry Andric// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 17750b57cec5SDimitry Andric 17760b57cec5SDimitry Andricdef HWWriteZeroLatency : SchedWriteRes<[]> { 17770b57cec5SDimitry Andric let Latency = 0; 17780b57cec5SDimitry Andric} 17790b57cec5SDimitry Andric 17800b57cec5SDimitry Andricdef HWWriteZeroIdiom : SchedWriteVariant<[ 17810b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 17820b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteALU]> 17830b57cec5SDimitry Andric]>; 17840b57cec5SDimitry Andricdef : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 17850b57cec5SDimitry Andric XOR32rr, XOR64rr)>; 17860b57cec5SDimitry Andric 17870b57cec5SDimitry Andricdef HWWriteFZeroIdiom : SchedWriteVariant<[ 17880b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 17890b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteFLogic]> 17900b57cec5SDimitry Andric]>; 17910b57cec5SDimitry Andricdef : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 17920b57cec5SDimitry Andric VXORPDrr)>; 17930b57cec5SDimitry Andric 17940b57cec5SDimitry Andricdef HWWriteFZeroIdiomY : SchedWriteVariant<[ 17950b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 17960b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteFLogicY]> 17970b57cec5SDimitry Andric]>; 17980b57cec5SDimitry Andricdef : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 17990b57cec5SDimitry Andric 18000b57cec5SDimitry Andricdef HWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 18010b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 18020b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteVecLogicX]> 18030b57cec5SDimitry Andric]>; 18040b57cec5SDimitry Andricdef : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 18050b57cec5SDimitry Andric 18060b57cec5SDimitry Andricdef HWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 18070b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 18080b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteVecLogicY]> 18090b57cec5SDimitry Andric]>; 18100b57cec5SDimitry Andricdef : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 18110b57cec5SDimitry Andric 18120b57cec5SDimitry Andricdef HWWriteVZeroIdiomALUX : SchedWriteVariant<[ 18130b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 18140b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteVecALUX]> 18150b57cec5SDimitry Andric]>; 18160b57cec5SDimitry Andricdef : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 18170b57cec5SDimitry Andric PSUBDrr, VPSUBDrr, 18180b57cec5SDimitry Andric PSUBQrr, VPSUBQrr, 18190b57cec5SDimitry Andric PSUBWrr, VPSUBWrr, 18200b57cec5SDimitry Andric PCMPGTBrr, VPCMPGTBrr, 18210b57cec5SDimitry Andric PCMPGTDrr, VPCMPGTDrr, 18220b57cec5SDimitry Andric PCMPGTWrr, VPCMPGTWrr)>; 18230b57cec5SDimitry Andric 18240b57cec5SDimitry Andricdef HWWriteVZeroIdiomALUY : SchedWriteVariant<[ 18250b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 18260b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteVecALUY]> 18270b57cec5SDimitry Andric]>; 18280b57cec5SDimitry Andricdef : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 18290b57cec5SDimitry Andric VPSUBDYrr, 18300b57cec5SDimitry Andric VPSUBQYrr, 18310b57cec5SDimitry Andric VPSUBWYrr, 18320b57cec5SDimitry Andric VPCMPGTBYrr, 18330b57cec5SDimitry Andric VPCMPGTDYrr, 18340b57cec5SDimitry Andric VPCMPGTWYrr)>; 18350b57cec5SDimitry Andric 18360b57cec5SDimitry Andricdef HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> { 18370b57cec5SDimitry Andric let Latency = 5; 18380b57cec5SDimitry Andric let NumMicroOps = 1; 18395f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 18400b57cec5SDimitry Andric} 18410b57cec5SDimitry Andric 18420b57cec5SDimitry Andricdef HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 18430b57cec5SDimitry Andric SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 18440b57cec5SDimitry Andric SchedVar<NoSchedPred, [HWWritePCMPGTQ]> 18450b57cec5SDimitry Andric]>; 18460b57cec5SDimitry Andricdef : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 18470b57cec5SDimitry Andric VPCMPGTQYrr)>; 18480b57cec5SDimitry Andric 18490b57cec5SDimitry Andric 18500b57cec5SDimitry Andric// The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require 18510b57cec5SDimitry Andric// a single uop. It does not apply to the GR8 encoding. And only applies to the 18520b57cec5SDimitry Andric// 8-bit immediate since using larger immediate for 0 would be silly. 18530b57cec5SDimitry Andric// Unfortunately, this optimization does not apply to the AX/EAX/RAX short 18540b57cec5SDimitry Andric// encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since 18550b57cec5SDimitry Andric// we schedule before that point. 18560b57cec5SDimitry Andric// TODO: Should we disable using the short encodings on these CPUs? 18570b57cec5SDimitry Andricdef HWFastADC0 : MCSchedPredicate< 18580b57cec5SDimitry Andric CheckAll<[ 18590b57cec5SDimitry Andric CheckImmOperand<2, 0>, // Second MCOperand is Imm and has value 0. 18600b57cec5SDimitry Andric CheckNot<CheckRegOperand<1, AX>>, // First MCOperand is not register AX 18610b57cec5SDimitry Andric CheckNot<CheckRegOperand<1, EAX>>, // First MCOperand is not register EAX 18620b57cec5SDimitry Andric CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX 18630b57cec5SDimitry Andric ]> 18640b57cec5SDimitry Andric>; 18650b57cec5SDimitry Andric 18660b57cec5SDimitry Andricdef HWWriteADC0 : SchedWriteRes<[HWPort06]> { 18670b57cec5SDimitry Andric let Latency = 1; 18680b57cec5SDimitry Andric let NumMicroOps = 1; 18695f757f3fSDimitry Andric let ReleaseAtCycles = [1]; 18700b57cec5SDimitry Andric} 18710b57cec5SDimitry Andric 18720b57cec5SDimitry Andricdef HWWriteADC : SchedWriteVariant<[ 18730b57cec5SDimitry Andric SchedVar<HWFastADC0, [HWWriteADC0]>, 18740b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteADC]> 18750b57cec5SDimitry Andric]>; 18760b57cec5SDimitry Andric 18770b57cec5SDimitry Andricdef : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8, 18780b57cec5SDimitry Andric SBB16ri8, SBB32ri8, SBB64ri8)>; 18790b57cec5SDimitry Andric 18800b57cec5SDimitry Andric// CMOVs that use both Z and C flag require an extra uop. 18810b57cec5SDimitry Andricdef HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> { 18820b57cec5SDimitry Andric let Latency = 3; 18835f757f3fSDimitry Andric let ReleaseAtCycles = [1,2]; 18840b57cec5SDimitry Andric let NumMicroOps = 3; 18850b57cec5SDimitry Andric} 18860b57cec5SDimitry Andric 18870b57cec5SDimitry Andricdef HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> { 18880b57cec5SDimitry Andric let Latency = 8; 18895f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,2]; 18900b57cec5SDimitry Andric let NumMicroOps = 4; 18910b57cec5SDimitry Andric} 18920b57cec5SDimitry Andric 18930b57cec5SDimitry Andricdef HWCMOVA_CMOVBErr : SchedWriteVariant<[ 18940b57cec5SDimitry Andric SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>, 18950b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteCMOV]> 18960b57cec5SDimitry Andric]>; 18970b57cec5SDimitry Andric 18980b57cec5SDimitry Andricdef HWCMOVA_CMOVBErm : SchedWriteVariant<[ 18990b57cec5SDimitry Andric SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>, 19000b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteCMOV.Folded]> 19010b57cec5SDimitry Andric]>; 19020b57cec5SDimitry Andric 19030b57cec5SDimitry Andricdef : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 19040b57cec5SDimitry Andricdef : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 19050b57cec5SDimitry Andric 19060b57cec5SDimitry Andric// SETCCs that use both Z and C flag require an extra uop. 19070b57cec5SDimitry Andricdef HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> { 19080b57cec5SDimitry Andric let Latency = 2; 19095f757f3fSDimitry Andric let ReleaseAtCycles = [1,1]; 19100b57cec5SDimitry Andric let NumMicroOps = 2; 19110b57cec5SDimitry Andric} 19120b57cec5SDimitry Andric 19130b57cec5SDimitry Andricdef HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 19140b57cec5SDimitry Andric let Latency = 3; 19155f757f3fSDimitry Andric let ReleaseAtCycles = [1,1,1,1]; 19160b57cec5SDimitry Andric let NumMicroOps = 4; 19170b57cec5SDimitry Andric} 19180b57cec5SDimitry Andric 19190b57cec5SDimitry Andricdef HWSETA_SETBErr : SchedWriteVariant<[ 19200b57cec5SDimitry Andric SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>, 19210b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteSETCC]> 19220b57cec5SDimitry Andric]>; 19230b57cec5SDimitry Andric 19240b57cec5SDimitry Andricdef HWSETA_SETBErm : SchedWriteVariant<[ 19250b57cec5SDimitry Andric SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>, 19260b57cec5SDimitry Andric SchedVar<NoSchedPred, [WriteSETCCStore]> 19270b57cec5SDimitry Andric]>; 19280b57cec5SDimitry Andric 19290b57cec5SDimitry Andricdef : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>; 19300b57cec5SDimitry Andricdef : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>; 19310b57cec5SDimitry Andric 193204eeddc0SDimitry Andric/////////////////////////////////////////////////////////////////////////////// 193304eeddc0SDimitry Andric// Dependency breaking instructions. 193404eeddc0SDimitry Andric/////////////////////////////////////////////////////////////////////////////// 193504eeddc0SDimitry Andric 193604eeddc0SDimitry Andricdef : IsZeroIdiomFunction<[ 193704eeddc0SDimitry Andric // GPR Zero-idioms. 193804eeddc0SDimitry Andric DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 193904eeddc0SDimitry Andric 194004eeddc0SDimitry Andric // SSE Zero-idioms. 194104eeddc0SDimitry Andric DepBreakingClass<[ 194204eeddc0SDimitry Andric // fp variants. 194304eeddc0SDimitry Andric XORPSrr, XORPDrr, 194404eeddc0SDimitry Andric 194504eeddc0SDimitry Andric // int variants. 194604eeddc0SDimitry Andric PXORrr, 194704eeddc0SDimitry Andric PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 194804eeddc0SDimitry Andric PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 194904eeddc0SDimitry Andric ], ZeroIdiomPredicate>, 195004eeddc0SDimitry Andric 195104eeddc0SDimitry Andric // AVX Zero-idioms. 195204eeddc0SDimitry Andric DepBreakingClass<[ 195304eeddc0SDimitry Andric // xmm fp variants. 195404eeddc0SDimitry Andric VXORPSrr, VXORPDrr, 195504eeddc0SDimitry Andric 195604eeddc0SDimitry Andric // xmm int variants. 195704eeddc0SDimitry Andric VPXORrr, 195804eeddc0SDimitry Andric VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 195904eeddc0SDimitry Andric VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 196004eeddc0SDimitry Andric 196104eeddc0SDimitry Andric // ymm variants. 196204eeddc0SDimitry Andric VXORPSYrr, VXORPDYrr, VPXORYrr, 196304eeddc0SDimitry Andric VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 196404eeddc0SDimitry Andric VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr 196504eeddc0SDimitry Andric ], ZeroIdiomPredicate>, 196604eeddc0SDimitry Andric]>; 196704eeddc0SDimitry Andric 19680b57cec5SDimitry Andric} // SchedModel 1969