1//=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Haswell to support instruction 10// scheduling and other instruction cost heuristics. 11// 12// Note that we define some instructions here that are not supported by haswell, 13// but we still have to define them because KNL uses the HSW model. 14// They are currently tagged with a comment `Unsupported = 1`. 15// FIXME: Use Unsupported = 1 once KNL has its own model. 16// 17//===----------------------------------------------------------------------===// 18 19def HaswellModel : SchedMachineModel { 20 // All x86 instructions are modeled as a single micro-op, and HW can decode 4 21 // instructions per cycle. 22 let IssueWidth = 4; 23 let MicroOpBufferSize = 192; // Based on the reorder buffer. 24 let LoadLatency = 5; 25 let MispredictPenalty = 16; 26 27 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 28 let LoopMicroOpBufferSize = 50; 29 30 // This flag is set to allow the scheduler to assign a default model to 31 // unrecognized opcodes. 32 let CompleteModel = 0; 33} 34 35let SchedModel = HaswellModel in { 36 37// Haswell can issue micro-ops to 8 different ports in one cycle. 38 39// Ports 0, 1, 5, and 6 handle all computation. 40// Port 4 gets the data half of stores. Store data can be available later than 41// the store address, but since we don't model the latency of stores, we can 42// ignore that. 43// Ports 2 and 3 are identical. They handle loads and the address half of 44// stores. Port 7 can handle address calculations. 45def HWPort0 : ProcResource<1>; 46def HWPort1 : ProcResource<1>; 47def HWPort2 : ProcResource<1>; 48def HWPort3 : ProcResource<1>; 49def HWPort4 : ProcResource<1>; 50def HWPort5 : ProcResource<1>; 51def HWPort6 : ProcResource<1>; 52def HWPort7 : ProcResource<1>; 53 54// Many micro-ops are capable of issuing on multiple ports. 55def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>; 56def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>; 57def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>; 58def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>; 59def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>; 60def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>; 61def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; 62def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>; 63def HWPort56 : ProcResGroup<[HWPort5, HWPort6]>; 64def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; 65def HWPort056 : ProcResGroup<[HWPort0, HWPort5, HWPort6]>; 66def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; 67 68// 60 Entry Unified Scheduler 69def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4, 70 HWPort5, HWPort6, HWPort7]> { 71 let BufferSize=60; 72} 73 74// Integer division issued on port 0. 75def HWDivider : ProcResource<1>; 76// FP division and sqrt on port 0. 77def HWFPDivider : ProcResource<1>; 78 79// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 80// cycles after the memory operand. 81def : ReadAdvance<ReadAfterLd, 5>; 82 83// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 84// until 5/6/7 cycles after the memory operand. 85def : ReadAdvance<ReadAfterVecLd, 5>; 86def : ReadAdvance<ReadAfterVecXLd, 6>; 87def : ReadAdvance<ReadAfterVecYLd, 7>; 88 89def : ReadAdvance<ReadInt2Fpu, 0>; 90 91// Many SchedWrites are defined in pairs with and without a folded load. 92// Instructions with folded loads are usually micro-fused, so they only appear 93// as two micro-ops when queued in the reservation station. 94// This multiclass defines the resource usage for variants with and without 95// folded loads. 96multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW, 97 list<ProcResourceKind> ExePorts, 98 int Lat, list<int> Res = [1], int UOps = 1, 99 int LoadLat = 5> { 100 // Register variant is using a single cycle on ExePort. 101 def : WriteRes<SchedRW, ExePorts> { 102 let Latency = Lat; 103 let ResourceCycles = Res; 104 let NumMicroOps = UOps; 105 } 106 107 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 108 // the latency (default = 5). 109 def : WriteRes<SchedRW.Folded, !listconcat([HWPort23], ExePorts)> { 110 let Latency = !add(Lat, LoadLat); 111 let ResourceCycles = !listconcat([1], Res); 112 let NumMicroOps = !add(UOps, 1); 113 } 114} 115 116// A folded store needs a cycle on port 4 for the store data, and an extra port 117// 2/3/7 cycle to recompute the address. 118def : WriteRes<WriteRMW, [HWPort237,HWPort4]>; 119 120// Store_addr on 237. 121// Store_data on 4. 122defm : X86WriteRes<WriteStore, [HWPort237, HWPort4], 1, [1,1], 1>; 123defm : X86WriteRes<WriteStoreNT, [HWPort237, HWPort4], 1, [1,1], 2>; 124defm : X86WriteRes<WriteLoad, [HWPort23], 5, [1], 1>; 125defm : X86WriteRes<WriteMove, [HWPort0156], 1, [1], 1>; 126def : WriteRes<WriteZero, []>; 127 128// Arithmetic. 129defm : HWWriteResPair<WriteALU, [HWPort0156], 1>; 130defm : HWWriteResPair<WriteADC, [HWPort06, HWPort0156], 2, [1,1], 2>; 131 132// Integer multiplication. 133defm : HWWriteResPair<WriteIMul8, [HWPort1], 3>; 134defm : HWWriteResPair<WriteIMul16, [HWPort1,HWPort06,HWPort0156], 4, [1,1,2], 4>; 135defm : X86WriteRes<WriteIMul16Imm, [HWPort1,HWPort0156], 4, [1,1], 2>; 136defm : X86WriteRes<WriteIMul16ImmLd, [HWPort1,HWPort0156,HWPort23], 8, [1,1,1], 3>; 137defm : HWWriteResPair<WriteIMul16Reg, [HWPort1], 3>; 138defm : HWWriteResPair<WriteIMul32, [HWPort1,HWPort06,HWPort0156], 4, [1,1,1], 3>; 139defm : HWWriteResPair<WriteIMul32Imm, [HWPort1], 3>; 140defm : HWWriteResPair<WriteIMul32Reg, [HWPort1], 3>; 141defm : HWWriteResPair<WriteIMul64, [HWPort1,HWPort6], 4, [1,1], 2>; 142defm : HWWriteResPair<WriteIMul64Imm, [HWPort1], 3>; 143defm : HWWriteResPair<WriteIMul64Reg, [HWPort1], 3>; 144def : WriteRes<WriteIMulH, []> { let Latency = 3; } 145 146defm : X86WriteRes<WriteBSWAP32, [HWPort15], 1, [1], 1>; 147defm : X86WriteRes<WriteBSWAP64, [HWPort06, HWPort15], 2, [1,1], 2>; 148defm : X86WriteRes<WriteCMPXCHG,[HWPort06, HWPort0156], 5, [2,3], 5>; 149defm : X86WriteRes<WriteCMPXCHGRMW,[HWPort23,HWPort06,HWPort0156,HWPort237,HWPort4], 9, [1,2,1,1,1], 6>; 150defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>; 151 152// Integer shifts and rotates. 153defm : HWWriteResPair<WriteShift, [HWPort06], 1>; 154defm : HWWriteResPair<WriteShiftCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 155defm : HWWriteResPair<WriteRotate, [HWPort06], 1, [1], 1>; 156defm : HWWriteResPair<WriteRotateCL, [HWPort06, HWPort0156], 3, [2,1], 3>; 157 158// SHLD/SHRD. 159defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>; 160defm : X86WriteRes<WriteSHDrrcl,[HWPort1, HWPort06, HWPort0156], 6, [1, 1, 2], 4>; 161defm : X86WriteRes<WriteSHDmri, [HWPort1, HWPort23, HWPort237, HWPort0156], 10, [1, 1, 1, 1], 4>; 162defm : X86WriteRes<WriteSHDmrcl,[HWPort1, HWPort23, HWPort237, HWPort06, HWPort0156], 12, [1, 1, 1, 1, 2], 6>; 163 164defm : HWWriteResPair<WriteJump, [HWPort06], 1>; 165defm : HWWriteResPair<WriteCRC32, [HWPort1], 3>; 166 167defm : HWWriteResPair<WriteCMOV, [HWPort06,HWPort0156], 2, [1,1], 2>; // Conditional move. 168defm : X86WriteRes<WriteFCMOV, [HWPort1], 3, [1], 1>; // x87 conditional move. 169def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc. 170def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> { 171 let Latency = 2; 172 let NumMicroOps = 3; 173} 174 175defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>; 176defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>; 177defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>; 178defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>; 179defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>; 180defm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 3>; 181//defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>; 182 183// This is for simple LEAs with one or two input operands. 184// The complex ones can only execute on port 1, and they require two cycles on 185// the port to read all inputs. We don't model that. 186def : WriteRes<WriteLEA, [HWPort15]>; 187 188// Bit counts. 189defm : HWWriteResPair<WriteBSF, [HWPort1], 3>; 190defm : HWWriteResPair<WriteBSR, [HWPort1], 3>; 191defm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>; 192defm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>; 193defm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>; 194 195// BMI1 BEXTR/BLS, BMI2 BZHI 196defm : HWWriteResPair<WriteBEXTR, [HWPort06,HWPort15], 2, [1,1], 2>; 197defm : HWWriteResPair<WriteBLS, [HWPort15], 1>; 198defm : HWWriteResPair<WriteBZHI, [HWPort15], 1>; 199 200// TODO: Why isn't the HWDivider used? 201defm : X86WriteRes<WriteDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 22, [], 9>; 202defm : X86WriteRes<WriteDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 203defm : X86WriteRes<WriteDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 204defm : X86WriteRes<WriteDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156], 98, [7,7,3,3,1,11], 32>; 205defm : X86WriteRes<WriteDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 206defm : X86WriteRes<WriteDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 207defm : X86WriteRes<WriteDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 208defm : X86WriteRes<WriteDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 209 210defm : X86WriteRes<WriteIDiv8, [HWPort0,HWPort1,HWPort5,HWPort6], 23, [], 9>; 211defm : X86WriteRes<WriteIDiv16, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 212defm : X86WriteRes<WriteIDiv32, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 213defm : X86WriteRes<WriteIDiv64, [HWPort0,HWPort1,HWPort5,HWPort6,HWPort06,HWPort0156], 112, [4,2,4,8,14,34], 66>; 214defm : X86WriteRes<WriteIDiv8Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 215defm : X86WriteRes<WriteIDiv16Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 216defm : X86WriteRes<WriteIDiv32Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 217defm : X86WriteRes<WriteIDiv64Ld, [HWPort0,HWPort23,HWDivider], 29, [1,1,10], 2>; 218 219// Scalar and vector floating point. 220defm : X86WriteRes<WriteFLD0, [HWPort01], 1, [1], 1>; 221defm : X86WriteRes<WriteFLD1, [HWPort01], 1, [2], 2>; 222defm : X86WriteRes<WriteFLDC, [HWPort01], 1, [2], 2>; 223defm : X86WriteRes<WriteFLoad, [HWPort23], 5, [1], 1>; 224defm : X86WriteRes<WriteFLoadX, [HWPort23], 6, [1], 1>; 225defm : X86WriteRes<WriteFLoadY, [HWPort23], 7, [1], 1>; 226defm : X86WriteRes<WriteFMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 227defm : X86WriteRes<WriteFMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 228defm : X86WriteRes<WriteFStore, [HWPort237,HWPort4], 1, [1,1], 2>; 229defm : X86WriteRes<WriteFStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 230defm : X86WriteRes<WriteFStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 231defm : X86WriteRes<WriteFStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 232defm : X86WriteRes<WriteFStoreNTX, [HWPort237,HWPort4], 1, [1,1], 2>; 233defm : X86WriteRes<WriteFStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 234 235defm : X86WriteRes<WriteFMaskedStore32, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 236defm : X86WriteRes<WriteFMaskedStore32Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 237defm : X86WriteRes<WriteFMaskedStore64, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 238defm : X86WriteRes<WriteFMaskedStore64Y, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 239 240defm : X86WriteRes<WriteFMove, [HWPort5], 1, [1], 1>; 241defm : X86WriteRes<WriteFMoveX, [HWPort5], 1, [1], 1>; 242defm : X86WriteRes<WriteFMoveY, [HWPort5], 1, [1], 1>; 243defm : X86WriteRes<WriteEMMS, [HWPort01,HWPort15,HWPort015,HWPort0156], 31, [8,1,21,1], 31>; 244 245defm : HWWriteResPair<WriteFAdd, [HWPort1], 3, [1], 1, 5>; 246defm : HWWriteResPair<WriteFAddX, [HWPort1], 3, [1], 1, 6>; 247defm : HWWriteResPair<WriteFAddY, [HWPort1], 3, [1], 1, 7>; 248defm : HWWriteResPair<WriteFAddZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 249defm : HWWriteResPair<WriteFAdd64, [HWPort1], 3, [1], 1, 5>; 250defm : HWWriteResPair<WriteFAdd64X, [HWPort1], 3, [1], 1, 6>; 251defm : HWWriteResPair<WriteFAdd64Y, [HWPort1], 3, [1], 1, 7>; 252defm : HWWriteResPair<WriteFAdd64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 253 254defm : HWWriteResPair<WriteFCmp, [HWPort1], 3, [1], 1, 5>; 255defm : HWWriteResPair<WriteFCmpX, [HWPort1], 3, [1], 1, 6>; 256defm : HWWriteResPair<WriteFCmpY, [HWPort1], 3, [1], 1, 7>; 257defm : HWWriteResPair<WriteFCmpZ, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 258defm : HWWriteResPair<WriteFCmp64, [HWPort1], 3, [1], 1, 5>; 259defm : HWWriteResPair<WriteFCmp64X, [HWPort1], 3, [1], 1, 6>; 260defm : HWWriteResPair<WriteFCmp64Y, [HWPort1], 3, [1], 1, 7>; 261defm : HWWriteResPair<WriteFCmp64Z, [HWPort1], 3, [1], 1, 7>; // Unsupported = 1 262 263defm : HWWriteResPair<WriteFCom, [HWPort1], 3>; 264 265defm : HWWriteResPair<WriteFMul, [HWPort01], 5, [1], 1, 5>; 266defm : HWWriteResPair<WriteFMulX, [HWPort01], 5, [1], 1, 6>; 267defm : HWWriteResPair<WriteFMulY, [HWPort01], 5, [1], 1, 7>; 268defm : HWWriteResPair<WriteFMulZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 269defm : HWWriteResPair<WriteFMul64, [HWPort01], 5, [1], 1, 5>; 270defm : HWWriteResPair<WriteFMul64X, [HWPort01], 5, [1], 1, 6>; 271defm : HWWriteResPair<WriteFMul64Y, [HWPort01], 5, [1], 1, 7>; 272defm : HWWriteResPair<WriteFMul64Z, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 273 274defm : HWWriteResPair<WriteFDiv, [HWPort0,HWFPDivider], 13, [1,7], 1, 5>; 275defm : HWWriteResPair<WriteFDivX, [HWPort0,HWFPDivider], 13, [1,7], 1, 6>; 276defm : HWWriteResPair<WriteFDivY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 277defm : HWWriteResPair<WriteFDivZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 278defm : HWWriteResPair<WriteFDiv64, [HWPort0,HWFPDivider], 20, [1,14], 1, 5>; 279defm : HWWriteResPair<WriteFDiv64X, [HWPort0,HWFPDivider], 20, [1,14], 1, 6>; 280defm : HWWriteResPair<WriteFDiv64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 281defm : HWWriteResPair<WriteFDiv64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 282 283defm : HWWriteResPair<WriteFRcp, [HWPort0], 5, [1], 1, 5>; 284defm : HWWriteResPair<WriteFRcpX, [HWPort0], 5, [1], 1, 6>; 285defm : HWWriteResPair<WriteFRcpY, [HWPort0,HWPort015], 11, [2,1], 3, 7>; 286defm : HWWriteResPair<WriteFRcpZ, [HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 287 288defm : HWWriteResPair<WriteFRsqrt, [HWPort0], 5, [1], 1, 5>; 289defm : HWWriteResPair<WriteFRsqrtX,[HWPort0], 5, [1], 1, 6>; 290defm : HWWriteResPair<WriteFRsqrtY,[HWPort0,HWPort015], 11, [2,1], 3, 7>; 291defm : HWWriteResPair<WriteFRsqrtZ,[HWPort0,HWPort015], 11, [2,1], 3, 7>; // Unsupported = 1 292 293defm : HWWriteResPair<WriteFSqrt, [HWPort0,HWFPDivider], 11, [1,7], 1, 5>; 294defm : HWWriteResPair<WriteFSqrtX, [HWPort0,HWFPDivider], 11, [1,7], 1, 6>; 295defm : HWWriteResPair<WriteFSqrtY, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; 296defm : HWWriteResPair<WriteFSqrtZ, [HWPort0,HWPort15,HWFPDivider], 21, [2,1,14], 3, 7>; // Unsupported = 1 297defm : HWWriteResPair<WriteFSqrt64, [HWPort0,HWFPDivider], 16, [1,14], 1, 5>; 298defm : HWWriteResPair<WriteFSqrt64X, [HWPort0,HWFPDivider], 16, [1,14], 1, 6>; 299defm : HWWriteResPair<WriteFSqrt64Y, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; 300defm : HWWriteResPair<WriteFSqrt64Z, [HWPort0,HWPort15,HWFPDivider], 35, [2,1,28], 3, 7>; // Unsupported = 1 301defm : HWWriteResPair<WriteFSqrt80, [HWPort0,HWFPDivider], 23, [1,17]>; 302 303defm : HWWriteResPair<WriteFMA, [HWPort01], 5, [1], 1, 5>; 304defm : HWWriteResPair<WriteFMAX, [HWPort01], 5, [1], 1, 6>; 305defm : HWWriteResPair<WriteFMAY, [HWPort01], 5, [1], 1, 7>; 306defm : HWWriteResPair<WriteFMAZ, [HWPort01], 5, [1], 1, 7>; // Unsupported = 1 307defm : HWWriteResPair<WriteDPPD, [HWPort0,HWPort1,HWPort5], 9, [1,1,1], 3, 6>; 308defm : HWWriteResPair<WriteDPPS, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 6>; 309defm : HWWriteResPair<WriteDPPSY, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; 310defm : HWWriteResPair<WriteDPPSZ, [HWPort0,HWPort1,HWPort5], 14, [2,1,1], 4, 7>; // Unsupported = 1 311defm : HWWriteResPair<WriteFSign, [HWPort0], 1>; 312defm : X86WriteRes<WriteFRnd, [HWPort23], 6, [1], 1>; 313defm : X86WriteRes<WriteFRndY, [HWPort23], 6, [1], 1>; 314defm : X86WriteRes<WriteFRndZ, [HWPort23], 6, [1], 1>; // Unsupported = 1 315defm : X86WriteRes<WriteFRndLd, [HWPort1,HWPort23], 12, [2,1], 3>; 316defm : X86WriteRes<WriteFRndYLd, [HWPort1,HWPort23], 13, [2,1], 3>; 317defm : X86WriteRes<WriteFRndZLd, [HWPort1,HWPort23], 13, [2,1], 3>; // Unsupported = 1 318defm : HWWriteResPair<WriteFLogic, [HWPort5], 1, [1], 1, 6>; 319defm : HWWriteResPair<WriteFLogicY, [HWPort5], 1, [1], 1, 7>; 320defm : HWWriteResPair<WriteFLogicZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 321defm : HWWriteResPair<WriteFTest, [HWPort0], 1, [1], 1, 6>; 322defm : HWWriteResPair<WriteFTestY, [HWPort0], 1, [1], 1, 7>; 323defm : HWWriteResPair<WriteFTestZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 324defm : HWWriteResPair<WriteFShuffle, [HWPort5], 1, [1], 1, 6>; 325defm : HWWriteResPair<WriteFShuffleY, [HWPort5], 1, [1], 1, 7>; 326defm : HWWriteResPair<WriteFShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 327defm : HWWriteResPair<WriteFVarShuffle, [HWPort5], 1, [1], 1, 6>; 328defm : HWWriteResPair<WriteFVarShuffleY, [HWPort5], 1, [1], 1, 7>; 329defm : HWWriteResPair<WriteFVarShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 330defm : HWWriteResPair<WriteFBlend, [HWPort015], 1, [1], 1, 6>; 331defm : HWWriteResPair<WriteFBlendY, [HWPort015], 1, [1], 1, 7>; 332defm : HWWriteResPair<WriteFBlendZ, [HWPort015], 1, [1], 1, 7>; // Unsupported = 1 333defm : HWWriteResPair<WriteFShuffle256, [HWPort5], 3, [1], 1, 7>; 334defm : HWWriteResPair<WriteFVarShuffle256, [HWPort5], 3, [1], 1, 7>; 335defm : HWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2], 2, 6>; 336defm : HWWriteResPair<WriteFVarBlendY, [HWPort5], 2, [2], 2, 7>; 337defm : HWWriteResPair<WriteFVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 338 339// Conversion between integer and float. 340defm : HWWriteResPair<WriteCvtSD2I, [HWPort1], 3>; 341defm : HWWriteResPair<WriteCvtPD2I, [HWPort1], 3>; 342defm : HWWriteResPair<WriteCvtPD2IY, [HWPort1], 3>; 343defm : HWWriteResPair<WriteCvtPD2IZ, [HWPort1], 3>; // Unsupported = 1 344defm : HWWriteResPair<WriteCvtSS2I, [HWPort1], 3>; 345defm : HWWriteResPair<WriteCvtPS2I, [HWPort1], 3>; 346defm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3>; 347defm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3>; // Unsupported = 1 348 349defm : HWWriteResPair<WriteCvtI2SD, [HWPort1], 4>; 350defm : HWWriteResPair<WriteCvtI2PD, [HWPort1], 4>; 351defm : HWWriteResPair<WriteCvtI2PDY, [HWPort1], 4>; 352defm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1], 4>; // Unsupported = 1 353defm : HWWriteResPair<WriteCvtI2SS, [HWPort1], 4>; 354defm : HWWriteResPair<WriteCvtI2PS, [HWPort1], 4>; 355defm : HWWriteResPair<WriteCvtI2PSY, [HWPort1], 4>; 356defm : HWWriteResPair<WriteCvtI2PSZ, [HWPort1], 4>; // Unsupported = 1 357 358defm : HWWriteResPair<WriteCvtSS2SD, [HWPort1], 3>; 359defm : HWWriteResPair<WriteCvtPS2PD, [HWPort1], 3>; 360defm : HWWriteResPair<WriteCvtPS2PDY, [HWPort1], 3>; 361defm : HWWriteResPair<WriteCvtPS2PDZ, [HWPort1], 3>; // Unsupported = 1 362defm : HWWriteResPair<WriteCvtSD2SS, [HWPort1], 3>; 363defm : HWWriteResPair<WriteCvtPD2PS, [HWPort1], 3>; 364defm : HWWriteResPair<WriteCvtPD2PSY, [HWPort1], 3>; 365defm : HWWriteResPair<WriteCvtPD2PSZ, [HWPort1], 3>; // Unsupported = 1 366 367defm : X86WriteRes<WriteCvtPH2PS, [HWPort0,HWPort5], 2, [1,1], 2>; 368defm : X86WriteRes<WriteCvtPH2PSY, [HWPort0,HWPort5], 2, [1,1], 2>; 369defm : X86WriteRes<WriteCvtPH2PSZ, [HWPort0,HWPort5], 2, [1,1], 2>; // Unsupported = 1 370defm : X86WriteRes<WriteCvtPH2PSLd, [HWPort0,HWPort23], 6, [1,1], 2>; 371defm : X86WriteRes<WriteCvtPH2PSYLd, [HWPort0,HWPort23], 7, [1,1], 2>; 372defm : X86WriteRes<WriteCvtPH2PSZLd, [HWPort0,HWPort23], 7, [1,1], 2>; // Unsupported = 1 373 374defm : X86WriteRes<WriteCvtPS2PH, [HWPort1,HWPort5], 4, [1,1], 2>; 375defm : X86WriteRes<WriteCvtPS2PHY, [HWPort1,HWPort5], 6, [1,1], 2>; 376defm : X86WriteRes<WriteCvtPS2PHZ, [HWPort1,HWPort5], 6, [1,1], 2>; // Unsupported = 1 377defm : X86WriteRes<WriteCvtPS2PHSt, [HWPort1,HWPort4,HWPort5,HWPort237], 5, [1,1,1,1], 4>; 378defm : X86WriteRes<WriteCvtPS2PHYSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; 379defm : X86WriteRes<WriteCvtPS2PHZSt, [HWPort1,HWPort4,HWPort5,HWPort237], 7, [1,1,1,1], 4>; // Unsupported = 1 380 381// Vector integer operations. 382defm : X86WriteRes<WriteVecLoad, [HWPort23], 5, [1], 1>; 383defm : X86WriteRes<WriteVecLoadX, [HWPort23], 6, [1], 1>; 384defm : X86WriteRes<WriteVecLoadY, [HWPort23], 7, [1], 1>; 385defm : X86WriteRes<WriteVecLoadNT, [HWPort23], 6, [1], 1>; 386defm : X86WriteRes<WriteVecLoadNTY, [HWPort23], 7, [1], 1>; 387defm : X86WriteRes<WriteVecMaskedLoad, [HWPort23,HWPort5], 8, [1,2], 3>; 388defm : X86WriteRes<WriteVecMaskedLoadY, [HWPort23,HWPort5], 9, [1,2], 3>; 389defm : X86WriteRes<WriteVecStore, [HWPort237,HWPort4], 1, [1,1], 2>; 390defm : X86WriteRes<WriteVecStoreX, [HWPort237,HWPort4], 1, [1,1], 2>; 391defm : X86WriteRes<WriteVecStoreY, [HWPort237,HWPort4], 1, [1,1], 2>; 392defm : X86WriteRes<WriteVecStoreNT, [HWPort237,HWPort4], 1, [1,1], 2>; 393defm : X86WriteRes<WriteVecStoreNTY, [HWPort237,HWPort4], 1, [1,1], 2>; 394defm : X86WriteRes<WriteVecMaskedStore, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 395defm : X86WriteRes<WriteVecMaskedStoreY, [HWPort0,HWPort4,HWPort237,HWPort15], 5, [1,1,1,1], 4>; 396defm : X86WriteRes<WriteVecMove, [HWPort015], 1, [1], 1>; 397defm : X86WriteRes<WriteVecMoveX, [HWPort015], 1, [1], 1>; 398defm : X86WriteRes<WriteVecMoveY, [HWPort015], 1, [1], 1>; 399defm : X86WriteRes<WriteVecMoveToGpr, [HWPort0], 1, [1], 1>; 400defm : X86WriteRes<WriteVecMoveFromGpr, [HWPort5], 1, [1], 1>; 401 402defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 5>; 403defm : HWWriteResPair<WriteVecLogicX,[HWPort015], 1, [1], 1, 6>; 404defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>; 405defm : HWWriteResPair<WriteVecLogicZ,[HWPort015], 1, [1], 1, 7>; // Unsupported = 1 406defm : HWWriteResPair<WriteVecTest, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 407defm : HWWriteResPair<WriteVecTestY, [HWPort0,HWPort5], 4, [1,1], 2, 7>; 408defm : HWWriteResPair<WriteVecTestZ, [HWPort0,HWPort5], 4, [1,1], 2, 7>; // Unsupported = 1 409defm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 5>; 410defm : HWWriteResPair<WriteVecALUX, [HWPort15], 1, [1], 1, 6>; 411defm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>; 412defm : HWWriteResPair<WriteVecALUZ, [HWPort15], 1, [1], 1, 7>; // Unsupported = 1 413defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>; 414defm : HWWriteResPair<WriteVecIMulX, [HWPort0], 5, [1], 1, 6>; 415defm : HWWriteResPair<WriteVecIMulY, [HWPort0], 5, [1], 1, 7>; 416defm : HWWriteResPair<WriteVecIMulZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 417defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>; 418defm : HWWriteResPair<WritePMULLDY, [HWPort0], 10, [2], 2, 7>; 419defm : HWWriteResPair<WritePMULLDZ, [HWPort0], 10, [2], 2, 7>; // Unsupported = 1 420defm : HWWriteResPair<WriteShuffle, [HWPort5], 1, [1], 1, 5>; 421defm : HWWriteResPair<WriteShuffleX, [HWPort5], 1, [1], 1, 6>; 422defm : HWWriteResPair<WriteShuffleY, [HWPort5], 1, [1], 1, 7>; 423defm : HWWriteResPair<WriteShuffleZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 424defm : HWWriteResPair<WriteVarShuffle, [HWPort5], 1, [1], 1, 5>; 425defm : HWWriteResPair<WriteVarShuffleX,[HWPort5], 1, [1], 1, 6>; 426defm : HWWriteResPair<WriteVarShuffleY,[HWPort5], 1, [1], 1, 7>; 427defm : HWWriteResPair<WriteVarShuffleZ,[HWPort5], 1, [1], 1, 7>; // Unsupported = 1 428defm : HWWriteResPair<WriteBlend, [HWPort5], 1, [1], 1, 6>; 429defm : HWWriteResPair<WriteBlendY, [HWPort5], 1, [1], 1, 7>; 430defm : HWWriteResPair<WriteBlendZ, [HWPort5], 1, [1], 1, 7>; // Unsupported = 1 431defm : HWWriteResPair<WriteShuffle256, [HWPort5], 3, [1], 1, 7>; 432defm : HWWriteResPair<WriteVarShuffle256, [HWPort5], 3, [1], 1, 7>; 433defm : HWWriteResPair<WriteVarBlend, [HWPort5], 2, [2], 2, 6>; 434defm : HWWriteResPair<WriteVarBlendY, [HWPort5], 2, [2], 2, 7>; 435defm : HWWriteResPair<WriteVarBlendZ, [HWPort5], 2, [2], 2, 7>; // Unsupported = 1 436defm : HWWriteResPair<WriteMPSAD, [HWPort0, HWPort5], 7, [1, 2], 3, 6>; 437defm : HWWriteResPair<WriteMPSADY, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; 438defm : HWWriteResPair<WriteMPSADZ, [HWPort0, HWPort5], 7, [1, 2], 3, 7>; // Unsupported = 1 439defm : HWWriteResPair<WritePSADBW, [HWPort0], 5, [1], 1, 5>; 440defm : HWWriteResPair<WritePSADBWX, [HWPort0], 5, [1], 1, 6>; 441defm : HWWriteResPair<WritePSADBWY, [HWPort0], 5, [1], 1, 7>; 442defm : HWWriteResPair<WritePSADBWZ, [HWPort0], 5, [1], 1, 7>; // Unsupported = 1 443defm : HWWriteResPair<WritePHMINPOS, [HWPort0], 5, [1], 1, 6>; 444 445// Vector integer shifts. 446defm : HWWriteResPair<WriteVecShift, [HWPort0], 1, [1], 1, 5>; 447defm : HWWriteResPair<WriteVecShiftX, [HWPort0,HWPort5], 2, [1,1], 2, 6>; 448defm : X86WriteRes<WriteVecShiftY, [HWPort0,HWPort5], 4, [1,1], 2>; 449defm : X86WriteRes<WriteVecShiftZ, [HWPort0,HWPort5], 4, [1,1], 2>; // Unsupported = 1 450defm : X86WriteRes<WriteVecShiftYLd, [HWPort0,HWPort23], 8, [1,1], 2>; 451defm : X86WriteRes<WriteVecShiftZLd, [HWPort0,HWPort23], 8, [1,1], 2>; // Unsupported = 1 452 453defm : HWWriteResPair<WriteVecShiftImm, [HWPort0], 1, [1], 1, 5>; 454defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>; 455defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>; 456defm : HWWriteResPair<WriteVecShiftImmZ, [HWPort0], 1, [1], 1, 7>; // Unsupported = 1 457defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 3, [2,1], 3, 6>; 458defm : HWWriteResPair<WriteVarVecShiftY, [HWPort0, HWPort5], 3, [2,1], 3, 7>; 459defm : HWWriteResPair<WriteVarVecShiftZ, [HWPort0, HWPort5], 3, [2,1], 3, 7>; // Unsupported = 1 460 461// Vector insert/extract operations. 462def : WriteRes<WriteVecInsert, [HWPort5]> { 463 let Latency = 2; 464 let NumMicroOps = 2; 465 let ResourceCycles = [2]; 466} 467def : WriteRes<WriteVecInsertLd, [HWPort5,HWPort23]> { 468 let Latency = 6; 469 let NumMicroOps = 2; 470} 471def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 472 473def : WriteRes<WriteVecExtract, [HWPort0,HWPort5]> { 474 let Latency = 2; 475 let NumMicroOps = 2; 476} 477def : WriteRes<WriteVecExtractSt, [HWPort4,HWPort5,HWPort237]> { 478 let Latency = 2; 479 let NumMicroOps = 3; 480} 481 482// String instructions. 483 484// Packed Compare Implicit Length Strings, Return Mask 485def : WriteRes<WritePCmpIStrM, [HWPort0]> { 486 let Latency = 11; 487 let NumMicroOps = 3; 488 let ResourceCycles = [3]; 489} 490def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> { 491 let Latency = 17; 492 let NumMicroOps = 4; 493 let ResourceCycles = [3,1]; 494} 495 496// Packed Compare Explicit Length Strings, Return Mask 497def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort5, HWPort015, HWPort0156]> { 498 let Latency = 19; 499 let NumMicroOps = 9; 500 let ResourceCycles = [4,3,1,1]; 501} 502def : WriteRes<WritePCmpEStrMLd, [HWPort0, HWPort5, HWPort23, HWPort015, HWPort0156]> { 503 let Latency = 25; 504 let NumMicroOps = 10; 505 let ResourceCycles = [4,3,1,1,1]; 506} 507 508// Packed Compare Implicit Length Strings, Return Index 509def : WriteRes<WritePCmpIStrI, [HWPort0]> { 510 let Latency = 11; 511 let NumMicroOps = 3; 512 let ResourceCycles = [3]; 513} 514def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> { 515 let Latency = 17; 516 let NumMicroOps = 4; 517 let ResourceCycles = [3,1]; 518} 519 520// Packed Compare Explicit Length Strings, Return Index 521def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> { 522 let Latency = 18; 523 let NumMicroOps = 8; 524 let ResourceCycles = [4,3,1]; 525} 526def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> { 527 let Latency = 24; 528 let NumMicroOps = 9; 529 let ResourceCycles = [4,3,1,1]; 530} 531 532// MOVMSK Instructions. 533def : WriteRes<WriteFMOVMSK, [HWPort0]> { let Latency = 3; } 534def : WriteRes<WriteVecMOVMSK, [HWPort0]> { let Latency = 3; } 535def : WriteRes<WriteVecMOVMSKY, [HWPort0]> { let Latency = 3; } 536def : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; } 537 538// AES Instructions. 539def : WriteRes<WriteAESDecEnc, [HWPort5]> { 540 let Latency = 7; 541 let NumMicroOps = 1; 542 let ResourceCycles = [1]; 543} 544def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> { 545 let Latency = 13; 546 let NumMicroOps = 2; 547 let ResourceCycles = [1,1]; 548} 549 550def : WriteRes<WriteAESIMC, [HWPort5]> { 551 let Latency = 14; 552 let NumMicroOps = 2; 553 let ResourceCycles = [2]; 554} 555def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> { 556 let Latency = 20; 557 let NumMicroOps = 3; 558 let ResourceCycles = [2,1]; 559} 560 561def : WriteRes<WriteAESKeyGen, [HWPort0,HWPort5,HWPort015]> { 562 let Latency = 29; 563 let NumMicroOps = 11; 564 let ResourceCycles = [2,7,2]; 565} 566def : WriteRes<WriteAESKeyGenLd, [HWPort0,HWPort5,HWPort23,HWPort015]> { 567 let Latency = 34; 568 let NumMicroOps = 11; 569 let ResourceCycles = [2,7,1,1]; 570} 571 572// Carry-less multiplication instructions. 573def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> { 574 let Latency = 11; 575 let NumMicroOps = 3; 576 let ResourceCycles = [2,1]; 577} 578def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> { 579 let Latency = 17; 580 let NumMicroOps = 4; 581 let ResourceCycles = [2,1,1]; 582} 583 584// Load/store MXCSR. 585def : WriteRes<WriteLDMXCSR, [HWPort0,HWPort23,HWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 586def : WriteRes<WriteSTMXCSR, [HWPort4,HWPort5,HWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 587 588def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; } 589def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; } 590def : WriteRes<WriteFence, [HWPort23, HWPort4]>; 591def : WriteRes<WriteNop, []>; 592 593//================ Exceptions ================// 594 595//-- Specific Scheduling Models --// 596 597// Starting with P0. 598def HWWriteP0 : SchedWriteRes<[HWPort0]>; 599 600def HWWriteP01 : SchedWriteRes<[HWPort01]>; 601 602def HWWrite2P01 : SchedWriteRes<[HWPort01]> { 603 let NumMicroOps = 2; 604} 605def HWWrite3P01 : SchedWriteRes<[HWPort01]> { 606 let NumMicroOps = 3; 607} 608 609def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 610 let NumMicroOps = 2; 611} 612 613def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> { 614 let NumMicroOps = 3; 615 let ResourceCycles = [2, 1]; 616} 617 618// Starting with P1. 619def HWWriteP1 : SchedWriteRes<[HWPort1]>; 620 621 622def HWWrite2P1 : SchedWriteRes<[HWPort1]> { 623 let NumMicroOps = 2; 624 let ResourceCycles = [2]; 625} 626 627// Notation: 628// - r: register. 629// - mm: 64 bit mmx register. 630// - x = 128 bit xmm register. 631// - (x)mm = mmx or xmm register. 632// - y = 256 bit ymm register. 633// - v = any vector register. 634// - m = memory. 635 636//=== Integer Instructions ===// 637//-- Move instructions --// 638 639// XLAT. 640def HWWriteXLAT : SchedWriteRes<[]> { 641 let Latency = 7; 642 let NumMicroOps = 3; 643} 644def : InstRW<[HWWriteXLAT], (instrs XLAT)>; 645 646// PUSHA. 647def HWWritePushA : SchedWriteRes<[]> { 648 let NumMicroOps = 19; 649} 650def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>; 651 652// POPA. 653def HWWritePopA : SchedWriteRes<[]> { 654 let NumMicroOps = 18; 655} 656def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>; 657 658//-- Arithmetic instructions --// 659 660// BTR BTS BTC. 661// m,r. 662def HWWriteBTRSCmr : SchedWriteRes<[]> { 663 let NumMicroOps = 11; 664} 665def : SchedAlias<WriteBitTestSetRegRMW, HWWriteBTRSCmr>; 666 667//-- Control transfer instructions --// 668 669// CALL. 670// i. 671def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> { 672 let NumMicroOps = 4; 673 let ResourceCycles = [1, 2, 1]; 674} 675def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>; 676 677// BOUND. 678// r,m. 679def HWWriteBOUND : SchedWriteRes<[]> { 680 let NumMicroOps = 15; 681} 682def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>; 683 684// INTO. 685def HWWriteINTO : SchedWriteRes<[]> { 686 let NumMicroOps = 4; 687} 688def : InstRW<[HWWriteINTO], (instrs INTO)>; 689 690//-- String instructions --// 691 692// LODSB/W. 693def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>; 694 695// LODSD/Q. 696def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>; 697 698// MOVS. 699def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> { 700 let Latency = 4; 701 let NumMicroOps = 5; 702 let ResourceCycles = [2, 1, 2]; 703} 704def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 705 706// CMPS. 707def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> { 708 let Latency = 4; 709 let NumMicroOps = 5; 710 let ResourceCycles = [2, 3]; 711} 712def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>; 713 714//-- Other --// 715 716// RDPMC.f 717def HWWriteRDPMC : SchedWriteRes<[]> { 718 let NumMicroOps = 34; 719} 720def : InstRW<[HWWriteRDPMC], (instrs RDPMC)>; 721 722// RDRAND. 723def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> { 724 let NumMicroOps = 17; 725 let ResourceCycles = [1, 16]; 726} 727def : InstRW<[HWWriteRDRAND], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 728 729//=== Floating Point x87 Instructions ===// 730//-- Move instructions --// 731 732// FLD. 733// m80. 734def : InstRW<[HWWriteP01], (instrs LD_Frr)>; 735 736// FBLD. 737// m80. 738def HWWriteFBLD : SchedWriteRes<[]> { 739 let Latency = 47; 740 let NumMicroOps = 43; 741} 742def : InstRW<[HWWriteFBLD], (instrs FBLDm)>; 743 744// FST(P). 745// r. 746def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>; 747 748// FFREE. 749def : InstRW<[HWWriteP01], (instregex "FFREE")>; 750 751// FNSAVE. 752def HWWriteFNSAVE : SchedWriteRes<[]> { 753 let NumMicroOps = 147; 754} 755def : InstRW<[HWWriteFNSAVE], (instrs FSAVEm)>; 756 757// FRSTOR. 758def HWWriteFRSTOR : SchedWriteRes<[]> { 759 let NumMicroOps = 90; 760} 761def : InstRW<[HWWriteFRSTOR], (instrs FRSTORm)>; 762 763//-- Arithmetic instructions --// 764 765// FCOMPP FUCOMPP. 766// r. 767def : InstRW<[HWWrite2P01], (instrs FCOMPP, UCOM_FPPr)>; 768 769// FCOMI(P) FUCOMI(P). 770// m. 771def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 772 773// FTST. 774def : InstRW<[HWWriteP1], (instregex "TST_F")>; 775 776// FXAM. 777def : InstRW<[HWWrite2P1], (instrs FXAM)>; 778 779// FPREM. 780def HWWriteFPREM : SchedWriteRes<[]> { 781 let Latency = 19; 782 let NumMicroOps = 28; 783} 784def : InstRW<[HWWriteFPREM], (instrs FPREM)>; 785 786// FPREM1. 787def HWWriteFPREM1 : SchedWriteRes<[]> { 788 let Latency = 27; 789 let NumMicroOps = 41; 790} 791def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>; 792 793// FRNDINT. 794def HWWriteFRNDINT : SchedWriteRes<[]> { 795 let Latency = 11; 796 let NumMicroOps = 17; 797} 798def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>; 799 800//-- Math instructions --// 801 802// FSCALE. 803def HWWriteFSCALE : SchedWriteRes<[]> { 804 let Latency = 75; // 49-125 805 let NumMicroOps = 50; // 25-75 806} 807def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>; 808 809// FXTRACT. 810def HWWriteFXTRACT : SchedWriteRes<[]> { 811 let Latency = 15; 812 let NumMicroOps = 17; 813} 814def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>; 815 816//////////////////////////////////////////////////////////////////////////////// 817// Horizontal add/sub instructions. 818//////////////////////////////////////////////////////////////////////////////// 819 820defm : HWWriteResPair<WriteFHAdd, [HWPort1, HWPort5], 5, [1,2], 3, 6>; 821defm : HWWriteResPair<WriteFHAddY, [HWPort1, HWPort5], 5, [1,2], 3, 7>; 822defm : HWWriteResPair<WritePHAdd, [HWPort5, HWPort15], 3, [2,1], 3, 5>; 823defm : HWWriteResPair<WritePHAddX, [HWPort5, HWPort15], 3, [2,1], 3, 6>; 824defm : HWWriteResPair<WritePHAddY, [HWPort5, HWPort15], 3, [2,1], 3, 7>; 825 826//=== Floating Point XMM and YMM Instructions ===// 827 828// Remaining instrs. 829 830def HWWriteResGroup0 : SchedWriteRes<[HWPort23]> { 831 let Latency = 6; 832 let NumMicroOps = 1; 833 let ResourceCycles = [1]; 834} 835def: InstRW<[HWWriteResGroup0], (instrs VBROADCASTSSrm)>; 836def: InstRW<[HWWriteResGroup0], (instregex "(V?)MOVSHDUPrm", 837 "(V?)MOVSLDUPrm", 838 "VPBROADCAST(D|Q)rm")>; 839 840def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> { 841 let Latency = 7; 842 let NumMicroOps = 1; 843 let ResourceCycles = [1]; 844} 845def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128, 846 VBROADCASTI128, 847 VBROADCASTSDYrm, 848 VBROADCASTSSYrm, 849 VMOVDDUPYrm, 850 VMOVSHDUPYrm, 851 VMOVSLDUPYrm)>; 852def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m", 853 "VPBROADCAST(D|Q)Yrm")>; 854 855def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> { 856 let Latency = 5; 857 let NumMicroOps = 1; 858 let ResourceCycles = [1]; 859} 860def: InstRW<[HWWriteResGroup0_2], (instregex "MOVSX(16|32|64)rm(8|16|32)", 861 "MOVZX(16|32|64)rm(8|16)", 862 "(V?)MOVDDUPrm")>; 863 864def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> { 865 let Latency = 1; 866 let NumMicroOps = 2; 867 let ResourceCycles = [1,1]; 868} 869def: InstRW<[HWWriteResGroup1], (instrs FBSTPm, VMPTRSTm)>; 870def: InstRW<[HWWriteResGroup1], (instregex "ST_FP(32|64|80)m")>; 871 872def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> { 873 let Latency = 1; 874 let NumMicroOps = 1; 875 let ResourceCycles = [1]; 876} 877def: InstRW<[HWWriteResGroup2], (instregex "VPSLLVQ(Y?)rr", 878 "VPSRLVQ(Y?)rr")>; 879 880def HWWriteResGroup3 : SchedWriteRes<[HWPort1]> { 881 let Latency = 1; 882 let NumMicroOps = 1; 883 let ResourceCycles = [1]; 884} 885def: InstRW<[HWWriteResGroup3], (instregex "COM(P?)_FST0r", 886 "UCOM_F(P?)r")>; 887 888def HWWriteResGroup4 : SchedWriteRes<[HWPort5]> { 889 let Latency = 1; 890 let NumMicroOps = 1; 891 let ResourceCycles = [1]; 892} 893def: InstRW<[HWWriteResGroup4], (instrs MMX_MOVQ2DQrr)>; 894 895def HWWriteResGroup5 : SchedWriteRes<[HWPort6]> { 896 let Latency = 1; 897 let NumMicroOps = 1; 898 let ResourceCycles = [1]; 899} 900def: InstRW<[HWWriteResGroup5], (instregex "JMP(16|32|64)r")>; 901 902def HWWriteResGroup6 : SchedWriteRes<[HWPort01]> { 903 let Latency = 1; 904 let NumMicroOps = 1; 905 let ResourceCycles = [1]; 906} 907def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>; 908 909def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> { 910 let Latency = 1; 911 let NumMicroOps = 1; 912 let ResourceCycles = [1]; 913} 914def: InstRW<[HWWriteResGroup7], (instrs CDQ, CQO)>; 915 916def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { 917 let Latency = 1; 918 let NumMicroOps = 1; 919 let ResourceCycles = [1]; 920} 921def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr")>; 922 923def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { 924 let Latency = 1; 925 let NumMicroOps = 1; 926 let ResourceCycles = [1]; 927} 928def: InstRW<[HWWriteResGroup9], (instregex "VPBLENDD(Y?)rri")>; 929 930def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> { 931 let Latency = 1; 932 let NumMicroOps = 1; 933 let ResourceCycles = [1]; 934} 935def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE, 936 CMC, STC, 937 SGDT64m, 938 SIDT64m, 939 SMSW16m, 940 STRm, 941 SYSCALL)>; 942 943def HWWriteResGroup11 : SchedWriteRes<[HWPort0,HWPort23]> { 944 let Latency = 6; 945 let NumMicroOps = 2; 946 let ResourceCycles = [1,1]; 947} 948def: InstRW<[HWWriteResGroup11], (instregex "(V?)CVTPS2PDrm")>; 949 950def HWWriteResGroup11_1 : SchedWriteRes<[HWPort0,HWPort23]> { 951 let Latency = 7; 952 let NumMicroOps = 2; 953 let ResourceCycles = [1,1]; 954} 955def: InstRW<[HWWriteResGroup11_1], (instrs VPSLLVQrm, VPSRLVQrm)>; 956def: InstRW<[HWWriteResGroup11_1], (instregex "(V?)CVTSS2SDrm")>; 957 958def HWWriteResGroup11_2 : SchedWriteRes<[HWPort0,HWPort23]> { 959 let Latency = 8; 960 let NumMicroOps = 2; 961 let ResourceCycles = [1,1]; 962} 963def: InstRW<[HWWriteResGroup11_2], (instrs VPSLLVQYrm, VPSRLVQYrm)>; 964 965def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> { 966 let Latency = 8; 967 let NumMicroOps = 2; 968 let ResourceCycles = [1,1]; 969} 970def: InstRW<[HWWriteResGroup12], (instrs MMX_CVTPI2PSirm)>; 971def: InstRW<[HWWriteResGroup12], (instregex "P(DEP|EXT)(32|64)rm")>; 972 973def HWWriteResGroup13 : SchedWriteRes<[HWPort5,HWPort23]> { 974 let Latency = 6; 975 let NumMicroOps = 2; 976 let ResourceCycles = [1,1]; 977} 978def: InstRW<[HWWriteResGroup13], (instregex "(V?)PMOV(SX|ZX)BDrm", 979 "(V?)PMOV(SX|ZX)BQrm", 980 "(V?)PMOV(SX|ZX)BWrm", 981 "(V?)PMOV(SX|ZX)DQrm", 982 "(V?)PMOV(SX|ZX)WDrm", 983 "(V?)PMOV(SX|ZX)WQrm")>; 984 985def HWWriteResGroup13_1 : SchedWriteRes<[HWPort5,HWPort23]> { 986 let Latency = 8; 987 let NumMicroOps = 2; 988 let ResourceCycles = [1,1]; 989} 990def: InstRW<[HWWriteResGroup13_1], (instrs VPMOVSXBDYrm, 991 VPMOVSXBQYrm, 992 VPMOVSXWQYrm)>; 993 994def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> { 995 let Latency = 6; 996 let NumMicroOps = 2; 997 let ResourceCycles = [1,1]; 998} 999def: InstRW<[HWWriteResGroup14], (instrs FARJMP64)>; 1000def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>; 1001 1002def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> { 1003 let Latency = 6; 1004 let NumMicroOps = 2; 1005 let ResourceCycles = [1,1]; 1006} 1007def: InstRW<[HWWriteResGroup16], (instregex "ANDN(32|64)rm", 1008 "MOVBE(16|32|64)rm")>; 1009 1010def HWWriteResGroup17 : SchedWriteRes<[HWPort23,HWPort015]> { 1011 let Latency = 7; 1012 let NumMicroOps = 2; 1013 let ResourceCycles = [1,1]; 1014} 1015def: InstRW<[HWWriteResGroup17], (instrs VINSERTF128rm, 1016 VINSERTI128rm, 1017 VPBLENDDrmi)>; 1018 1019def HWWriteResGroup17_2 : SchedWriteRes<[HWPort23,HWPort015]> { 1020 let Latency = 8; 1021 let NumMicroOps = 2; 1022 let ResourceCycles = [1,1]; 1023} 1024def: InstRW<[HWWriteResGroup17_2], (instrs VPBLENDDYrmi)>; 1025 1026def HWWriteResGroup18 : SchedWriteRes<[HWPort23,HWPort0156]> { 1027 let Latency = 6; 1028 let NumMicroOps = 2; 1029 let ResourceCycles = [1,1]; 1030} 1031def: InstRW<[HWWriteResGroup18], (instrs POP16r, POP32r, POP64r)>; 1032def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)rmr")>; 1033 1034def HWWriteResGroup19 : SchedWriteRes<[HWPort237,HWPort0156]> { 1035 let Latency = 2; 1036 let NumMicroOps = 2; 1037 let ResourceCycles = [1,1]; 1038} 1039def: InstRW<[HWWriteResGroup19], (instrs SFENCE)>; 1040 1041def HWWriteResGroup21 : SchedWriteRes<[HWPort4,HWPort6,HWPort237]> { 1042 let Latency = 2; 1043 let NumMicroOps = 3; 1044 let ResourceCycles = [1,1,1]; 1045} 1046def: InstRW<[HWWriteResGroup21], (instrs FNSTCW16m)>; 1047 1048def HWWriteResGroup23 : SchedWriteRes<[HWPort4,HWPort237,HWPort15]> { 1049 let Latency = 2; 1050 let NumMicroOps = 3; 1051 let ResourceCycles = [1,1,1]; 1052} 1053def: InstRW<[HWWriteResGroup23], (instregex "MOVBE(32|64)mr")>; 1054 1055def HWWriteResGroup23_16 : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> { 1056 let Latency = 2; 1057 let NumMicroOps = 3; 1058 let ResourceCycles = [1,1,1]; 1059} 1060def: InstRW<[HWWriteResGroup23_16], (instrs MOVBE16mr)>; 1061 1062def HWWriteResGroup24 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 1063 let Latency = 2; 1064 let NumMicroOps = 3; 1065 let ResourceCycles = [1,1,1]; 1066} 1067def: InstRW<[HWWriteResGroup24], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 1068 STOSB, STOSL, STOSQ, STOSW)>; 1069def: InstRW<[HWWriteResGroup24], (instregex "PUSH(16|32|64)rmr")>; 1070 1071def HWWriteResGroup25 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 1072 let Latency = 7; 1073 let NumMicroOps = 4; 1074 let ResourceCycles = [1,1,1,1]; 1075} 1076def: InstRW<[HWWriteResGroup25], (instregex "SAR(8|16|32|64)m(1|i)", 1077 "SHL(8|16|32|64)m(1|i)", 1078 "SHR(8|16|32|64)m(1|i)")>; 1079 1080def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1081 let Latency = 7; 1082 let NumMicroOps = 4; 1083 let ResourceCycles = [1,1,1,1]; 1084} 1085def: InstRW<[HWWriteResGroup26], (instregex "POP(16|32|64)rmm", 1086 "PUSH(16|32|64)rmm")>; 1087 1088def HWWriteResGroup28 : SchedWriteRes<[HWPort01]> { 1089 let Latency = 2; 1090 let NumMicroOps = 2; 1091 let ResourceCycles = [2]; 1092} 1093def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>; 1094 1095def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> { 1096 let Latency = 2; 1097 let NumMicroOps = 2; 1098 let ResourceCycles = [2]; 1099} 1100def: InstRW<[HWWriteResGroup30], (instrs LFENCE, 1101 MFENCE, 1102 WAIT, 1103 XGETBV)>; 1104 1105def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> { 1106 let Latency = 2; 1107 let NumMicroOps = 2; 1108 let ResourceCycles = [1,1]; 1109} 1110def: InstRW<[HWWriteResGroup31], (instregex "(V?)CVTPS2PDrr", 1111 "(V?)CVTSS2SDrr")>; 1112 1113def HWWriteResGroup32 : SchedWriteRes<[HWPort6,HWPort0156]> { 1114 let Latency = 2; 1115 let NumMicroOps = 2; 1116 let ResourceCycles = [1,1]; 1117} 1118def: InstRW<[HWWriteResGroup32], (instregex "CLFLUSH")>; 1119 1120def HWWriteResGroup33 : SchedWriteRes<[HWPort01,HWPort015]> { 1121 let Latency = 2; 1122 let NumMicroOps = 2; 1123 let ResourceCycles = [1,1]; 1124} 1125def: InstRW<[HWWriteResGroup33], (instrs MMX_MOVDQ2Qrr)>; 1126 1127def HWWriteResGroup35 : SchedWriteRes<[HWPort06,HWPort0156]> { 1128 let Latency = 2; 1129 let NumMicroOps = 2; 1130 let ResourceCycles = [1,1]; 1131} 1132def: InstRW<[HWWriteResGroup35], (instrs CWD, JCXZ, JECXZ, JRCXZ)>; 1133 1134def HWWriteResGroup36_2 : SchedWriteRes<[HWPort5,HWPort23]> { 1135 let Latency = 7; 1136 let NumMicroOps = 3; 1137 let ResourceCycles = [2,1]; 1138} 1139def: InstRW<[HWWriteResGroup36_2], (instrs MMX_PACKSSDWirm, 1140 MMX_PACKSSWBirm, 1141 MMX_PACKUSWBirm)>; 1142 1143def HWWriteResGroup37 : SchedWriteRes<[HWPort23,HWPort0156]> { 1144 let Latency = 7; 1145 let NumMicroOps = 3; 1146 let ResourceCycles = [1,2]; 1147} 1148def: InstRW<[HWWriteResGroup37], (instrs LEAVE, LEAVE64, 1149 SCASB, SCASL, SCASQ, SCASW)>; 1150 1151def HWWriteResGroup39 : SchedWriteRes<[HWPort0,HWPort01,HWPort23]> { 1152 let Latency = 7; 1153 let NumMicroOps = 3; 1154 let ResourceCycles = [1,1,1]; 1155} 1156def: InstRW<[HWWriteResGroup39], (instrs FLDCW16m)>; 1157 1158def HWWriteResGroup41 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 1159 let Latency = 7; 1160 let NumMicroOps = 3; 1161 let ResourceCycles = [1,1,1]; 1162} 1163def: InstRW<[HWWriteResGroup41], (instrs LRETQ, RETL, RETQ)>; 1164 1165def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> { 1166 let Latency = 3; 1167 let NumMicroOps = 4; 1168 let ResourceCycles = [1,1,1,1]; 1169} 1170def: InstRW<[HWWriteResGroup44], (instregex "CALL(16|32|64)r")>; 1171 1172def HWWriteResGroup45 : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 1173 let Latency = 3; 1174 let NumMicroOps = 4; 1175 let ResourceCycles = [1,1,1,1]; 1176} 1177def: InstRW<[HWWriteResGroup45], (instrs CALL64pcrel32)>; 1178 1179def HWWriteResGroup46 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06]> { 1180 let Latency = 8; 1181 let NumMicroOps = 5; 1182 let ResourceCycles = [1,1,1,2]; 1183} 1184def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)", 1185 "ROR(8|16|32|64)m(1|i)")>; 1186 1187def HWWriteResGroup46_1 : SchedWriteRes<[HWPort06]> { 1188 let Latency = 2; 1189 let NumMicroOps = 2; 1190 let ResourceCycles = [2]; 1191} 1192def: InstRW<[HWWriteResGroup46_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1193 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1194 1195def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1196 let Latency = 8; 1197 let NumMicroOps = 5; 1198 let ResourceCycles = [1,1,1,2]; 1199} 1200def: InstRW<[HWWriteResGroup47], (instregex "XADD(8|16|32|64)rm")>; 1201 1202def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1203 let Latency = 8; 1204 let NumMicroOps = 5; 1205 let ResourceCycles = [1,1,1,1,1]; 1206} 1207def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m")>; 1208def: InstRW<[HWWriteResGroup48], (instrs FARCALL64)>; 1209 1210def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> { 1211 let Latency = 3; 1212 let NumMicroOps = 1; 1213 let ResourceCycles = [1]; 1214} 1215def: InstRW<[HWWriteResGroup50], (instrs MMX_CVTPI2PSirr)>; 1216def: InstRW<[HWWriteResGroup50], (instregex "P(DEP|EXT)(32|64)rr", 1217 "(V?)CVTDQ2PS(Y?)rr")>; 1218 1219def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> { 1220 let Latency = 3; 1221 let NumMicroOps = 1; 1222 let ResourceCycles = [1]; 1223} 1224def: InstRW<[HWWriteResGroup51], (instregex "VPBROADCAST(B|W)rr")>; 1225 1226def HWWriteResGroup52 : SchedWriteRes<[HWPort1,HWPort23]> { 1227 let Latency = 9; 1228 let NumMicroOps = 2; 1229 let ResourceCycles = [1,1]; 1230} 1231def: InstRW<[HWWriteResGroup52], (instregex "(V?)CVTPS2DQrm", 1232 "(V?)CVTTPS2DQrm")>; 1233 1234def HWWriteResGroup52_1 : SchedWriteRes<[HWPort1,HWPort23]> { 1235 let Latency = 10; 1236 let NumMicroOps = 2; 1237 let ResourceCycles = [1,1]; 1238} 1239def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1240 "ILD_F(16|32|64)m")>; 1241def: InstRW<[HWWriteResGroup52_1], (instrs VCVTDQ2PSYrm, 1242 VCVTPS2DQYrm, 1243 VCVTTPS2DQYrm)>; 1244 1245def HWWriteResGroup53_1 : SchedWriteRes<[HWPort5,HWPort23]> { 1246 let Latency = 9; 1247 let NumMicroOps = 2; 1248 let ResourceCycles = [1,1]; 1249} 1250def: InstRW<[HWWriteResGroup53_1], (instrs VPMOVSXBWYrm, 1251 VPMOVSXDQYrm, 1252 VPMOVSXWDYrm, 1253 VPMOVZXWDYrm)>; 1254 1255def HWWriteResGroup57 : SchedWriteRes<[HWPort5,HWPort0156]> { 1256 let Latency = 3; 1257 let NumMicroOps = 3; 1258 let ResourceCycles = [2,1]; 1259} 1260def: InstRW<[HWWriteResGroup57], (instrs MMX_PACKSSDWirr, 1261 MMX_PACKSSWBirr, 1262 MMX_PACKUSWBirr)>; 1263 1264def HWWriteResGroup58 : SchedWriteRes<[HWPort6,HWPort0156]> { 1265 let Latency = 3; 1266 let NumMicroOps = 3; 1267 let ResourceCycles = [1,2]; 1268} 1269def: InstRW<[HWWriteResGroup58], (instregex "CLD")>; 1270 1271def HWWriteResGroup59 : SchedWriteRes<[HWPort06,HWPort0156]> { 1272 let Latency = 3; 1273 let NumMicroOps = 3; 1274 let ResourceCycles = [1,2]; 1275} 1276def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)", 1277 "RCR(8|16|32|64)r(1|i)")>; 1278 1279def HWWriteResGroup61 : SchedWriteRes<[HWPort0,HWPort4,HWPort237]> { 1280 let Latency = 4; 1281 let NumMicroOps = 3; 1282 let ResourceCycles = [1,1,1]; 1283} 1284def: InstRW<[HWWriteResGroup61], (instrs FNSTSWm)>; 1285 1286def HWWriteResGroup62 : SchedWriteRes<[HWPort1,HWPort4,HWPort237]> { 1287 let Latency = 4; 1288 let NumMicroOps = 3; 1289 let ResourceCycles = [1,1,1]; 1290} 1291def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m", 1292 "IST_F(16|32)m")>; 1293 1294def HWWriteResGroup66 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> { 1295 let Latency = 9; 1296 let NumMicroOps = 5; 1297 let ResourceCycles = [1,1,1,2]; 1298} 1299def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)", 1300 "RCR(8|16|32|64)m(1|i)")>; 1301 1302def HWWriteResGroup68 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> { 1303 let Latency = 9; 1304 let NumMicroOps = 6; 1305 let ResourceCycles = [1,1,1,3]; 1306} 1307def: InstRW<[HWWriteResGroup68], (instregex "XCHG(8|16|32|64)rm")>; 1308 1309def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1310 let Latency = 9; 1311 let NumMicroOps = 6; 1312 let ResourceCycles = [1,1,1,2,1]; 1313} 1314def: InstRW<[HWWriteResGroup69], (instregex "ROL(8|16|32|64)mCL", 1315 "ROR(8|16|32|64)mCL", 1316 "SAR(8|16|32|64)mCL", 1317 "SHL(8|16|32|64)mCL", 1318 "SHR(8|16|32|64)mCL")>; 1319def: SchedAlias<WriteADCRMW, HWWriteResGroup69>; 1320 1321def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> { 1322 let Latency = 4; 1323 let NumMicroOps = 2; 1324 let ResourceCycles = [1,1]; 1325} 1326def: InstRW<[HWWriteResGroup70], (instregex "(V?)CVT(T?)SD2SI(64)?rr", 1327 "(V?)CVT(T?)SS2SI(64)?rr")>; 1328 1329def HWWriteResGroup71 : SchedWriteRes<[HWPort0,HWPort5]> { 1330 let Latency = 4; 1331 let NumMicroOps = 2; 1332 let ResourceCycles = [1,1]; 1333} 1334def: InstRW<[HWWriteResGroup71], (instrs VCVTPS2PDYrr)>; 1335 1336def HWWriteResGroup72 : SchedWriteRes<[HWPort0,HWPort0156]> { 1337 let Latency = 4; 1338 let NumMicroOps = 2; 1339 let ResourceCycles = [1,1]; 1340} 1341def: InstRW<[HWWriteResGroup72], (instrs FNSTSW16r)>; 1342 1343def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> { 1344 let Latency = 4; 1345 let NumMicroOps = 2; 1346 let ResourceCycles = [1,1]; 1347} 1348def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDirr, 1349 MMX_CVTPD2PIirr, 1350 MMX_CVTPS2PIirr, 1351 MMX_CVTTPD2PIirr, 1352 MMX_CVTTPS2PIirr)>; 1353def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr", 1354 "(V?)CVTPD2PSrr", 1355 "(V?)CVTSD2SSrr", 1356 "(V?)CVTSI(64)?2SDrr", 1357 "(V?)CVTSI2SSrr", 1358 "(V?)CVT(T?)PD2DQrr")>; 1359 1360def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> { 1361 let Latency = 11; 1362 let NumMicroOps = 3; 1363 let ResourceCycles = [2,1]; 1364} 1365def: InstRW<[HWWriteResGroup75], (instregex "FICOM(P?)(16|32)m")>; 1366 1367def HWWriteResGroup76 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1368 let Latency = 9; 1369 let NumMicroOps = 3; 1370 let ResourceCycles = [1,1,1]; 1371} 1372def: InstRW<[HWWriteResGroup76], (instregex "(V?)CVTSD2SI(64)?rm", 1373 "(V?)CVTSS2SI(64)?rm", 1374 "(V?)CVTTSD2SI(64)?rm", 1375 "VCVTTSS2SI64rm", 1376 "(V?)CVTTSS2SIrm")>; 1377 1378def HWWriteResGroup77 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> { 1379 let Latency = 10; 1380 let NumMicroOps = 3; 1381 let ResourceCycles = [1,1,1]; 1382} 1383def: InstRW<[HWWriteResGroup77], (instrs VCVTPS2PDYrm)>; 1384 1385def HWWriteResGroup78 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1386 let Latency = 10; 1387 let NumMicroOps = 3; 1388 let ResourceCycles = [1,1,1]; 1389} 1390def: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm, 1391 CVTPD2DQrm, 1392 CVTTPD2DQrm, 1393 MMX_CVTPD2PIirm, 1394 MMX_CVTTPD2PIirm, 1395 CVTDQ2PDrm, 1396 VCVTDQ2PDrm)>; 1397 1398def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1399 let Latency = 9; 1400 let NumMicroOps = 3; 1401 let ResourceCycles = [1,1,1]; 1402} 1403def: InstRW<[HWWriteResGroup78_1], (instrs MMX_CVTPI2PDirm, 1404 CVTSD2SSrm, CVTSD2SSrm_Int, 1405 VCVTSD2SSrm, VCVTSD2SSrm_Int)>; 1406 1407def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { 1408 let Latency = 9; 1409 let NumMicroOps = 3; 1410 let ResourceCycles = [1,1,1]; 1411} 1412def: InstRW<[HWWriteResGroup80], (instregex "VPBROADCAST(B|W)(Y?)rm")>; 1413 1414def HWWriteResGroup81 : SchedWriteRes<[HWPort0156]> { 1415 let Latency = 4; 1416 let NumMicroOps = 4; 1417 let ResourceCycles = [4]; 1418} 1419def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>; 1420 1421def HWWriteResGroup82 : SchedWriteRes<[]> { 1422 let Latency = 0; 1423 let NumMicroOps = 4; 1424 let ResourceCycles = []; 1425} 1426def: InstRW<[HWWriteResGroup82], (instrs VZEROUPPER)>; 1427 1428def HWWriteResGroup83 : SchedWriteRes<[HWPort1,HWPort6,HWPort0156]> { 1429 let Latency = 4; 1430 let NumMicroOps = 4; 1431 let ResourceCycles = [1,1,2]; 1432} 1433def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>; 1434 1435def HWWriteResGroup87 : SchedWriteRes<[HWPort1,HWPort6,HWPort23,HWPort0156]> { 1436 let Latency = 9; 1437 let NumMicroOps = 5; 1438 let ResourceCycles = [1,2,1,1]; 1439} 1440def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm", 1441 "LSL(16|32|64)rm")>; 1442 1443def HWWriteResGroup88 : SchedWriteRes<[HWPort4,HWPort237,HWPort0156]> { 1444 let Latency = 5; 1445 let NumMicroOps = 6; 1446 let ResourceCycles = [1,1,4]; 1447} 1448def: InstRW<[HWWriteResGroup88], (instregex "PUSHF(16|64)")>; 1449 1450def HWWriteResGroup89 : SchedWriteRes<[HWPort0]> { 1451 let Latency = 5; 1452 let NumMicroOps = 1; 1453 let ResourceCycles = [1]; 1454} 1455def: InstRW<[HWWriteResGroup89], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 1456 1457def HWWriteResGroup91_2 : SchedWriteRes<[HWPort0,HWPort23]> { 1458 let Latency = 11; 1459 let NumMicroOps = 2; 1460 let ResourceCycles = [1,1]; 1461} 1462def: InstRW<[HWWriteResGroup91_2], (instregex "(V?)PCMPGTQrm")>; 1463 1464def HWWriteResGroup91_3 : SchedWriteRes<[HWPort0,HWPort23]> { 1465 let Latency = 12; 1466 let NumMicroOps = 2; 1467 let ResourceCycles = [1,1]; 1468} 1469def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m")>; 1470def: InstRW<[HWWriteResGroup91_3], (instrs VPCMPGTQYrm)>; 1471 1472def HWWriteResGroup93 : SchedWriteRes<[HWPort1,HWPort5]> { 1473 let Latency = 5; 1474 let NumMicroOps = 3; 1475 let ResourceCycles = [1,2]; 1476} 1477def: InstRW<[HWWriteResGroup93], (instregex "(V?)CVTSI642SSrr")>; 1478 1479def HWWriteResGroup94 : SchedWriteRes<[HWPort1,HWPort6,HWPort06]> { 1480 let Latency = 5; 1481 let NumMicroOps = 3; 1482 let ResourceCycles = [1,1,1]; 1483} 1484def: InstRW<[HWWriteResGroup94], (instregex "STR(16|32|64)r")>; 1485 1486def HWWriteResGroup97 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort23]> { 1487 let Latency = 10; 1488 let NumMicroOps = 4; 1489 let ResourceCycles = [1,1,1,1]; 1490} 1491def: InstRW<[HWWriteResGroup97], (instregex "CVTTSS2SI64rm")>; 1492 1493def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { 1494 let Latency = 5; 1495 let NumMicroOps = 5; 1496 let ResourceCycles = [1,4]; 1497} 1498def: InstRW<[HWWriteResGroup99], (instrs PAUSE)>; 1499 1500def HWWriteResGroup100 : SchedWriteRes<[HWPort06,HWPort0156]> { 1501 let Latency = 5; 1502 let NumMicroOps = 5; 1503 let ResourceCycles = [1,4]; 1504} 1505def: InstRW<[HWWriteResGroup100], (instrs XSETBV)>; 1506 1507def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> { 1508 let Latency = 6; 1509 let NumMicroOps = 2; 1510 let ResourceCycles = [1,1]; 1511} 1512def: InstRW<[HWWriteResGroup102], (instrs VCVTDQ2PDYrr, 1513 VCVTPD2PSYrr, 1514 VCVTPD2DQYrr, 1515 VCVTTPD2DQYrr)>; 1516 1517def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> { 1518 let Latency = 13; 1519 let NumMicroOps = 3; 1520 let ResourceCycles = [2,1]; 1521} 1522def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1523 1524def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { 1525 let Latency = 12; 1526 let NumMicroOps = 3; 1527 let ResourceCycles = [1,1,1]; 1528} 1529def: InstRW<[HWWriteResGroup104], (instrs VCVTDQ2PDYrm)>; 1530 1531def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> { 1532 let Latency = 6; 1533 let NumMicroOps = 4; 1534 let ResourceCycles = [1,1,1,1]; 1535} 1536def: InstRW<[HWWriteResGroup107], (instregex "SLDT(16|32|64)r")>; 1537 1538def HWWriteResGroup108 : SchedWriteRes<[HWPort6,HWPort0156]> { 1539 let Latency = 6; 1540 let NumMicroOps = 6; 1541 let ResourceCycles = [1,5]; 1542} 1543def: InstRW<[HWWriteResGroup108], (instrs STD)>; 1544 1545def HWWriteResGroup114 : SchedWriteRes<[HWPort6,HWPort06,HWPort15,HWPort0156]> { 1546 let Latency = 7; 1547 let NumMicroOps = 7; 1548 let ResourceCycles = [2,2,1,2]; 1549} 1550def: InstRW<[HWWriteResGroup114], (instrs LOOP)>; 1551 1552def HWWriteResGroup115 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1553 let Latency = 15; 1554 let NumMicroOps = 3; 1555 let ResourceCycles = [1,1,1]; 1556} 1557def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>; 1558 1559def HWWriteResGroup120 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1560 let Latency = 16; 1561 let NumMicroOps = 10; 1562 let ResourceCycles = [1,1,1,4,1,2]; 1563} 1564def: InstRW<[HWWriteResGroup120], (instregex "RCL(8|16|32|64)mCL")>; 1565 1566def HWWriteResGroup129 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { 1567 let Latency = 11; 1568 let NumMicroOps = 7; 1569 let ResourceCycles = [2,2,3]; 1570} 1571def: InstRW<[HWWriteResGroup129], (instregex "RCL(16|32|64)rCL", 1572 "RCR(16|32|64)rCL")>; 1573 1574def HWWriteResGroup130 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 1575 let Latency = 11; 1576 let NumMicroOps = 9; 1577 let ResourceCycles = [1,4,1,3]; 1578} 1579def: InstRW<[HWWriteResGroup130], (instrs RCL8rCL)>; 1580 1581def HWWriteResGroup131 : SchedWriteRes<[HWPort06,HWPort0156]> { 1582 let Latency = 11; 1583 let NumMicroOps = 11; 1584 let ResourceCycles = [2,9]; 1585} 1586def: InstRW<[HWWriteResGroup131], (instrs LOOPE, LOOPNE)>; 1587 1588def HWWriteResGroup132 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1589 let Latency = 17; 1590 let NumMicroOps = 14; 1591 let ResourceCycles = [1,1,1,4,2,5]; 1592} 1593def: InstRW<[HWWriteResGroup132], (instrs CMPXCHG8B)>; 1594 1595def HWWriteResGroup135 : SchedWriteRes<[HWPort1,HWPort23,HWPort237,HWPort06,HWPort15,HWPort0156]> { 1596 let Latency = 19; 1597 let NumMicroOps = 11; 1598 let ResourceCycles = [2,1,1,3,1,3]; 1599} 1600def: InstRW<[HWWriteResGroup135], (instregex "RCR(8|16|32|64)mCL")>; 1601 1602def HWWriteResGroup142 : SchedWriteRes<[HWPort1,HWPort06,HWPort15,HWPort0156]> { 1603 let Latency = 14; 1604 let NumMicroOps = 10; 1605 let ResourceCycles = [2,3,1,4]; 1606} 1607def: InstRW<[HWWriteResGroup142], (instrs RCR8rCL)>; 1608 1609def HWWriteResGroup143 : SchedWriteRes<[HWPort23,HWPort0156]> { 1610 let Latency = 19; 1611 let NumMicroOps = 15; 1612 let ResourceCycles = [1,14]; 1613} 1614def: InstRW<[HWWriteResGroup143], (instrs POPF16)>; 1615 1616def HWWriteResGroup144 : SchedWriteRes<[HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1617 let Latency = 21; 1618 let NumMicroOps = 8; 1619 let ResourceCycles = [1,1,1,1,1,1,2]; 1620} 1621def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>; 1622 1623def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> { 1624 let Latency = 8; 1625 let NumMicroOps = 20; 1626 let ResourceCycles = [1,1]; 1627} 1628def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>; 1629 1630def HWWriteResGroup146 : SchedWriteRes<[HWPort0,HWPort4,HWPort5,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1631 let Latency = 22; 1632 let NumMicroOps = 19; 1633 let ResourceCycles = [2,1,4,1,1,4,6]; 1634} 1635def: InstRW<[HWWriteResGroup146], (instrs CMPXCHG16B)>; 1636 1637def HWWriteResGroup147 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> { 1638 let Latency = 17; 1639 let NumMicroOps = 15; 1640 let ResourceCycles = [2,1,2,4,2,4]; 1641} 1642def: InstRW<[HWWriteResGroup147], (instrs XCH_F)>; 1643 1644def HWWriteResGroup149 : SchedWriteRes<[HWPort5,HWPort6,HWPort06,HWPort0156]> { 1645 let Latency = 18; 1646 let NumMicroOps = 8; 1647 let ResourceCycles = [1,1,1,5]; 1648} 1649def: InstRW<[HWWriteResGroup149], (instrs CPUID, RDTSC)>; 1650 1651def HWWriteResGroup151 : SchedWriteRes<[HWPort6,HWPort23,HWPort0156]> { 1652 let Latency = 23; 1653 let NumMicroOps = 19; 1654 let ResourceCycles = [3,1,15]; 1655} 1656def: InstRW<[HWWriteResGroup151], (instregex "XRSTOR(64)?")>; 1657 1658def HWWriteResGroup154 : SchedWriteRes<[HWPort0]> { 1659 let Latency = 20; 1660 let NumMicroOps = 1; 1661 let ResourceCycles = [1]; 1662} 1663def: InstRW<[HWWriteResGroup154], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1664 1665def HWWriteResGroup155 : SchedWriteRes<[HWPort0,HWPort23]> { 1666 let Latency = 27; 1667 let NumMicroOps = 2; 1668 let ResourceCycles = [1,1]; 1669} 1670def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>; 1671 1672def HWWriteResGroup156 : SchedWriteRes<[HWPort5,HWPort6,HWPort0156]> { 1673 let Latency = 20; 1674 let NumMicroOps = 10; 1675 let ResourceCycles = [1,2,7]; 1676} 1677def: InstRW<[HWWriteResGroup156], (instrs MWAITrr)>; 1678 1679def HWWriteResGroup161 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1680 let Latency = 30; 1681 let NumMicroOps = 3; 1682 let ResourceCycles = [1,1,1]; 1683} 1684def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>; 1685 1686def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> { 1687 let Latency = 24; 1688 let NumMicroOps = 1; 1689 let ResourceCycles = [1]; 1690} 1691def: InstRW<[HWWriteResGroup162], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1692 1693def HWWriteResGroup163 : SchedWriteRes<[HWPort0,HWPort23]> { 1694 let Latency = 31; 1695 let NumMicroOps = 2; 1696 let ResourceCycles = [1,1]; 1697} 1698def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>; 1699 1700def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1701 let Latency = 30; 1702 let NumMicroOps = 27; 1703 let ResourceCycles = [1,5,1,1,19]; 1704} 1705def: InstRW<[HWWriteResGroup164], (instrs XSAVE64)>; 1706 1707def HWWriteResGroup165 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> { 1708 let Latency = 31; 1709 let NumMicroOps = 28; 1710 let ResourceCycles = [1,6,1,1,19]; 1711} 1712def: InstRW<[HWWriteResGroup165], (instrs XSAVE)>; 1713def: InstRW<[HWWriteResGroup165], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 1714 1715def HWWriteResGroup166 : SchedWriteRes<[HWPort0,HWPort1,HWPort23]> { 1716 let Latency = 34; 1717 let NumMicroOps = 3; 1718 let ResourceCycles = [1,1,1]; 1719} 1720def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>; 1721 1722def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> { 1723 let Latency = 35; 1724 let NumMicroOps = 23; 1725 let ResourceCycles = [1,5,3,4,10]; 1726} 1727def: InstRW<[HWWriteResGroup170], (instregex "IN(8|16|32)ri", 1728 "IN(8|16|32)rr")>; 1729 1730def HWWriteResGroup171 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort237,HWPort06,HWPort0156]> { 1731 let Latency = 36; 1732 let NumMicroOps = 23; 1733 let ResourceCycles = [1,5,2,1,4,10]; 1734} 1735def: InstRW<[HWWriteResGroup171], (instregex "OUT(8|16|32)ir", 1736 "OUT(8|16|32)rr")>; 1737 1738def HWWriteResGroup175 : SchedWriteRes<[HWPort1,HWPort4,HWPort5,HWPort6,HWPort23,HWPort237,HWPort15,HWPort0156]> { 1739 let Latency = 41; 1740 let NumMicroOps = 18; 1741 let ResourceCycles = [1,1,2,3,1,1,1,8]; 1742} 1743def: InstRW<[HWWriteResGroup175], (instrs VMCLEARm)>; 1744 1745def HWWriteResGroup176 : SchedWriteRes<[HWPort5,HWPort0156]> { 1746 let Latency = 42; 1747 let NumMicroOps = 22; 1748 let ResourceCycles = [2,20]; 1749} 1750def: InstRW<[HWWriteResGroup176], (instrs RDTSCP)>; 1751 1752def HWWriteResGroup177 : SchedWriteRes<[HWPort0,HWPort01,HWPort23,HWPort05,HWPort06,HWPort015,HWPort0156]> { 1753 let Latency = 61; 1754 let NumMicroOps = 64; 1755 let ResourceCycles = [2,2,8,1,10,2,39]; 1756} 1757def: InstRW<[HWWriteResGroup177], (instrs FLDENVm)>; 1758 1759def HWWriteResGroup178 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 1760 let Latency = 64; 1761 let NumMicroOps = 88; 1762 let ResourceCycles = [4,4,31,1,2,1,45]; 1763} 1764def: InstRW<[HWWriteResGroup178], (instrs FXRSTOR64)>; 1765 1766def HWWriteResGroup179 : SchedWriteRes<[HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156]> { 1767 let Latency = 64; 1768 let NumMicroOps = 90; 1769 let ResourceCycles = [4,2,33,1,2,1,47]; 1770} 1771def: InstRW<[HWWriteResGroup179], (instrs FXRSTOR)>; 1772 1773def HWWriteResGroup180 : SchedWriteRes<[HWPort5,HWPort01,HWPort0156]> { 1774 let Latency = 75; 1775 let NumMicroOps = 15; 1776 let ResourceCycles = [6,3,6]; 1777} 1778def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>; 1779 1780def HWWriteResGroup183 : SchedWriteRes<[HWPort0,HWPort1,HWPort4,HWPort5,HWPort6,HWPort237,HWPort06,HWPort0156]> { 1781 let Latency = 115; 1782 let NumMicroOps = 100; 1783 let ResourceCycles = [9,9,11,8,1,11,21,30]; 1784} 1785def: InstRW<[HWWriteResGroup183], (instrs FSTENVm)>; 1786 1787def HWWriteResGroup184 : SchedWriteRes<[HWPort0, HWPort5, HWPort15, HWPort015, HWPort06, HWPort23]> { 1788 let Latency = 26; 1789 let NumMicroOps = 12; 1790 let ResourceCycles = [2,2,1,3,2,2]; 1791} 1792def: InstRW<[HWWriteResGroup184], (instrs VGATHERDPDrm, 1793 VPGATHERDQrm, 1794 VPGATHERDDrm)>; 1795 1796def HWWriteResGroup185 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1797 let Latency = 24; 1798 let NumMicroOps = 22; 1799 let ResourceCycles = [5,3,4,1,5,4]; 1800} 1801def: InstRW<[HWWriteResGroup185], (instrs VGATHERQPDYrm, 1802 VPGATHERQQYrm)>; 1803 1804def HWWriteResGroup186 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1805 let Latency = 28; 1806 let NumMicroOps = 22; 1807 let ResourceCycles = [5,3,4,1,5,4]; 1808} 1809def: InstRW<[HWWriteResGroup186], (instrs VPGATHERQDYrm)>; 1810 1811def HWWriteResGroup187 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1812 let Latency = 25; 1813 let NumMicroOps = 22; 1814 let ResourceCycles = [5,3,4,1,5,4]; 1815} 1816def: InstRW<[HWWriteResGroup187], (instrs VPGATHERQDrm)>; 1817 1818def HWWriteResGroup188 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1819 let Latency = 27; 1820 let NumMicroOps = 20; 1821 let ResourceCycles = [3,3,4,1,5,4]; 1822} 1823def: InstRW<[HWWriteResGroup188], (instrs VGATHERDPDYrm, 1824 VPGATHERDQYrm)>; 1825 1826def HWWriteResGroup189 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1827 let Latency = 27; 1828 let NumMicroOps = 34; 1829 let ResourceCycles = [5,3,8,1,9,8]; 1830} 1831def: InstRW<[HWWriteResGroup189], (instrs VGATHERDPSYrm, 1832 VPGATHERDDYrm)>; 1833 1834def HWWriteResGroup190 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1835 let Latency = 23; 1836 let NumMicroOps = 14; 1837 let ResourceCycles = [3,3,2,1,3,2]; 1838} 1839def: InstRW<[HWWriteResGroup190], (instrs VGATHERQPDrm, 1840 VPGATHERQQrm)>; 1841 1842def HWWriteResGroup191 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1843 let Latency = 28; 1844 let NumMicroOps = 15; 1845 let ResourceCycles = [3,3,2,1,4,2]; 1846} 1847def: InstRW<[HWWriteResGroup191], (instrs VGATHERQPSYrm)>; 1848 1849def HWWriteResGroup192 : SchedWriteRes<[HWPort0, HWPort5, HWPort06, HWPort15, HWPort015, HWPort23]> { 1850 let Latency = 25; 1851 let NumMicroOps = 15; 1852 let ResourceCycles = [3,3,2,1,4,2]; 1853} 1854def: InstRW<[HWWriteResGroup192], (instrs VGATHERQPSrm, 1855 VGATHERDPSrm)>; 1856 1857def: InstRW<[WriteZero], (instrs CLC)>; 1858 1859 1860// Intruction variants handled by the renamer. These might not need execution 1861// ports in certain conditions. 1862// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1863// section "Haswell and Broadwell Pipeline" > "Register allocation and 1864// renaming". 1865// These can be investigated with llvm-exegesis, e.g. 1866// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1867// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1868 1869def HWWriteZeroLatency : SchedWriteRes<[]> { 1870 let Latency = 0; 1871} 1872 1873def HWWriteZeroIdiom : SchedWriteVariant<[ 1874 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1875 SchedVar<NoSchedPred, [WriteALU]> 1876]>; 1877def : InstRW<[HWWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1878 XOR32rr, XOR64rr)>; 1879 1880def HWWriteFZeroIdiom : SchedWriteVariant<[ 1881 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1882 SchedVar<NoSchedPred, [WriteFLogic]> 1883]>; 1884def : InstRW<[HWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1885 VXORPDrr)>; 1886 1887def HWWriteFZeroIdiomY : SchedWriteVariant<[ 1888 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1889 SchedVar<NoSchedPred, [WriteFLogicY]> 1890]>; 1891def : InstRW<[HWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1892 1893def HWWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1894 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1895 SchedVar<NoSchedPred, [WriteVecLogicX]> 1896]>; 1897def : InstRW<[HWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1898 1899def HWWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1900 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1901 SchedVar<NoSchedPred, [WriteVecLogicY]> 1902]>; 1903def : InstRW<[HWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1904 1905def HWWriteVZeroIdiomALUX : SchedWriteVariant<[ 1906 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1907 SchedVar<NoSchedPred, [WriteVecALUX]> 1908]>; 1909def : InstRW<[HWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1910 PSUBDrr, VPSUBDrr, 1911 PSUBQrr, VPSUBQrr, 1912 PSUBWrr, VPSUBWrr, 1913 PCMPGTBrr, VPCMPGTBrr, 1914 PCMPGTDrr, VPCMPGTDrr, 1915 PCMPGTWrr, VPCMPGTWrr)>; 1916 1917def HWWriteVZeroIdiomALUY : SchedWriteVariant<[ 1918 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1919 SchedVar<NoSchedPred, [WriteVecALUY]> 1920]>; 1921def : InstRW<[HWWriteVZeroIdiomALUY], (instrs VPSUBBYrr, 1922 VPSUBDYrr, 1923 VPSUBQYrr, 1924 VPSUBWYrr, 1925 VPCMPGTBYrr, 1926 VPCMPGTDYrr, 1927 VPCMPGTWYrr)>; 1928 1929def HWWritePCMPGTQ : SchedWriteRes<[HWPort0]> { 1930 let Latency = 5; 1931 let NumMicroOps = 1; 1932 let ResourceCycles = [1]; 1933} 1934 1935def HWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1936 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [HWWriteZeroLatency]>, 1937 SchedVar<NoSchedPred, [HWWritePCMPGTQ]> 1938]>; 1939def : InstRW<[HWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1940 VPCMPGTQYrr)>; 1941 1942 1943// The 0x83 ADC/SBB opcodes have special support for immediate 0 to only require 1944// a single uop. It does not apply to the GR8 encoding. And only applies to the 1945// 8-bit immediate since using larger immediate for 0 would be silly. 1946// Unfortunately, this optimization does not apply to the AX/EAX/RAX short 1947// encodings we convert to in MCInstLowering so we exclude AX/EAX/RAX here since 1948// we schedule before that point. 1949// TODO: Should we disable using the short encodings on these CPUs? 1950def HWFastADC0 : MCSchedPredicate< 1951 CheckAll<[ 1952 CheckImmOperand<2, 0>, // Second MCOperand is Imm and has value 0. 1953 CheckNot<CheckRegOperand<1, AX>>, // First MCOperand is not register AX 1954 CheckNot<CheckRegOperand<1, EAX>>, // First MCOperand is not register EAX 1955 CheckNot<CheckRegOperand<1, RAX>> // First MCOperand is not register RAX 1956 ]> 1957>; 1958 1959def HWWriteADC0 : SchedWriteRes<[HWPort06]> { 1960 let Latency = 1; 1961 let NumMicroOps = 1; 1962 let ResourceCycles = [1]; 1963} 1964 1965def HWWriteADC : SchedWriteVariant<[ 1966 SchedVar<HWFastADC0, [HWWriteADC0]>, 1967 SchedVar<NoSchedPred, [WriteADC]> 1968]>; 1969 1970def : InstRW<[HWWriteADC], (instrs ADC16ri8, ADC32ri8, ADC64ri8, 1971 SBB16ri8, SBB32ri8, SBB64ri8)>; 1972 1973// CMOVs that use both Z and C flag require an extra uop. 1974def HWWriteCMOVA_CMOVBErr : SchedWriteRes<[HWPort06,HWPort0156]> { 1975 let Latency = 3; 1976 let ResourceCycles = [1,2]; 1977 let NumMicroOps = 3; 1978} 1979 1980def HWWriteCMOVA_CMOVBErm : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> { 1981 let Latency = 8; 1982 let ResourceCycles = [1,1,2]; 1983 let NumMicroOps = 4; 1984} 1985 1986def HWCMOVA_CMOVBErr : SchedWriteVariant<[ 1987 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [HWWriteCMOVA_CMOVBErr]>, 1988 SchedVar<NoSchedPred, [WriteCMOV]> 1989]>; 1990 1991def HWCMOVA_CMOVBErm : SchedWriteVariant<[ 1992 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [HWWriteCMOVA_CMOVBErm]>, 1993 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1994]>; 1995 1996def : InstRW<[HWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1997def : InstRW<[HWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1998 1999// SETCCs that use both Z and C flag require an extra uop. 2000def HWWriteSETA_SETBEr : SchedWriteRes<[HWPort06,HWPort0156]> { 2001 let Latency = 2; 2002 let ResourceCycles = [1,1]; 2003 let NumMicroOps = 2; 2004} 2005 2006def HWWriteSETA_SETBEm : SchedWriteRes<[HWPort4,HWPort237,HWPort06,HWPort0156]> { 2007 let Latency = 3; 2008 let ResourceCycles = [1,1,1,1]; 2009 let NumMicroOps = 4; 2010} 2011 2012def HWSETA_SETBErr : SchedWriteVariant<[ 2013 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [HWWriteSETA_SETBEr]>, 2014 SchedVar<NoSchedPred, [WriteSETCC]> 2015]>; 2016 2017def HWSETA_SETBErm : SchedWriteVariant<[ 2018 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [HWWriteSETA_SETBEm]>, 2019 SchedVar<NoSchedPred, [WriteSETCCStore]> 2020]>; 2021 2022def : InstRW<[HWSETA_SETBErr], (instrs SETCCr)>; 2023def : InstRW<[HWSETA_SETBErm], (instrs SETCCm)>; 2024 2025} // SchedModel 2026