1//=- X86SchedIceLake.td - X86 Ice Lake Scheduling ------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Ice Lake to support 10// instruction scheduling and other instruction cost heuristics. 11// 12// TODO: This is mainly a copy X86SchedSkylakeServer.td, but allows us to 13// iteratively improve scheduling handling toward better modelling the 14// Ice Lake (Sunny/Cypress Cove) microarchitecture. 15// 16//===----------------------------------------------------------------------===// 17 18def IceLakeModel : SchedMachineModel { 19 // All x86 instructions are modeled as a single micro-op, and Ice Lake can 20 // decode 6 instructions per cycle. 21 let IssueWidth = 6; 22 let MicroOpBufferSize = 224; // Based on the reorder buffer. 23 let LoadLatency = 5; 24 let MispredictPenalty = 14; 25 26 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 27 let LoopMicroOpBufferSize = 50; 28 29 // This flag is set to allow the scheduler to assign a default model to 30 // unrecognized opcodes. 31 let CompleteModel = 0; 32} 33 34let SchedModel = IceLakeModel in { 35 36// Ice Lake can issue micro-ops to 8 different ports in one cycle. 37 38// Ports 0, 1, 5, and 6 handle all computation. 39// Ports 4 and 9 gets the data half of stores. Store data can be available later 40// than the store address, but since we don't model the latency of stores, we 41// can ignore that. 42// Ports 2 and 3 are identical. They handle loads and address calculations. 43// Ports 7 and 8 are identical. They handle stores address calculations. 44def ICXPort0 : ProcResource<1>; 45def ICXPort1 : ProcResource<1>; 46def ICXPort2 : ProcResource<1>; 47def ICXPort3 : ProcResource<1>; 48def ICXPort4 : ProcResource<1>; 49def ICXPort5 : ProcResource<1>; 50def ICXPort6 : ProcResource<1>; 51def ICXPort7 : ProcResource<1>; 52def ICXPort8 : ProcResource<1>; 53def ICXPort9 : ProcResource<1>; 54 55// Many micro-ops are capable of issuing on multiple ports. 56def ICXPort01 : ProcResGroup<[ICXPort0, ICXPort1]>; 57def ICXPort23 : ProcResGroup<[ICXPort2, ICXPort3]>; 58def ICXPort237 : ProcResGroup<[ICXPort2, ICXPort3, ICXPort7]>; 59def ICXPort04 : ProcResGroup<[ICXPort0, ICXPort4]>; 60def ICXPort05 : ProcResGroup<[ICXPort0, ICXPort5]>; 61def ICXPort06 : ProcResGroup<[ICXPort0, ICXPort6]>; 62def ICXPort15 : ProcResGroup<[ICXPort1, ICXPort5]>; 63def ICXPort16 : ProcResGroup<[ICXPort1, ICXPort6]>; 64def ICXPort49 : ProcResGroup<[ICXPort4, ICXPort9]>; 65def ICXPort56 : ProcResGroup<[ICXPort5, ICXPort6]>; 66def ICXPort78 : ProcResGroup<[ICXPort7, ICXPort8]>; 67def ICXPort015 : ProcResGroup<[ICXPort0, ICXPort1, ICXPort5]>; 68def ICXPort056 : ProcResGroup<[ICXPort0, ICXPort5, ICXPort6]>; 69def ICXPort0156: ProcResGroup<[ICXPort0, ICXPort1, ICXPort5, ICXPort6]>; 70 71def ICXDivider : ProcResource<1>; // Integer division issued on port 0. 72// FP division and sqrt on port 0. 73def ICXFPDivider : ProcResource<1>; 74 75// 60 Entry Unified Scheduler 76def ICXPortAny : ProcResGroup<[ICXPort0, ICXPort1, ICXPort2, ICXPort3, ICXPort4, 77 ICXPort5, ICXPort6, ICXPort7, ICXPort8, ICXPort9]> { 78 let BufferSize=60; 79} 80 81// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 82// cycles after the memory operand. 83def : ReadAdvance<ReadAfterLd, 5>; 84 85// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 86// until 5/6/7 cycles after the memory operand. 87def : ReadAdvance<ReadAfterVecLd, 5>; 88def : ReadAdvance<ReadAfterVecXLd, 6>; 89def : ReadAdvance<ReadAfterVecYLd, 7>; 90 91def : ReadAdvance<ReadInt2Fpu, 0>; 92 93// Many SchedWrites are defined in pairs with and without a folded load. 94// Instructions with folded loads are usually micro-fused, so they only appear 95// as two micro-ops when queued in the reservation station. 96// This multiclass defines the resource usage for variants with and without 97// folded loads. 98multiclass ICXWriteResPair<X86FoldableSchedWrite SchedRW, 99 list<ProcResourceKind> ExePorts, 100 int Lat, list<int> Res = [1], int UOps = 1, 101 int LoadLat = 5> { 102 // Register variant is using a single cycle on ExePort. 103 def : WriteRes<SchedRW, ExePorts> { 104 let Latency = Lat; 105 let ResourceCycles = Res; 106 let NumMicroOps = UOps; 107 } 108 109 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 110 // the latency (default = 5). 111 def : WriteRes<SchedRW.Folded, !listconcat([ICXPort23], ExePorts)> { 112 let Latency = !add(Lat, LoadLat); 113 let ResourceCycles = !listconcat([1], Res); 114 let NumMicroOps = !add(UOps, 1); 115 } 116} 117 118// A folded store needs a cycle on port 4 for the store data, and an extra port 119// 2/3/7 cycle to recompute the address. 120def : WriteRes<WriteRMW, [ICXPort237,ICXPort4]>; 121 122// Arithmetic. 123defm : ICXWriteResPair<WriteALU, [ICXPort0156], 1>; // Simple integer ALU op. 124defm : ICXWriteResPair<WriteADC, [ICXPort06], 1>; // Integer ALU + flags op. 125 126// Integer multiplication. 127defm : ICXWriteResPair<WriteIMul8, [ICXPort1], 3>; 128defm : ICXWriteResPair<WriteIMul16, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,2], 4>; 129defm : X86WriteRes<WriteIMul16Imm, [ICXPort1,ICXPort0156], 4, [1,1], 2>; 130defm : X86WriteRes<WriteIMul16ImmLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 131defm : X86WriteRes<WriteIMul16Reg, [ICXPort1], 3, [1], 1>; 132defm : X86WriteRes<WriteIMul16RegLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 133defm : ICXWriteResPair<WriteIMul32, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,1], 3>; 134defm : ICXWriteResPair<WriteMULX32, [ICXPort1,ICXPort06,ICXPort0156], 3, [1,1,1], 3>; 135defm : ICXWriteResPair<WriteIMul32Imm, [ICXPort1], 3>; 136defm : ICXWriteResPair<WriteIMul32Reg, [ICXPort1], 3>; 137defm : ICXWriteResPair<WriteIMul64, [ICXPort1,ICXPort5], 4, [1,1], 2>; 138defm : ICXWriteResPair<WriteMULX64, [ICXPort1,ICXPort5], 3, [1,1], 2>; 139defm : ICXWriteResPair<WriteIMul64Imm, [ICXPort1], 3>; 140defm : ICXWriteResPair<WriteIMul64Reg, [ICXPort1], 3>; 141def ICXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 142def : WriteRes<WriteIMulHLd, []> { 143 let Latency = !add(ICXWriteIMulH.Latency, SkylakeServerModel.LoadLatency); 144} 145 146defm : X86WriteRes<WriteBSWAP32, [ICXPort15], 1, [1], 1>; 147defm : X86WriteRes<WriteBSWAP64, [ICXPort06, ICXPort15], 2, [1,1], 2>; 148defm : X86WriteRes<WriteCMPXCHG,[ICXPort06, ICXPort0156], 5, [2,3], 5>; 149defm : X86WriteRes<WriteCMPXCHGRMW,[ICXPort23,ICXPort06,ICXPort0156,ICXPort237,ICXPort4], 8, [1,2,1,1,1], 6>; 150defm : X86WriteRes<WriteXCHG, [ICXPort0156], 2, [3], 3>; 151 152// TODO: Why isn't the ICXDivider used? 153defm : ICXWriteResPair<WriteDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1, 4>; 154defm : X86WriteRes<WriteDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 155defm : X86WriteRes<WriteDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 156defm : X86WriteRes<WriteDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 157defm : X86WriteRes<WriteDiv16Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 158defm : X86WriteRes<WriteDiv32Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 159defm : X86WriteRes<WriteDiv64Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 160 161defm : X86WriteRes<WriteIDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1>; 162defm : X86WriteRes<WriteIDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 163defm : X86WriteRes<WriteIDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 164defm : X86WriteRes<WriteIDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 165defm : X86WriteRes<WriteIDiv8Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 166defm : X86WriteRes<WriteIDiv16Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 167defm : X86WriteRes<WriteIDiv32Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 168defm : X86WriteRes<WriteIDiv64Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 169 170defm : ICXWriteResPair<WriteCRC32, [ICXPort1], 3>; 171 172def : WriteRes<WriteLEA, [ICXPort15]>; // LEA instructions can't fold loads. 173 174defm : ICXWriteResPair<WriteCMOV, [ICXPort06], 1, [1], 1>; // Conditional move. 175defm : X86WriteRes<WriteFCMOV, [ICXPort1], 3, [1], 1>; // x87 conditional move. 176def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc. 177def : WriteRes<WriteSETCCStore, [ICXPort06,ICXPort4,ICXPort237]> { 178 let Latency = 2; 179 let NumMicroOps = 3; 180} 181defm : X86WriteRes<WriteLAHFSAHF, [ICXPort06], 1, [1], 1>; 182defm : X86WriteRes<WriteBitTest, [ICXPort06], 1, [1], 1>; 183defm : X86WriteRes<WriteBitTestImmLd, [ICXPort06,ICXPort23], 6, [1,1], 2>; 184defm : X86WriteRes<WriteBitTestRegLd, [ICXPort0156,ICXPort23], 6, [1,1], 2>; 185defm : X86WriteRes<WriteBitTestSet, [ICXPort06], 1, [1], 1>; 186defm : X86WriteRes<WriteBitTestSetImmLd, [ICXPort06,ICXPort23], 5, [1,1], 3>; 187defm : X86WriteRes<WriteBitTestSetRegLd, [ICXPort0156,ICXPort23], 5, [1,1], 2>; 188 189// Integer shifts and rotates. 190defm : ICXWriteResPair<WriteShift, [ICXPort06], 1>; 191defm : ICXWriteResPair<WriteShiftCL, [ICXPort06], 3, [3], 3>; 192defm : ICXWriteResPair<WriteRotate, [ICXPort06], 1, [1], 1>; 193defm : ICXWriteResPair<WriteRotateCL, [ICXPort06], 3, [3], 3>; 194 195// SHLD/SHRD. 196defm : X86WriteRes<WriteSHDrri, [ICXPort1], 3, [1], 1>; 197defm : X86WriteRes<WriteSHDrrcl,[ICXPort1,ICXPort06,ICXPort0156], 6, [1, 2, 1], 4>; 198defm : X86WriteRes<WriteSHDmri, [ICXPort1,ICXPort23,ICXPort237,ICXPort0156], 9, [1, 1, 1, 1], 4>; 199defm : X86WriteRes<WriteSHDmrcl,[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort0156], 11, [1, 1, 1, 2, 1], 6>; 200 201// Bit counts. 202defm : ICXWriteResPair<WriteBSF, [ICXPort1], 3>; 203defm : ICXWriteResPair<WriteBSR, [ICXPort1], 3>; 204defm : ICXWriteResPair<WriteLZCNT, [ICXPort1], 3>; 205defm : ICXWriteResPair<WriteTZCNT, [ICXPort1], 3>; 206defm : ICXWriteResPair<WritePOPCNT, [ICXPort1], 3>; 207 208// BMI1 BEXTR/BLS, BMI2 BZHI 209defm : ICXWriteResPair<WriteBEXTR, [ICXPort06,ICXPort15], 2, [1,1], 2>; 210defm : ICXWriteResPair<WriteBLS, [ICXPort15], 1>; 211defm : ICXWriteResPair<WriteBZHI, [ICXPort15], 1>; 212 213// Loads, stores, and moves, not folded with other operations. 214defm : X86WriteRes<WriteLoad, [ICXPort23], 5, [1], 1>; 215defm : X86WriteRes<WriteStore, [ICXPort237, ICXPort4], 1, [1,1], 1>; 216defm : X86WriteRes<WriteStoreNT, [ICXPort237, ICXPort4], 1, [1,1], 2>; 217defm : X86WriteRes<WriteMove, [ICXPort0156], 1, [1], 1>; 218 219// Model the effect of clobbering the read-write mask operand of the GATHER operation. 220// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 221defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 222 223// Idioms that clear a register, like xorps %xmm0, %xmm0. 224// These can often bypass execution ports completely. 225def : WriteRes<WriteZero, []>; 226 227// Branches don't produce values, so they have no latency, but they still 228// consume resources. Indirect branches can fold loads. 229defm : ICXWriteResPair<WriteJump, [ICXPort06], 1>; 230 231// Floating point. This covers both scalar and vector operations. 232defm : X86WriteRes<WriteFLD0, [ICXPort05], 1, [1], 1>; 233defm : X86WriteRes<WriteFLD1, [ICXPort05], 1, [2], 2>; 234defm : X86WriteRes<WriteFLDC, [ICXPort05], 1, [2], 2>; 235defm : X86WriteRes<WriteFLoad, [ICXPort23], 5, [1], 1>; 236defm : X86WriteRes<WriteFLoadX, [ICXPort23], 6, [1], 1>; 237defm : X86WriteRes<WriteFLoadY, [ICXPort23], 7, [1], 1>; 238defm : X86WriteRes<WriteFMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 239defm : X86WriteRes<WriteFMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 240defm : X86WriteRes<WriteFStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 241defm : X86WriteRes<WriteFStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 242defm : X86WriteRes<WriteFStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 243defm : X86WriteRes<WriteFStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 244defm : X86WriteRes<WriteFStoreNTX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 245defm : X86WriteRes<WriteFStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 246 247defm : X86WriteRes<WriteFMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 248defm : X86WriteRes<WriteFMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 249defm : X86WriteRes<WriteFMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 250defm : X86WriteRes<WriteFMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 251 252defm : X86WriteRes<WriteFMove, [ICXPort015], 1, [1], 1>; 253defm : X86WriteRes<WriteFMoveX, [ICXPort015], 1, [1], 1>; 254defm : X86WriteRes<WriteFMoveY, [ICXPort015], 1, [1], 1>; 255defm : X86WriteRes<WriteFMoveZ, [ICXPort05], 1, [1], 1>; 256defm : X86WriteRes<WriteEMMS, [ICXPort05,ICXPort0156], 10, [9,1], 10>; 257 258defm : ICXWriteResPair<WriteFAdd, [ICXPort01], 4, [1], 1, 5>; // Floating point add/sub. 259defm : ICXWriteResPair<WriteFAddX, [ICXPort01], 4, [1], 1, 6>; 260defm : ICXWriteResPair<WriteFAddY, [ICXPort01], 4, [1], 1, 7>; 261defm : ICXWriteResPair<WriteFAddZ, [ICXPort05], 4, [1], 1, 7>; 262defm : ICXWriteResPair<WriteFAdd64, [ICXPort01], 4, [1], 1, 5>; // Floating point double add/sub. 263defm : ICXWriteResPair<WriteFAdd64X, [ICXPort01], 4, [1], 1, 6>; 264defm : ICXWriteResPair<WriteFAdd64Y, [ICXPort01], 4, [1], 1, 7>; 265defm : ICXWriteResPair<WriteFAdd64Z, [ICXPort05], 4, [1], 1, 7>; 266 267defm : ICXWriteResPair<WriteFCmp, [ICXPort01], 4, [1], 1, 5>; // Floating point compare. 268defm : ICXWriteResPair<WriteFCmpX, [ICXPort01], 4, [1], 1, 6>; 269defm : ICXWriteResPair<WriteFCmpY, [ICXPort01], 4, [1], 1, 7>; 270defm : ICXWriteResPair<WriteFCmpZ, [ICXPort05], 4, [1], 1, 7>; 271defm : ICXWriteResPair<WriteFCmp64, [ICXPort01], 4, [1], 1, 5>; // Floating point double compare. 272defm : ICXWriteResPair<WriteFCmp64X, [ICXPort01], 4, [1], 1, 6>; 273defm : ICXWriteResPair<WriteFCmp64Y, [ICXPort01], 4, [1], 1, 7>; 274defm : ICXWriteResPair<WriteFCmp64Z, [ICXPort05], 4, [1], 1, 7>; 275 276defm : ICXWriteResPair<WriteFCom, [ICXPort0], 2>; // Floating point compare to flags (X87). 277defm : ICXWriteResPair<WriteFComX, [ICXPort0], 2>; // Floating point compare to flags (SSE). 278 279defm : ICXWriteResPair<WriteFMul, [ICXPort01], 4, [1], 1, 5>; // Floating point multiplication. 280defm : ICXWriteResPair<WriteFMulX, [ICXPort01], 4, [1], 1, 6>; 281defm : ICXWriteResPair<WriteFMulY, [ICXPort01], 4, [1], 1, 7>; 282defm : ICXWriteResPair<WriteFMulZ, [ICXPort05], 4, [1], 1, 7>; 283defm : ICXWriteResPair<WriteFMul64, [ICXPort01], 4, [1], 1, 5>; // Floating point double multiplication. 284defm : ICXWriteResPair<WriteFMul64X, [ICXPort01], 4, [1], 1, 6>; 285defm : ICXWriteResPair<WriteFMul64Y, [ICXPort01], 4, [1], 1, 7>; 286defm : ICXWriteResPair<WriteFMul64Z, [ICXPort05], 4, [1], 1, 7>; 287 288defm : ICXWriteResPair<WriteFDiv, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 289//defm : ICXWriteResPair<WriteFDivX, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. 290defm : ICXWriteResPair<WriteFDivY, [ICXPort0,ICXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles. 291defm : ICXWriteResPair<WriteFDivZ, [ICXPort0,ICXPort5,ICXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles. 292//defm : ICXWriteResPair<WriteFDiv64, [ICXPort0,ICXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 293//defm : ICXWriteResPair<WriteFDiv64X, [ICXPort0,ICXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles. 294//defm : ICXWriteResPair<WriteFDiv64Y, [ICXPort0,ICXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles. 295defm : ICXWriteResPair<WriteFDiv64Z, [ICXPort0,ICXPort5,ICXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles. 296 297defm : ICXWriteResPair<WriteFSqrt, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 298defm : ICXWriteResPair<WriteFSqrtX, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 6>; 299defm : ICXWriteResPair<WriteFSqrtY, [ICXPort0,ICXFPDivider], 12, [1,6], 1, 7>; 300defm : ICXWriteResPair<WriteFSqrtZ, [ICXPort0,ICXPort5,ICXFPDivider], 20, [2,1,12], 3, 7>; 301defm : ICXWriteResPair<WriteFSqrt64, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 302defm : ICXWriteResPair<WriteFSqrt64X, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 6>; 303defm : ICXWriteResPair<WriteFSqrt64Y, [ICXPort0,ICXFPDivider], 18, [1,12],1, 7>; 304defm : ICXWriteResPair<WriteFSqrt64Z, [ICXPort0,ICXPort5,ICXFPDivider], 32, [2,1,24], 3, 7>; 305defm : ICXWriteResPair<WriteFSqrt80, [ICXPort0,ICXFPDivider], 21, [1,7]>; // Floating point long double square root. 306 307defm : ICXWriteResPair<WriteFRcp, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 308defm : ICXWriteResPair<WriteFRcpX, [ICXPort0], 4, [1], 1, 6>; 309defm : ICXWriteResPair<WriteFRcpY, [ICXPort0], 4, [1], 1, 7>; 310defm : ICXWriteResPair<WriteFRcpZ, [ICXPort0,ICXPort5], 4, [2,1], 3, 7>; 311 312defm : ICXWriteResPair<WriteFRsqrt, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 313defm : ICXWriteResPair<WriteFRsqrtX,[ICXPort0], 4, [1], 1, 6>; 314defm : ICXWriteResPair<WriteFRsqrtY,[ICXPort0], 4, [1], 1, 7>; 315defm : ICXWriteResPair<WriteFRsqrtZ,[ICXPort0,ICXPort5], 9, [2,1], 3, 7>; 316 317defm : ICXWriteResPair<WriteFMA, [ICXPort01], 4, [1], 1, 5>; // Fused Multiply Add. 318defm : ICXWriteResPair<WriteFMAX, [ICXPort01], 4, [1], 1, 6>; 319defm : ICXWriteResPair<WriteFMAY, [ICXPort01], 4, [1], 1, 7>; 320defm : ICXWriteResPair<WriteFMAZ, [ICXPort05], 4, [1], 1, 7>; 321defm : ICXWriteResPair<WriteDPPD, [ICXPort5,ICXPort015], 9, [1,2], 3, 6>; // Floating point double dot product. 322defm : ICXWriteResPair<WriteDPPS, [ICXPort5,ICXPort015], 13, [1,3], 4, 6>; 323defm : ICXWriteResPair<WriteDPPSY,[ICXPort5,ICXPort015], 13, [1,3], 4, 7>; 324defm : ICXWriteResPair<WriteDPPSZ,[ICXPort5,ICXPort015], 13, [1,3], 4, 7>; 325defm : ICXWriteResPair<WriteFSign, [ICXPort0], 1>; // Floating point fabs/fchs. 326defm : ICXWriteResPair<WriteFRnd, [ICXPort01], 8, [2], 2, 6>; // Floating point rounding. 327defm : ICXWriteResPair<WriteFRndY, [ICXPort01], 8, [2], 2, 7>; 328defm : ICXWriteResPair<WriteFRndZ, [ICXPort05], 8, [2], 2, 7>; 329defm : ICXWriteResPair<WriteFLogic, [ICXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 330defm : ICXWriteResPair<WriteFLogicY, [ICXPort015], 1, [1], 1, 7>; 331defm : ICXWriteResPair<WriteFLogicZ, [ICXPort05], 1, [1], 1, 7>; 332defm : ICXWriteResPair<WriteFTest, [ICXPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 333defm : ICXWriteResPair<WriteFTestY, [ICXPort0], 2, [1], 1, 7>; 334defm : ICXWriteResPair<WriteFTestZ, [ICXPort0], 2, [1], 1, 7>; 335defm : ICXWriteResPair<WriteFShuffle, [ICXPort15], 1, [1], 1, 6>; // Floating point vector shuffles. 336defm : ICXWriteResPair<WriteFShuffleY, [ICXPort15], 1, [1], 1, 7>; 337defm : ICXWriteResPair<WriteFShuffleZ, [ICXPort5], 1, [1], 1, 7>; 338defm : ICXWriteResPair<WriteFVarShuffle, [ICXPort15], 1, [1], 1, 6>; // Floating point vector variable shuffles. 339defm : ICXWriteResPair<WriteFVarShuffleY, [ICXPort15], 1, [1], 1, 7>; 340defm : ICXWriteResPair<WriteFVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 341defm : ICXWriteResPair<WriteFBlend, [ICXPort015], 1, [1], 1, 6>; // Floating point vector blends. 342defm : ICXWriteResPair<WriteFBlendY,[ICXPort015], 1, [1], 1, 7>; 343defm : ICXWriteResPair<WriteFBlendZ,[ICXPort015], 1, [1], 1, 7>; 344defm : ICXWriteResPair<WriteFVarBlend, [ICXPort015], 2, [2], 2, 6>; // Fp vector variable blends. 345defm : ICXWriteResPair<WriteFVarBlendY,[ICXPort015], 2, [2], 2, 7>; 346defm : ICXWriteResPair<WriteFVarBlendZ,[ICXPort015], 2, [2], 2, 7>; 347 348// FMA Scheduling helper class. 349// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 350 351// Vector integer operations. 352defm : X86WriteRes<WriteVecLoad, [ICXPort23], 5, [1], 1>; 353defm : X86WriteRes<WriteVecLoadX, [ICXPort23], 6, [1], 1>; 354defm : X86WriteRes<WriteVecLoadY, [ICXPort23], 7, [1], 1>; 355defm : X86WriteRes<WriteVecLoadNT, [ICXPort23], 6, [1], 1>; 356defm : X86WriteRes<WriteVecLoadNTY, [ICXPort23], 7, [1], 1>; 357defm : X86WriteRes<WriteVecMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 358defm : X86WriteRes<WriteVecMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 359defm : X86WriteRes<WriteVecStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 360defm : X86WriteRes<WriteVecStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 361defm : X86WriteRes<WriteVecStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 362defm : X86WriteRes<WriteVecStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 363defm : X86WriteRes<WriteVecStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 364defm : X86WriteRes<WriteVecMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 365defm : X86WriteRes<WriteVecMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 366defm : X86WriteRes<WriteVecMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 367defm : X86WriteRes<WriteVecMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 368defm : X86WriteRes<WriteVecMove, [ICXPort05], 1, [1], 1>; 369defm : X86WriteRes<WriteVecMoveX, [ICXPort015], 1, [1], 1>; 370defm : X86WriteRes<WriteVecMoveY, [ICXPort015], 1, [1], 1>; 371defm : X86WriteRes<WriteVecMoveZ, [ICXPort05], 1, [1], 1>; 372defm : X86WriteRes<WriteVecMoveToGpr, [ICXPort0], 2, [1], 1>; 373defm : X86WriteRes<WriteVecMoveFromGpr, [ICXPort5], 1, [1], 1>; 374 375defm : ICXWriteResPair<WriteVecALU, [ICXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 376defm : ICXWriteResPair<WriteVecALUX, [ICXPort01], 1, [1], 1, 6>; 377defm : ICXWriteResPair<WriteVecALUY, [ICXPort01], 1, [1], 1, 7>; 378defm : ICXWriteResPair<WriteVecALUZ, [ICXPort0], 1, [1], 1, 7>; 379defm : ICXWriteResPair<WriteVecLogic, [ICXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 380defm : ICXWriteResPair<WriteVecLogicX,[ICXPort015], 1, [1], 1, 6>; 381defm : ICXWriteResPair<WriteVecLogicY,[ICXPort015], 1, [1], 1, 7>; 382defm : ICXWriteResPair<WriteVecLogicZ,[ICXPort05], 1, [1], 1, 7>; 383defm : ICXWriteResPair<WriteVecTest, [ICXPort0,ICXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 384defm : ICXWriteResPair<WriteVecTestY, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 385defm : ICXWriteResPair<WriteVecTestZ, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 386defm : ICXWriteResPair<WriteVecIMul, [ICXPort0], 5, [1], 1, 5>; // Vector integer multiply. 387defm : ICXWriteResPair<WriteVecIMulX, [ICXPort01], 5, [1], 1, 6>; 388defm : ICXWriteResPair<WriteVecIMulY, [ICXPort01], 5, [1], 1, 7>; 389defm : ICXWriteResPair<WriteVecIMulZ, [ICXPort05], 5, [1], 1, 7>; 390defm : ICXWriteResPair<WritePMULLD, [ICXPort01], 10, [2], 2, 6>; // Vector PMULLD. 391defm : ICXWriteResPair<WritePMULLDY, [ICXPort01], 10, [2], 2, 7>; 392defm : ICXWriteResPair<WritePMULLDZ, [ICXPort05], 10, [2], 2, 7>; 393defm : ICXWriteResPair<WriteShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector shuffles. 394defm : ICXWriteResPair<WriteShuffleX, [ICXPort15], 1, [1], 1, 6>; 395defm : ICXWriteResPair<WriteShuffleY, [ICXPort15], 1, [1], 1, 7>; 396defm : ICXWriteResPair<WriteShuffleZ, [ICXPort5], 1, [1], 1, 7>; 397defm : ICXWriteResPair<WriteVarShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector variable shuffles. 398defm : ICXWriteResPair<WriteVarShuffleX, [ICXPort15], 1, [1], 1, 6>; 399defm : ICXWriteResPair<WriteVarShuffleY, [ICXPort15], 1, [1], 1, 7>; 400defm : ICXWriteResPair<WriteVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 401defm : ICXWriteResPair<WriteBlend, [ICXPort5], 1, [1], 1, 6>; // Vector blends. 402defm : ICXWriteResPair<WriteBlendY,[ICXPort5], 1, [1], 1, 7>; 403defm : ICXWriteResPair<WriteBlendZ,[ICXPort5], 1, [1], 1, 7>; 404defm : ICXWriteResPair<WriteVarBlend, [ICXPort015], 2, [2], 2, 6>; // Vector variable blends. 405defm : ICXWriteResPair<WriteVarBlendY,[ICXPort015], 2, [2], 2, 6>; 406defm : ICXWriteResPair<WriteVarBlendZ,[ICXPort05], 2, [1], 1, 6>; 407defm : ICXWriteResPair<WriteMPSAD, [ICXPort5], 4, [2], 2, 6>; // Vector MPSAD. 408defm : ICXWriteResPair<WriteMPSADY, [ICXPort5], 4, [2], 2, 7>; 409defm : ICXWriteResPair<WriteMPSADZ, [ICXPort5], 4, [2], 2, 7>; 410defm : ICXWriteResPair<WritePSADBW, [ICXPort5], 3, [1], 1, 5>; // Vector PSADBW. 411defm : ICXWriteResPair<WritePSADBWX, [ICXPort5], 3, [1], 1, 6>; 412defm : ICXWriteResPair<WritePSADBWY, [ICXPort5], 3, [1], 1, 7>; 413defm : ICXWriteResPair<WritePSADBWZ, [ICXPort5], 3, [1], 1, 7>; 414defm : ICXWriteResPair<WritePHMINPOS, [ICXPort0], 4, [1], 1, 6>; // Vector PHMINPOS. 415 416// Vector integer shifts. 417defm : ICXWriteResPair<WriteVecShift, [ICXPort0], 1, [1], 1, 5>; 418defm : X86WriteRes<WriteVecShiftX, [ICXPort5,ICXPort01], 2, [1,1], 2>; 419defm : X86WriteRes<WriteVecShiftY, [ICXPort5,ICXPort01], 4, [1,1], 2>; 420defm : X86WriteRes<WriteVecShiftZ, [ICXPort5,ICXPort0], 4, [1,1], 2>; 421defm : X86WriteRes<WriteVecShiftXLd, [ICXPort01,ICXPort23], 7, [1,1], 2>; 422defm : X86WriteRes<WriteVecShiftYLd, [ICXPort01,ICXPort23], 8, [1,1], 2>; 423defm : X86WriteRes<WriteVecShiftZLd, [ICXPort0,ICXPort23], 8, [1,1], 2>; 424 425defm : ICXWriteResPair<WriteVecShiftImm, [ICXPort0], 1, [1], 1, 5>; 426defm : ICXWriteResPair<WriteVecShiftImmX, [ICXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts. 427defm : ICXWriteResPair<WriteVecShiftImmY, [ICXPort01], 1, [1], 1, 7>; 428defm : ICXWriteResPair<WriteVecShiftImmZ, [ICXPort0], 1, [1], 1, 7>; 429defm : ICXWriteResPair<WriteVarVecShift, [ICXPort01], 1, [1], 1, 6>; // Variable vector shifts. 430defm : ICXWriteResPair<WriteVarVecShiftY, [ICXPort01], 1, [1], 1, 7>; 431defm : ICXWriteResPair<WriteVarVecShiftZ, [ICXPort0], 1, [1], 1, 7>; 432 433// Vector insert/extract operations. 434def : WriteRes<WriteVecInsert, [ICXPort5]> { 435 let Latency = 2; 436 let NumMicroOps = 2; 437 let ResourceCycles = [2]; 438} 439def : WriteRes<WriteVecInsertLd, [ICXPort5,ICXPort23]> { 440 let Latency = 6; 441 let NumMicroOps = 2; 442} 443def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 444 445def : WriteRes<WriteVecExtract, [ICXPort0,ICXPort5]> { 446 let Latency = 3; 447 let NumMicroOps = 2; 448} 449def : WriteRes<WriteVecExtractSt, [ICXPort4,ICXPort5,ICXPort237]> { 450 let Latency = 2; 451 let NumMicroOps = 3; 452} 453 454// Conversion between integer and float. 455defm : ICXWriteResPair<WriteCvtSS2I, [ICXPort01], 6, [2], 2>; // Needs more work: DD vs DQ. 456defm : ICXWriteResPair<WriteCvtPS2I, [ICXPort01], 3>; 457defm : ICXWriteResPair<WriteCvtPS2IY, [ICXPort01], 3>; 458defm : ICXWriteResPair<WriteCvtPS2IZ, [ICXPort05], 3>; 459defm : ICXWriteResPair<WriteCvtSD2I, [ICXPort01], 6, [2], 2>; 460defm : ICXWriteResPair<WriteCvtPD2I, [ICXPort01], 3>; 461defm : ICXWriteResPair<WriteCvtPD2IY, [ICXPort01], 3>; 462defm : ICXWriteResPair<WriteCvtPD2IZ, [ICXPort05], 3>; 463 464defm : ICXWriteResPair<WriteCvtI2SS, [ICXPort1], 4>; 465defm : ICXWriteResPair<WriteCvtI2PS, [ICXPort01], 4>; 466defm : ICXWriteResPair<WriteCvtI2PSY, [ICXPort01], 4>; 467defm : ICXWriteResPair<WriteCvtI2PSZ, [ICXPort05], 4>; // Needs more work: DD vs DQ. 468defm : ICXWriteResPair<WriteCvtI2SD, [ICXPort1], 4>; 469defm : ICXWriteResPair<WriteCvtI2PD, [ICXPort01], 4>; 470defm : ICXWriteResPair<WriteCvtI2PDY, [ICXPort01], 4>; 471defm : ICXWriteResPair<WriteCvtI2PDZ, [ICXPort05], 4>; 472 473defm : ICXWriteResPair<WriteCvtSS2SD, [ICXPort1], 3>; 474defm : ICXWriteResPair<WriteCvtPS2PD, [ICXPort1], 3>; 475defm : ICXWriteResPair<WriteCvtPS2PDY, [ICXPort5,ICXPort01], 3, [1,1], 2>; 476defm : ICXWriteResPair<WriteCvtPS2PDZ, [ICXPort05], 3, [2], 2>; 477defm : ICXWriteResPair<WriteCvtSD2SS, [ICXPort1], 3>; 478defm : ICXWriteResPair<WriteCvtPD2PS, [ICXPort1], 3>; 479defm : ICXWriteResPair<WriteCvtPD2PSY, [ICXPort5,ICXPort01], 3, [1,1], 2>; 480defm : ICXWriteResPair<WriteCvtPD2PSZ, [ICXPort05], 3, [2], 2>; 481 482defm : X86WriteRes<WriteCvtPH2PS, [ICXPort5,ICXPort01], 5, [1,1], 2>; 483defm : X86WriteRes<WriteCvtPH2PSY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 484defm : X86WriteRes<WriteCvtPH2PSZ, [ICXPort5,ICXPort0], 7, [1,1], 2>; 485defm : X86WriteRes<WriteCvtPH2PSLd, [ICXPort23,ICXPort01], 9, [1,1], 2>; 486defm : X86WriteRes<WriteCvtPH2PSYLd, [ICXPort23,ICXPort01], 10, [1,1], 2>; 487defm : X86WriteRes<WriteCvtPH2PSZLd, [ICXPort23,ICXPort05], 10, [1,1], 2>; 488 489defm : X86WriteRes<WriteCvtPS2PH, [ICXPort5,ICXPort01], 5, [1,1], 2>; 490defm : X86WriteRes<WriteCvtPS2PHY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 491defm : X86WriteRes<WriteCvtPS2PHZ, [ICXPort5,ICXPort05], 7, [1,1], 2>; 492defm : X86WriteRes<WriteCvtPS2PHSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 6, [1,1,1,1], 4>; 493defm : X86WriteRes<WriteCvtPS2PHYSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 8, [1,1,1,1], 4>; 494defm : X86WriteRes<WriteCvtPS2PHZSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort05], 8, [1,1,1,1], 4>; 495 496// Strings instructions. 497 498// Packed Compare Implicit Length Strings, Return Mask 499def : WriteRes<WritePCmpIStrM, [ICXPort0]> { 500 let Latency = 10; 501 let NumMicroOps = 3; 502 let ResourceCycles = [3]; 503} 504def : WriteRes<WritePCmpIStrMLd, [ICXPort0, ICXPort23]> { 505 let Latency = 16; 506 let NumMicroOps = 4; 507 let ResourceCycles = [3,1]; 508} 509 510// Packed Compare Explicit Length Strings, Return Mask 511def : WriteRes<WritePCmpEStrM, [ICXPort0, ICXPort5, ICXPort015, ICXPort0156]> { 512 let Latency = 19; 513 let NumMicroOps = 9; 514 let ResourceCycles = [4,3,1,1]; 515} 516def : WriteRes<WritePCmpEStrMLd, [ICXPort0, ICXPort5, ICXPort23, ICXPort015, ICXPort0156]> { 517 let Latency = 25; 518 let NumMicroOps = 10; 519 let ResourceCycles = [4,3,1,1,1]; 520} 521 522// Packed Compare Implicit Length Strings, Return Index 523def : WriteRes<WritePCmpIStrI, [ICXPort0]> { 524 let Latency = 10; 525 let NumMicroOps = 3; 526 let ResourceCycles = [3]; 527} 528def : WriteRes<WritePCmpIStrILd, [ICXPort0, ICXPort23]> { 529 let Latency = 16; 530 let NumMicroOps = 4; 531 let ResourceCycles = [3,1]; 532} 533 534// Packed Compare Explicit Length Strings, Return Index 535def : WriteRes<WritePCmpEStrI, [ICXPort0,ICXPort5,ICXPort0156]> { 536 let Latency = 18; 537 let NumMicroOps = 8; 538 let ResourceCycles = [4,3,1]; 539} 540def : WriteRes<WritePCmpEStrILd, [ICXPort0, ICXPort5, ICXPort23, ICXPort0156]> { 541 let Latency = 24; 542 let NumMicroOps = 9; 543 let ResourceCycles = [4,3,1,1]; 544} 545 546// MOVMSK Instructions. 547def : WriteRes<WriteFMOVMSK, [ICXPort0]> { let Latency = 2; } 548def : WriteRes<WriteVecMOVMSK, [ICXPort0]> { let Latency = 2; } 549def : WriteRes<WriteVecMOVMSKY, [ICXPort0]> { let Latency = 2; } 550def : WriteRes<WriteMMXMOVMSK, [ICXPort0]> { let Latency = 2; } 551 552// AES instructions. 553def : WriteRes<WriteAESDecEnc, [ICXPort0]> { // Decryption, encryption. 554 let Latency = 4; 555 let NumMicroOps = 1; 556 let ResourceCycles = [1]; 557} 558def : WriteRes<WriteAESDecEncLd, [ICXPort0, ICXPort23]> { 559 let Latency = 10; 560 let NumMicroOps = 2; 561 let ResourceCycles = [1,1]; 562} 563 564def : WriteRes<WriteAESIMC, [ICXPort0]> { // InvMixColumn. 565 let Latency = 8; 566 let NumMicroOps = 2; 567 let ResourceCycles = [2]; 568} 569def : WriteRes<WriteAESIMCLd, [ICXPort0, ICXPort23]> { 570 let Latency = 14; 571 let NumMicroOps = 3; 572 let ResourceCycles = [2,1]; 573} 574 575def : WriteRes<WriteAESKeyGen, [ICXPort0,ICXPort5,ICXPort015]> { // Key Generation. 576 let Latency = 20; 577 let NumMicroOps = 11; 578 let ResourceCycles = [3,6,2]; 579} 580def : WriteRes<WriteAESKeyGenLd, [ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { 581 let Latency = 25; 582 let NumMicroOps = 11; 583 let ResourceCycles = [3,6,1,1]; 584} 585 586// Carry-less multiplication instructions. 587def : WriteRes<WriteCLMul, [ICXPort5]> { 588 let Latency = 6; 589 let NumMicroOps = 1; 590 let ResourceCycles = [1]; 591} 592def : WriteRes<WriteCLMulLd, [ICXPort5, ICXPort23]> { 593 let Latency = 12; 594 let NumMicroOps = 2; 595 let ResourceCycles = [1,1]; 596} 597 598// Catch-all for expensive system instructions. 599def : WriteRes<WriteSystem, [ICXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 600 601// AVX2. 602defm : ICXWriteResPair<WriteFShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 603defm : ICXWriteResPair<WriteFVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 604defm : ICXWriteResPair<WriteShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 605defm : ICXWriteResPair<WriteVPMOV256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 606defm : ICXWriteResPair<WriteVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 607 608// Old microcoded instructions that nobody use. 609def : WriteRes<WriteMicrocoded, [ICXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 610 611// Fence instructions. 612def : WriteRes<WriteFence, [ICXPort23, ICXPort4]>; 613 614// Load/store MXCSR. 615def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 616def : WriteRes<WriteSTMXCSR, [ICXPort4,ICXPort5,ICXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 617 618// Nop, not very useful expect it provides a model for nops! 619def : WriteRes<WriteNop, []>; 620 621//////////////////////////////////////////////////////////////////////////////// 622// Horizontal add/sub instructions. 623//////////////////////////////////////////////////////////////////////////////// 624 625defm : ICXWriteResPair<WriteFHAdd, [ICXPort5,ICXPort015], 6, [2,1], 3, 6>; 626defm : ICXWriteResPair<WriteFHAddY, [ICXPort5,ICXPort015], 6, [2,1], 3, 7>; 627defm : ICXWriteResPair<WritePHAdd, [ICXPort5,ICXPort05], 3, [2,1], 3, 5>; 628defm : ICXWriteResPair<WritePHAddX, [ICXPort5,ICXPort015], 3, [2,1], 3, 6>; 629defm : ICXWriteResPair<WritePHAddY, [ICXPort5,ICXPort015], 3, [2,1], 3, 7>; 630 631// Remaining instrs. 632 633def ICXWriteResGroup1 : SchedWriteRes<[ICXPort0]> { 634 let Latency = 1; 635 let NumMicroOps = 1; 636 let ResourceCycles = [1]; 637} 638def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", 639 "KANDN(B|D|Q|W)rr", 640 "KMOV(B|D|Q|W)kk", 641 "KNOT(B|D|Q|W)rr", 642 "KOR(B|D|Q|W)rr", 643 "KXNOR(B|D|Q|W)rr", 644 "KXOR(B|D|Q|W)rr", 645 "KSET0(B|D|Q|W)", // Same as KXOR 646 "KSET1(B|D|Q|W)", // Same as KXNOR 647 "MMX_PADDS(B|W)rr", 648 "MMX_PADDUS(B|W)rr", 649 "MMX_PAVG(B|W)rr", 650 "MMX_PCMPEQ(B|D|W)rr", 651 "MMX_PCMPGT(B|D|W)rr", 652 "MMX_P(MAX|MIN)SWrr", 653 "MMX_P(MAX|MIN)UBrr", 654 "MMX_PSUBS(B|W)rr", 655 "MMX_PSUBUS(B|W)rr", 656 "VPMOVB2M(Z|Z128|Z256)rr", 657 "VPMOVD2M(Z|Z128|Z256)rr", 658 "VPMOVQ2M(Z|Z128|Z256)rr", 659 "VPMOVW2M(Z|Z128|Z256)rr")>; 660 661def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> { 662 let Latency = 1; 663 let NumMicroOps = 1; 664 let ResourceCycles = [1]; 665} 666def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r", 667 "KMOV(B|D|Q|W)kr", 668 "UCOM_F(P?)r", 669 "VPBROADCAST(D|Q)rr", 670 "(V?)INSERTPS(Z?)rr", 671 "(V?)MOV(HL|LH)PS(Z?)rr", 672 "(V?)MOVDDUP(Y|Z|Z128|Z256)?rr", 673 "(V?)PALIGNR(Y|Z|Z128|Z256)?rri", 674 "(V?)PERMIL(PD|PS)(Y|Z|Z128|Z256)?ri", 675 "(V?)PERMIL(PD|PS)(Y|Z|Z128|Z256)?rr", 676 "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z128|Z256)?rr", 677 "(V?)UNPCK(L|H)(PD|PS)(Y|Z|Z128|Z256)?rr")>; 678 679def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> { 680 let Latency = 1; 681 let NumMicroOps = 1; 682 let ResourceCycles = [1]; 683} 684def: InstRW<[ICXWriteResGroup4], (instregex "JMP(16|32|64)r")>; 685 686def ICXWriteResGroup6 : SchedWriteRes<[ICXPort05]> { 687 let Latency = 1; 688 let NumMicroOps = 1; 689 let ResourceCycles = [1]; 690} 691def: InstRW<[ICXWriteResGroup6], (instrs FINCSTP, FNOP)>; 692 693def ICXWriteResGroup7 : SchedWriteRes<[ICXPort06]> { 694 let Latency = 1; 695 let NumMicroOps = 1; 696 let ResourceCycles = [1]; 697} 698def: InstRW<[ICXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 699 700def ICXWriteResGroup8 : SchedWriteRes<[ICXPort15]> { 701 let Latency = 1; 702 let NumMicroOps = 1; 703 let ResourceCycles = [1]; 704} 705def: InstRW<[ICXWriteResGroup8], (instregex "ANDN(32|64)rr")>; 706 707def ICXWriteResGroup9 : SchedWriteRes<[ICXPort015]> { 708 let Latency = 1; 709 let NumMicroOps = 1; 710 let ResourceCycles = [1]; 711} 712def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", 713 "VBLENDMPS(Z128|Z256)rr", 714 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", 715 "(V?)PADD(B|D|Q|W)rr", 716 "(V?)MOV(SD|SS)(Z?)rr", 717 "VPBLENDD(Y?)rri", 718 "VPBLENDMB(Z128|Z256)rr", 719 "VPBLENDMD(Z128|Z256)rr", 720 "VPBLENDMQ(Z128|Z256)rr", 721 "VPBLENDMW(Z128|Z256)rr", 722 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", 723 "VPTERNLOGD(Z|Z128|Z256)rri", 724 "VPTERNLOGQ(Z|Z128|Z256)rri")>; 725 726def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> { 727 let Latency = 1; 728 let NumMicroOps = 1; 729 let ResourceCycles = [1]; 730} 731def: InstRW<[ICXWriteResGroup10], (instrs CBW, CWDE, CDQE, 732 CMC, STC, 733 SGDT64m, 734 SIDT64m, 735 SMSW16m, 736 STRm, 737 SYSCALL)>; 738 739def ICXWriteResGroup11 : SchedWriteRes<[ICXPort4,ICXPort237]> { 740 let Latency = 1; 741 let NumMicroOps = 2; 742 let ResourceCycles = [1,1]; 743} 744def: InstRW<[ICXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 745def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", 746 "ST_FP(32|64|80)m")>; 747 748def ICXWriteResGroup13 : SchedWriteRes<[ICXPort5]> { 749 let Latency = 2; 750 let NumMicroOps = 2; 751 let ResourceCycles = [2]; 752} 753def: InstRW<[ICXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 754 755def ICXWriteResGroup14 : SchedWriteRes<[ICXPort05]> { 756 let Latency = 2; 757 let NumMicroOps = 2; 758 let ResourceCycles = [2]; 759} 760def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP, 761 MMX_MOVDQ2Qrr)>; 762 763def ICXWriteResGroup17 : SchedWriteRes<[ICXPort0156]> { 764 let Latency = 2; 765 let NumMicroOps = 2; 766 let ResourceCycles = [2]; 767} 768def: InstRW<[ICXWriteResGroup17], (instrs LFENCE, 769 WAIT, 770 XGETBV)>; 771 772def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 773 let Latency = 2; 774 let NumMicroOps = 2; 775 let ResourceCycles = [1,1]; 776} 777def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>; 778 779def ICXWriteResGroup21 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 780 let Latency = 2; 781 let NumMicroOps = 2; 782 let ResourceCycles = [1,1]; 783} 784def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>; 785 786def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 787 let Latency = 2; 788 let NumMicroOps = 2; 789 let ResourceCycles = [1,1]; 790} 791def: InstRW<[ICXWriteResGroup23], (instrs CWD, 792 JCXZ, JECXZ, JRCXZ, 793 ADC8i8, SBB8i8, 794 ADC16i16, SBB16i16, 795 ADC32i32, SBB32i32, 796 ADC64i32, SBB64i32)>; 797 798def ICXWriteResGroup25 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237]> { 799 let Latency = 2; 800 let NumMicroOps = 3; 801 let ResourceCycles = [1,1,1]; 802} 803def: InstRW<[ICXWriteResGroup25], (instrs FNSTCW16m)>; 804 805def ICXWriteResGroup27 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 806 let Latency = 2; 807 let NumMicroOps = 3; 808 let ResourceCycles = [1,1,1]; 809} 810def: InstRW<[ICXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 811 812def ICXWriteResGroup28 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 813 let Latency = 2; 814 let NumMicroOps = 3; 815 let ResourceCycles = [1,1,1]; 816} 817def: InstRW<[ICXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 818 STOSB, STOSL, STOSQ, STOSW)>; 819def: InstRW<[ICXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 820 821def ICXWriteResGroup29 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 822 let Latency = 2; 823 let NumMicroOps = 5; 824 let ResourceCycles = [2,2,1]; 825} 826def: InstRW<[ICXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; 827 828def ICXWriteResGroup30 : SchedWriteRes<[ICXPort0]> { 829 let Latency = 3; 830 let NumMicroOps = 1; 831 let ResourceCycles = [1]; 832} 833def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", 834 "KORTEST(B|D|Q|W)rr", 835 "KTEST(B|D|Q|W)rr")>; 836 837def ICXWriteResGroup31 : SchedWriteRes<[ICXPort1]> { 838 let Latency = 3; 839 let NumMicroOps = 1; 840 let ResourceCycles = [1]; 841} 842def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr", 843 "PEXT(32|64)rr")>; 844 845def ICXWriteResGroup32 : SchedWriteRes<[ICXPort5]> { 846 let Latency = 3; 847 let NumMicroOps = 1; 848 let ResourceCycles = [1]; 849} 850def: InstRW<[ICXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined. 851def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 852 "VALIGND(Z|Z128|Z256)rri", 853 "VALIGNQ(Z|Z128|Z256)rri", 854 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. 855 "VPBROADCAST(B|W)rr", 856 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>; 857 858def ICXWriteResGroup33 : SchedWriteRes<[ICXPort5]> { 859 let Latency = 4; 860 let NumMicroOps = 1; 861 let ResourceCycles = [1]; 862} 863def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr", 864 "KSHIFTL(B|D|Q|W)ri", 865 "KSHIFTR(B|D|Q|W)ri", 866 "KUNPCK(BW|DQ|WD)rr", 867 "VCMPPD(Z|Z128|Z256)rri", 868 "VCMPPS(Z|Z128|Z256)rri", 869 "VCMP(SD|SS)Zrr", 870 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", 871 "VFPCLASS(SD|SS)Zrr", 872 "VPCMPB(Z|Z128|Z256)rri", 873 "VPCMPD(Z|Z128|Z256)rri", 874 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", 875 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", 876 "VPCMPQ(Z|Z128|Z256)rri", 877 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", 878 "VPCMPW(Z|Z128|Z256)rri", 879 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; 880 881def ICXWriteResGroup34 : SchedWriteRes<[ICXPort0,ICXPort0156]> { 882 let Latency = 3; 883 let NumMicroOps = 2; 884 let ResourceCycles = [1,1]; 885} 886def: InstRW<[ICXWriteResGroup34], (instrs FNSTSW16r)>; 887 888def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> { 889 let Latency = 3; 890 let NumMicroOps = 3; 891 let ResourceCycles = [1,2]; 892} 893def: InstRW<[ICXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; 894 895def ICXWriteResGroup38 : SchedWriteRes<[ICXPort5,ICXPort01]> { 896 let Latency = 3; 897 let NumMicroOps = 3; 898 let ResourceCycles = [2,1]; 899} 900def: InstRW<[ICXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; 901 902def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 903 let Latency = 3; 904 let NumMicroOps = 3; 905 let ResourceCycles = [2,1]; 906} 907def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWrr, 908 MMX_PACKSSWBrr, 909 MMX_PACKUSWBrr)>; 910 911def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 912 let Latency = 3; 913 let NumMicroOps = 3; 914 let ResourceCycles = [1,2]; 915} 916def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>; 917 918def ICXWriteResGroup43 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 919 let Latency = 3; 920 let NumMicroOps = 3; 921 let ResourceCycles = [1,2]; 922} 923def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>; 924 925def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 926 let Latency = 2; 927 let NumMicroOps = 3; 928 let ResourceCycles = [1,2]; 929} 930def: InstRW<[ICXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 931 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 932 933def ICXWriteResGroup44b : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 934 let Latency = 5; 935 let NumMicroOps = 7; 936 let ResourceCycles = [2,3,2]; 937} 938def: InstRW<[ICXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 939 940def ICXWriteResGroup44c : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 941 let Latency = 6; 942 let NumMicroOps = 7; 943 let ResourceCycles = [2,3,2]; 944} 945def: InstRW<[ICXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 946 947def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237]> { 948 let Latency = 3; 949 let NumMicroOps = 3; 950 let ResourceCycles = [1,1,1]; 951} 952def: InstRW<[ICXWriteResGroup45], (instrs FNSTSWm)>; 953 954def ICXWriteResGroup47 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237,ICXPort0156]> { 955 let Latency = 3; 956 let NumMicroOps = 4; 957 let ResourceCycles = [1,1,1,1]; 958} 959def: InstRW<[ICXWriteResGroup47], (instregex "CALL(16|32|64)r")>; 960 961def ICXWriteResGroup48 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06,ICXPort0156]> { 962 let Latency = 3; 963 let NumMicroOps = 4; 964 let ResourceCycles = [1,1,1,1]; 965} 966def: InstRW<[ICXWriteResGroup48], (instrs CALL64pcrel32)>; 967 968def ICXWriteResGroup49 : SchedWriteRes<[ICXPort0]> { 969 let Latency = 4; 970 let NumMicroOps = 1; 971 let ResourceCycles = [1]; 972} 973def: InstRW<[ICXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 974 975def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> { 976 let Latency = 4; 977 let NumMicroOps = 1; 978 let ResourceCycles = [1]; 979} 980def: InstRW<[ICXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", 981 "(V?)CVTDQ2PSrr", 982 "VCVTPD2QQ(Z128|Z256)rr", 983 "VCVTPD2UQQ(Z128|Z256)rr", 984 "VCVTPS2DQ(Y|Z128|Z256)rr", 985 "(V?)CVTPS2DQrr", 986 "VCVTPS2UDQ(Z128|Z256)rr", 987 "VCVTQQ2PD(Z128|Z256)rr", 988 "VCVTTPD2QQ(Z128|Z256)rr", 989 "VCVTTPD2UQQ(Z128|Z256)rr", 990 "VCVTTPS2DQ(Z128|Z256)rr", 991 "(V?)CVTTPS2DQrr", 992 "VCVTTPS2UDQ(Z128|Z256)rr", 993 "VCVTUDQ2PS(Z128|Z256)rr", 994 "VCVTUQQ2PD(Z128|Z256)rr")>; 995 996def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> { 997 let Latency = 4; 998 let NumMicroOps = 1; 999 let ResourceCycles = [1]; 1000} 1001def: InstRW<[ICXWriteResGroup50z], (instrs VCVTDQ2PSZrr, 1002 VCVTPD2QQZrr, 1003 VCVTPD2UQQZrr, 1004 VCVTPS2DQZrr, 1005 VCVTPS2UDQZrr, 1006 VCVTQQ2PDZrr, 1007 VCVTTPD2QQZrr, 1008 VCVTTPD2UQQZrr, 1009 VCVTTPS2DQZrr, 1010 VCVTTPS2UDQZrr, 1011 VCVTUDQ2PSZrr, 1012 VCVTUQQ2PDZrr)>; 1013 1014def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> { 1015 let Latency = 4; 1016 let NumMicroOps = 2; 1017 let ResourceCycles = [2]; 1018} 1019def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", 1020 "VEXPANDPS(Z|Z128|Z256)rr", 1021 "VPEXPANDD(Z|Z128|Z256)rr", 1022 "VPEXPANDQ(Z|Z128|Z256)rr", 1023 "VPMOVDB(Z|Z128|Z256)rr", 1024 "VPMOVDW(Z|Z128|Z256)rr", 1025 "VPMOVQB(Z|Z128|Z256)rr", 1026 "VPMOVQW(Z|Z128|Z256)rr", 1027 "VPMOVSDB(Z|Z128|Z256)rr", 1028 "VPMOVSDW(Z|Z128|Z256)rr", 1029 "VPMOVSQB(Z|Z128|Z256)rr", 1030 "VPMOVSQD(Z|Z128|Z256)rr", 1031 "VPMOVSQW(Z|Z128|Z256)rr", 1032 "VPMOVSWB(Z|Z128|Z256)rr", 1033 "VPMOVUSDB(Z|Z128|Z256)rr", 1034 "VPMOVUSDW(Z|Z128|Z256)rr", 1035 "VPMOVUSQB(Z|Z128|Z256)rr", 1036 "VPMOVUSQD(Z|Z128|Z256)rr", 1037 "VPMOVUSWB(Z|Z128|Z256)rr", 1038 "VPMOVWB(Z|Z128|Z256)rr")>; 1039 1040def ICXWriteResGroup54 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1041 let Latency = 4; 1042 let NumMicroOps = 3; 1043 let ResourceCycles = [1,1,1]; 1044} 1045def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", 1046 "IST_F(16|32)m", 1047 "VPMOVQD(Z|Z128|Z256)mr(b?)")>; 1048 1049def ICXWriteResGroup55 : SchedWriteRes<[ICXPort0156]> { 1050 let Latency = 4; 1051 let NumMicroOps = 4; 1052 let ResourceCycles = [4]; 1053} 1054def: InstRW<[ICXWriteResGroup55], (instrs FNCLEX)>; 1055 1056def ICXWriteResGroup56 : SchedWriteRes<[]> { 1057 let Latency = 0; 1058 let NumMicroOps = 4; 1059 let ResourceCycles = []; 1060} 1061def: InstRW<[ICXWriteResGroup56], (instrs VZEROUPPER)>; 1062 1063def ICXWriteResGroup57 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort0156]> { 1064 let Latency = 4; 1065 let NumMicroOps = 4; 1066 let ResourceCycles = [1,1,2]; 1067} 1068def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 1069 1070def ICXWriteResGroup58 : SchedWriteRes<[ICXPort23]> { 1071 let Latency = 5; 1072 let NumMicroOps = 1; 1073 let ResourceCycles = [1]; 1074} 1075def: InstRW<[ICXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 1076 "MOVZX(16|32|64)rm(8|16)", 1077 "(V?)MOVDDUPrm")>; // TODO: Should this be ICXWriteResGroup71? 1078 1079def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1080 let Latency = 5; 1081 let NumMicroOps = 2; 1082 let ResourceCycles = [1,1]; 1083} 1084def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr", 1085 "MMX_CVT(T?)PS2PIrr", 1086 "VCVTDQ2PDZ128rr", 1087 "VCVTPD2DQZ128rr", 1088 "(V?)CVT(T?)PD2DQrr", 1089 "VCVTPD2PSZ128rr", 1090 "(V?)CVTPD2PSrr", 1091 "VCVTPD2UDQZ128rr", 1092 "VCVTPS2PDZ128rr", 1093 "(V?)CVTPS2PDrr", 1094 "VCVTPS2QQZ128rr", 1095 "VCVTPS2UQQZ128rr", 1096 "VCVTQQ2PSZ128rr", 1097 "(V?)CVTSD2SS(Z?)rr", 1098 "(V?)CVTSI(64)?2SDrr", 1099 "VCVTSI2SSZrr", 1100 "(V?)CVTSI2SSrr", 1101 "VCVTSI(64)?2SDZrr", 1102 "VCVTSS2SDZrr", 1103 "(V?)CVTSS2SDrr", 1104 "VCVTTPD2DQZ128rr", 1105 "VCVTTPD2UDQZ128rr", 1106 "VCVTTPS2QQZ128rr", 1107 "VCVTTPS2UQQZ128rr", 1108 "VCVTUDQ2PDZ128rr", 1109 "VCVTUQQ2PSZ128rr", 1110 "VCVTUSI2SSZrr", 1111 "VCVTUSI(64)?2SDZrr")>; 1112 1113def ICXWriteResGroup62 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1114 let Latency = 5; 1115 let NumMicroOps = 3; 1116 let ResourceCycles = [2,1]; 1117} 1118def: InstRW<[ICXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; 1119 1120def ICXWriteResGroup63 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06]> { 1121 let Latency = 5; 1122 let NumMicroOps = 3; 1123 let ResourceCycles = [1,1,1]; 1124} 1125def: InstRW<[ICXWriteResGroup63], (instregex "STR(16|32|64)r")>; 1126 1127def ICXWriteResGroup65 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort015]> { 1128 let Latency = 5; 1129 let NumMicroOps = 3; 1130 let ResourceCycles = [1,1,1]; 1131} 1132def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", 1133 "VCVTPS2PHZ256mr(b?)", 1134 "VCVTPS2PHZmr(b?)")>; 1135 1136def ICXWriteResGroup66 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1137 let Latency = 5; 1138 let NumMicroOps = 4; 1139 let ResourceCycles = [1,2,1]; 1140} 1141def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", 1142 "VPMOVDW(Z|Z128|Z256)mr(b?)", 1143 "VPMOVQB(Z|Z128|Z256)mr(b?)", 1144 "VPMOVQW(Z|Z128|Z256)mr(b?)", 1145 "VPMOVSDB(Z|Z128|Z256)mr(b?)", 1146 "VPMOVSDW(Z|Z128|Z256)mr(b?)", 1147 "VPMOVSQB(Z|Z128|Z256)mr(b?)", 1148 "VPMOVSQD(Z|Z128|Z256)mr(b?)", 1149 "VPMOVSQW(Z|Z128|Z256)mr(b?)", 1150 "VPMOVSWB(Z|Z128|Z256)mr(b?)", 1151 "VPMOVUSDB(Z|Z128|Z256)mr(b?)", 1152 "VPMOVUSDW(Z|Z128|Z256)mr(b?)", 1153 "VPMOVUSQB(Z|Z128|Z256)mr(b?)", 1154 "VPMOVUSQD(Z|Z128|Z256)mr(b?)", 1155 "VPMOVUSQW(Z|Z128|Z256)mr(b?)", 1156 "VPMOVUSWB(Z|Z128|Z256)mr(b?)", 1157 "VPMOVWB(Z|Z128|Z256)mr(b?)")>; 1158 1159def ICXWriteResGroup67 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1160 let Latency = 5; 1161 let NumMicroOps = 5; 1162 let ResourceCycles = [1,4]; 1163} 1164def: InstRW<[ICXWriteResGroup67], (instrs XSETBV)>; 1165 1166def ICXWriteResGroup69 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 1167 let Latency = 5; 1168 let NumMicroOps = 6; 1169 let ResourceCycles = [1,1,4]; 1170} 1171def: InstRW<[ICXWriteResGroup69], (instregex "PUSHF(16|64)")>; 1172 1173def ICXWriteResGroup71 : SchedWriteRes<[ICXPort23]> { 1174 let Latency = 6; 1175 let NumMicroOps = 1; 1176 let ResourceCycles = [1]; 1177} 1178def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm, 1179 VPBROADCASTDrm, 1180 VPBROADCASTQrm, 1181 VMOVSHDUPrm, 1182 VMOVSLDUPrm, 1183 MOVSHDUPrm, 1184 MOVSLDUPrm)>; 1185 1186def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> { 1187 let Latency = 6; 1188 let NumMicroOps = 2; 1189 let ResourceCycles = [2]; 1190} 1191def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>; 1192def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", 1193 "VCOMPRESSPS(Z|Z128|Z256)rr", 1194 "VPCOMPRESSD(Z|Z128|Z256)rr", 1195 "VPCOMPRESSQ(Z|Z128|Z256)rr", 1196 "VPERMW(Z|Z128|Z256)rr")>; 1197 1198def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1199 let Latency = 6; 1200 let NumMicroOps = 2; 1201 let ResourceCycles = [1,1]; 1202} 1203def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm, 1204 MMX_PADDSWrm, 1205 MMX_PADDUSBrm, 1206 MMX_PADDUSWrm, 1207 MMX_PAVGBrm, 1208 MMX_PAVGWrm, 1209 MMX_PCMPEQBrm, 1210 MMX_PCMPEQDrm, 1211 MMX_PCMPEQWrm, 1212 MMX_PCMPGTBrm, 1213 MMX_PCMPGTDrm, 1214 MMX_PCMPGTWrm, 1215 MMX_PMAXSWrm, 1216 MMX_PMAXUBrm, 1217 MMX_PMINSWrm, 1218 MMX_PMINUBrm, 1219 MMX_PSUBSBrm, 1220 MMX_PSUBSWrm, 1221 MMX_PSUBUSBrm, 1222 MMX_PSUBUSWrm)>; 1223 1224def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> { 1225 let Latency = 6; 1226 let NumMicroOps = 2; 1227 let ResourceCycles = [1,1]; 1228} 1229def: InstRW<[ICXWriteResGroup76], (instrs FARJMP64m)>; 1230def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>; 1231 1232def ICXWriteResGroup79 : SchedWriteRes<[ICXPort23,ICXPort15]> { 1233 let Latency = 6; 1234 let NumMicroOps = 2; 1235 let ResourceCycles = [1,1]; 1236} 1237def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm", 1238 "MOVBE(16|32|64)rm")>; 1239 1240def ICXWriteResGroup80 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1241 let Latency = 6; 1242 let NumMicroOps = 2; 1243 let ResourceCycles = [1,1]; 1244} 1245def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; 1246def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; 1247 1248def ICXWriteResGroup81 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1249 let Latency = 6; 1250 let NumMicroOps = 2; 1251 let ResourceCycles = [1,1]; 1252} 1253def: InstRW<[ICXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; 1254def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; 1255 1256def ICXWriteResGroup82 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1257 let Latency = 6; 1258 let NumMicroOps = 3; 1259 let ResourceCycles = [2,1]; 1260} 1261def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", 1262 "VCVTSI642SSZrr", 1263 "VCVTUSI642SSZrr")>; 1264 1265def ICXWriteResGroup84 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06,ICXPort0156]> { 1266 let Latency = 6; 1267 let NumMicroOps = 4; 1268 let ResourceCycles = [1,1,1,1]; 1269} 1270def: InstRW<[ICXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; 1271 1272def ICXWriteResGroup86 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1273 let Latency = 6; 1274 let NumMicroOps = 4; 1275 let ResourceCycles = [1,1,1,1]; 1276} 1277def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", 1278 "SHL(8|16|32|64)m(1|i)", 1279 "SHR(8|16|32|64)m(1|i)")>; 1280 1281def ICXWriteResGroup87 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1282 let Latency = 6; 1283 let NumMicroOps = 4; 1284 let ResourceCycles = [1,1,1,1]; 1285} 1286def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm", 1287 "PUSH(16|32|64)rmm")>; 1288 1289def ICXWriteResGroup88 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 1290 let Latency = 6; 1291 let NumMicroOps = 6; 1292 let ResourceCycles = [1,5]; 1293} 1294def: InstRW<[ICXWriteResGroup88], (instrs STD)>; 1295 1296def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> { 1297 let Latency = 7; 1298 let NumMicroOps = 1; 1299 let ResourceCycles = [1]; 1300} 1301def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; 1302def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128, 1303 VBROADCASTI128, 1304 VBROADCASTSDYrm, 1305 VBROADCASTSSYrm, 1306 VMOVDDUPYrm, 1307 VMOVSHDUPYrm, 1308 VMOVSLDUPYrm, 1309 VPBROADCASTDYrm, 1310 VPBROADCASTQYrm)>; 1311 1312def ICXWriteResGroup90 : SchedWriteRes<[ICXPort01,ICXPort5]> { 1313 let Latency = 7; 1314 let NumMicroOps = 2; 1315 let ResourceCycles = [1,1]; 1316} 1317def: InstRW<[ICXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; 1318 1319def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1320 let Latency = 7; 1321 let NumMicroOps = 2; 1322 let ResourceCycles = [1,1]; 1323} 1324def: InstRW<[ICXWriteResGroup92], (instregex "VMOV(SD|SS)Zrm(b?)", 1325 "VPBROADCAST(B|W)(Z128)?rm", 1326 "(V?)INSERTPS(Z?)rm", 1327 "(V?)PALIGNR(Z128)?rmi", 1328 "(V?)PERMIL(PD|PS)(Z128)?m(b?)i", 1329 "(V?)PERMIL(PD|PS)(Z128)?rm", 1330 "(V?)PACK(U|S)S(DW|WB)(Z128)?rm", 1331 "(V?)UNPCK(L|H)(PD|PS)(Z128)?rm")>; 1332 1333def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1334 let Latency = 7; 1335 let NumMicroOps = 2; 1336 let ResourceCycles = [1,1]; 1337} 1338def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", 1339 "VCVTPD2DQ(Y|Z256)rr", 1340 "VCVTPD2PS(Y|Z256)rr", 1341 "VCVTPD2UDQZ256rr", 1342 "VCVTPS2PD(Y|Z256)rr", 1343 "VCVTPS2QQZ256rr", 1344 "VCVTPS2UQQZ256rr", 1345 "VCVTQQ2PSZ256rr", 1346 "VCVTTPD2DQ(Y|Z256)rr", 1347 "VCVTTPD2UDQZ256rr", 1348 "VCVTTPS2QQZ256rr", 1349 "VCVTTPS2UQQZ256rr", 1350 "VCVTUDQ2PDZ256rr", 1351 "VCVTUQQ2PSZ256rr")>; 1352 1353def ICXWriteResGroup93z : SchedWriteRes<[ICXPort5,ICXPort05]> { 1354 let Latency = 7; 1355 let NumMicroOps = 2; 1356 let ResourceCycles = [1,1]; 1357} 1358def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr, 1359 VCVTPD2DQZrr, 1360 VCVTPD2PSZrr, 1361 VCVTPD2UDQZrr, 1362 VCVTPS2PDZrr, 1363 VCVTPS2QQZrr, 1364 VCVTPS2UQQZrr, 1365 VCVTQQ2PSZrr, 1366 VCVTTPD2DQZrr, 1367 VCVTTPD2UDQZrr, 1368 VCVTTPS2QQZrr, 1369 VCVTTPS2UQQZrr, 1370 VCVTUDQ2PDZrr, 1371 VCVTUQQ2PSZrr)>; 1372 1373def ICXWriteResGroup95 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1374 let Latency = 7; 1375 let NumMicroOps = 2; 1376 let ResourceCycles = [1,1]; 1377} 1378def: InstRW<[ICXWriteResGroup95], (instrs VMOVNTDQAZ128rm, 1379 VPBLENDDrmi)>; 1380def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd], 1381 (instregex "VBLENDMPDZ128rm(b?)", 1382 "VBLENDMPSZ128rm(b?)", 1383 "VBROADCASTI32X2Z128rm(b?)", 1384 "VBROADCASTSSZ128rm(b?)", 1385 "VINSERT(F|I)128rm", 1386 "VMOVAPDZ128rm(b?)", 1387 "VMOVAPSZ128rm(b?)", 1388 "VMOVDDUPZ128rm(b?)", 1389 "VMOVDQA32Z128rm(b?)", 1390 "VMOVDQA64Z128rm(b?)", 1391 "VMOVDQU16Z128rm(b?)", 1392 "VMOVDQU32Z128rm(b?)", 1393 "VMOVDQU64Z128rm(b?)", 1394 "VMOVDQU8Z128rm(b?)", 1395 "VMOVSHDUPZ128rm(b?)", 1396 "VMOVSLDUPZ128rm(b?)", 1397 "VMOVUPDZ128rm(b?)", 1398 "VMOVUPSZ128rm(b?)", 1399 "VPADD(B|D|Q|W)Z128rm(b?)", 1400 "(V?)PADD(B|D|Q|W)rm", 1401 "VPBLENDM(B|D|Q|W)Z128rm(b?)", 1402 "VPBROADCASTDZ128rm(b?)", 1403 "VPBROADCASTQZ128rm(b?)", 1404 "VPSUB(B|D|Q|W)Z128rm(b?)", 1405 "(V?)PSUB(B|D|Q|W)rm", 1406 "VPTERNLOGDZ128rm(b?)i", 1407 "VPTERNLOGQZ128rm(b?)i")>; 1408 1409def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1410 let Latency = 7; 1411 let NumMicroOps = 3; 1412 let ResourceCycles = [2,1]; 1413} 1414def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWrm, 1415 MMX_PACKSSWBrm, 1416 MMX_PACKUSWBrm)>; 1417 1418def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1419 let Latency = 7; 1420 let NumMicroOps = 3; 1421 let ResourceCycles = [2,1]; 1422} 1423def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr", 1424 "VPERMI2W256rr", 1425 "VPERMI2Wrr", 1426 "VPERMT2W128rr", 1427 "VPERMT2W256rr", 1428 "VPERMT2Wrr")>; 1429 1430def ICXWriteResGroup99 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1431 let Latency = 7; 1432 let NumMicroOps = 3; 1433 let ResourceCycles = [1,2]; 1434} 1435def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64, 1436 SCASB, SCASL, SCASQ, SCASW)>; 1437 1438def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort015]> { 1439 let Latency = 7; 1440 let NumMicroOps = 3; 1441 let ResourceCycles = [1,1,1]; 1442} 1443def: InstRW<[ICXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", 1444 "(V?)CVTSS2SI64(Z?)rr", 1445 "(V?)CVTTSS2SI64(Z?)rr", 1446 "VCVTTSS2USI64Zrr")>; 1447 1448def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> { 1449 let Latency = 7; 1450 let NumMicroOps = 3; 1451 let ResourceCycles = [1,1,1]; 1452} 1453def: InstRW<[ICXWriteResGroup101], (instrs FLDCW16m)>; 1454 1455def ICXWriteResGroup103 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort0156]> { 1456 let Latency = 7; 1457 let NumMicroOps = 3; 1458 let ResourceCycles = [1,1,1]; 1459} 1460def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; 1461 1462def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> { 1463 let Latency = 7; 1464 let NumMicroOps = 3; 1465 let ResourceCycles = [1,1,1]; 1466} 1467def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>; 1468 1469def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1470 let Latency = 7; 1471 let NumMicroOps = 4; 1472 let ResourceCycles = [1,2,1]; 1473} 1474def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", 1475 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", 1476 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", 1477 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; 1478 1479def ICXWriteResGroup107 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1480 let Latency = 7; 1481 let NumMicroOps = 5; 1482 let ResourceCycles = [1,1,1,2]; 1483} 1484def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", 1485 "ROR(8|16|32|64)m(1|i)")>; 1486 1487def ICXWriteResGroup107_1 : SchedWriteRes<[ICXPort06]> { 1488 let Latency = 2; 1489 let NumMicroOps = 2; 1490 let ResourceCycles = [2]; 1491} 1492def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1493 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1494 1495def ICXWriteResGroup108 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1496 let Latency = 7; 1497 let NumMicroOps = 5; 1498 let ResourceCycles = [1,1,1,2]; 1499} 1500def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; 1501 1502def ICXWriteResGroup109 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 1503 let Latency = 7; 1504 let NumMicroOps = 5; 1505 let ResourceCycles = [1,1,1,1,1]; 1506} 1507def: InstRW<[ICXWriteResGroup109], (instregex "CALL(16|32|64)m")>; 1508def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>; 1509 1510def ICXWriteResGroup110 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1511 let Latency = 7; 1512 let NumMicroOps = 7; 1513 let ResourceCycles = [1,2,2,2]; 1514} 1515def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr, 1516 VPSCATTERQQZ128mr, 1517 VSCATTERDPDZ128mr, 1518 VSCATTERQPDZ128mr)>; 1519 1520def ICXWriteResGroup111 : SchedWriteRes<[ICXPort6,ICXPort06,ICXPort15,ICXPort0156]> { 1521 let Latency = 7; 1522 let NumMicroOps = 7; 1523 let ResourceCycles = [1,3,1,2]; 1524} 1525def: InstRW<[ICXWriteResGroup111], (instrs LOOP)>; 1526 1527def ICXWriteResGroup112 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1528 let Latency = 7; 1529 let NumMicroOps = 11; 1530 let ResourceCycles = [1,4,4,2]; 1531} 1532def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr, 1533 VPSCATTERQQZ256mr, 1534 VSCATTERDPDZ256mr, 1535 VSCATTERQPDZ256mr)>; 1536 1537def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1538 let Latency = 7; 1539 let NumMicroOps = 19; 1540 let ResourceCycles = [1,8,8,2]; 1541} 1542def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr, 1543 VPSCATTERQQZmr, 1544 VSCATTERDPDZmr, 1545 VSCATTERQPDZmr)>; 1546 1547def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1548 let Latency = 7; 1549 let NumMicroOps = 36; 1550 let ResourceCycles = [1,16,1,16,2]; 1551} 1552def: InstRW<[ICXWriteResGroup114], (instrs VSCATTERDPSZmr)>; 1553 1554def ICXWriteResGroup118 : SchedWriteRes<[ICXPort1,ICXPort23]> { 1555 let Latency = 8; 1556 let NumMicroOps = 2; 1557 let ResourceCycles = [1,1]; 1558} 1559def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm", 1560 "PEXT(32|64)rm")>; 1561 1562def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1563 let Latency = 8; 1564 let NumMicroOps = 2; 1565 let ResourceCycles = [1,1]; 1566} 1567def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", 1568 "VPBROADCASTB(Z|Z256)rm(b?)", 1569 "VPBROADCASTW(Z|Z256)rm(b?)", 1570 "(V?)PALIGNR(Y|Z|Z256)rmi", 1571 "(V?)PERMIL(PD|PS)(Y|Z|Z256)m(b?)i", 1572 "(V?)PERMIL(PD|PS)(Y|Z|Z256)rm", 1573 "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z256)rm", 1574 "(V?)UNPCK(L|H)(PD|PS)(Y|Z|Z256)rm")>; 1575def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm, 1576 VPBROADCASTWYrm, 1577 VPMOVSXBDYrm, 1578 VPMOVSXBQYrm, 1579 VPMOVSXWQYrm)>; 1580 1581def ICXWriteResGroup121 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1582 let Latency = 8; 1583 let NumMicroOps = 2; 1584 let ResourceCycles = [1,1]; 1585} 1586def: InstRW<[ICXWriteResGroup121], (instrs VMOVNTDQAZ256rm, 1587 VPBLENDDYrmi)>; 1588def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd], 1589 (instregex "VBLENDMPD(Z|Z256)rm(b?)", 1590 "VBLENDMPS(Z|Z256)rm(b?)", 1591 "VBROADCASTF32X2Z256rm(b?)", 1592 "VBROADCASTF32X2Zrm(b?)", 1593 "VBROADCASTF32X4Z256rm(b?)", 1594 "VBROADCASTF32X4rm(b?)", 1595 "VBROADCASTF32X8rm(b?)", 1596 "VBROADCASTF64X2Z128rm(b?)", 1597 "VBROADCASTF64X2rm(b?)", 1598 "VBROADCASTF64X4rm(b?)", 1599 "VBROADCASTI32X2Z256rm(b?)", 1600 "VBROADCASTI32X2Zrm(b?)", 1601 "VBROADCASTI32X4Z256rm(b?)", 1602 "VBROADCASTI32X4rm(b?)", 1603 "VBROADCASTI32X8rm(b?)", 1604 "VBROADCASTI64X2Z128rm(b?)", 1605 "VBROADCASTI64X2rm(b?)", 1606 "VBROADCASTI64X4rm(b?)", 1607 "VBROADCASTSD(Z|Z256)rm(b?)", 1608 "VBROADCASTSS(Z|Z256)rm(b?)", 1609 "VINSERTF32x4(Z|Z256)rm(b?)", 1610 "VINSERTF32x8Zrm(b?)", 1611 "VINSERTF64x2(Z|Z256)rm(b?)", 1612 "VINSERTF64x4Zrm(b?)", 1613 "VINSERTI32x4(Z|Z256)rm(b?)", 1614 "VINSERTI32x8Zrm(b?)", 1615 "VINSERTI64x2(Z|Z256)rm(b?)", 1616 "VINSERTI64x4Zrm(b?)", 1617 "VMOVAPD(Z|Z256)rm(b?)", 1618 "VMOVAPS(Z|Z256)rm(b?)", 1619 "VMOVDDUP(Z|Z256)rm(b?)", 1620 "VMOVDQA32(Z|Z256)rm(b?)", 1621 "VMOVDQA64(Z|Z256)rm(b?)", 1622 "VMOVDQU16(Z|Z256)rm(b?)", 1623 "VMOVDQU32(Z|Z256)rm(b?)", 1624 "VMOVDQU64(Z|Z256)rm(b?)", 1625 "VMOVDQU8(Z|Z256)rm(b?)", 1626 "VMOVSHDUP(Z|Z256)rm(b?)", 1627 "VMOVSLDUP(Z|Z256)rm(b?)", 1628 "VMOVUPD(Z|Z256)rm(b?)", 1629 "VMOVUPS(Z|Z256)rm(b?)", 1630 "VPADD(B|D|Q|W)Yrm", 1631 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", 1632 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", 1633 "VPBROADCASTD(Z|Z256)rm(b?)", 1634 "VPBROADCASTQ(Z|Z256)rm(b?)", 1635 "VPSUB(B|D|Q|W)Yrm", 1636 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", 1637 "VPTERNLOGD(Z|Z256)rm(b?)i", 1638 "VPTERNLOGQ(Z|Z256)rm(b?)i")>; 1639 1640def ICXWriteResGroup123 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1641 let Latency = 8; 1642 let NumMicroOps = 4; 1643 let ResourceCycles = [1,2,1]; 1644} 1645def: InstRW<[ICXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1646 1647def ICXWriteResGroup127 : SchedWriteRes<[ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1648 let Latency = 8; 1649 let NumMicroOps = 5; 1650 let ResourceCycles = [1,1,1,2]; 1651} 1652def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", 1653 "RCR(8|16|32|64)m(1|i)")>; 1654 1655def ICXWriteResGroup128 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1656 let Latency = 8; 1657 let NumMicroOps = 6; 1658 let ResourceCycles = [1,1,1,3]; 1659} 1660def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", 1661 "ROR(8|16|32|64)mCL", 1662 "SAR(8|16|32|64)mCL", 1663 "SHL(8|16|32|64)mCL", 1664 "SHR(8|16|32|64)mCL")>; 1665 1666def ICXWriteResGroup130 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1667 let Latency = 8; 1668 let NumMicroOps = 6; 1669 let ResourceCycles = [1,1,1,2,1]; 1670} 1671def: SchedAlias<WriteADCRMW, ICXWriteResGroup130>; 1672 1673def ICXWriteResGroup131 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1674 let Latency = 8; 1675 let NumMicroOps = 8; 1676 let ResourceCycles = [1,2,1,2,2]; 1677} 1678def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr, 1679 VPSCATTERQDZ256mr, 1680 VSCATTERQPSZ128mr, 1681 VSCATTERQPSZ256mr)>; 1682 1683def ICXWriteResGroup132 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1684 let Latency = 8; 1685 let NumMicroOps = 12; 1686 let ResourceCycles = [1,4,1,4,2]; 1687} 1688def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr, 1689 VSCATTERDPSZ128mr)>; 1690 1691def ICXWriteResGroup133 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1692 let Latency = 8; 1693 let NumMicroOps = 20; 1694 let ResourceCycles = [1,8,1,8,2]; 1695} 1696def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr, 1697 VSCATTERDPSZ256mr)>; 1698 1699def ICXWriteResGroup134 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1700 let Latency = 8; 1701 let NumMicroOps = 36; 1702 let ResourceCycles = [1,16,1,16,2]; 1703} 1704def: InstRW<[ICXWriteResGroup134], (instrs VPSCATTERDDZmr)>; 1705 1706def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1707 let Latency = 9; 1708 let NumMicroOps = 2; 1709 let ResourceCycles = [1,1]; 1710} 1711def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>; 1712 1713def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1714 let Latency = 9; 1715 let NumMicroOps = 2; 1716 let ResourceCycles = [1,1]; 1717} 1718def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm, 1719 VPMOVSXDQYrm, 1720 VPMOVSXWDYrm, 1721 VPMOVZXWDYrm)>; 1722def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", 1723 "VFPCLASSSDZrm(b?)", 1724 "VFPCLASSSSZrm(b?)", 1725 "(V?)PCMPGTQrm", 1726 "VPERMI2D128rm(b?)", 1727 "VPERMI2PD128rm(b?)", 1728 "VPERMI2PS128rm(b?)", 1729 "VPERMI2Q128rm(b?)", 1730 "VPERMT2D128rm(b?)", 1731 "VPERMT2PD128rm(b?)", 1732 "VPERMT2PS128rm(b?)", 1733 "VPERMT2Q128rm(b?)", 1734 "VPMAXSQZ128rm(b?)", 1735 "VPMAXUQZ128rm(b?)", 1736 "VPMINSQZ128rm(b?)", 1737 "VPMINUQZ128rm(b?)")>; 1738 1739def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1740 let Latency = 10; 1741 let NumMicroOps = 2; 1742 let ResourceCycles = [1,1]; 1743} 1744def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i", 1745 "VCMP(SD|SS)Zrm", 1746 "VFPCLASSPDZ128rm(b?)", 1747 "VFPCLASSPSZ128rm(b?)", 1748 "VPCMPBZ128rmi(b?)", 1749 "VPCMPDZ128rmi(b?)", 1750 "VPCMPEQ(B|D|Q|W)Z128rm(b?)", 1751 "VPCMPGT(B|D|Q|W)Z128rm(b?)", 1752 "VPCMPQZ128rmi(b?)", 1753 "VPCMPU(B|D|Q|W)Z128rmi(b?)", 1754 "VPCMPWZ128rmi(b?)", 1755 "VPTESTMBZ128rm(b?)", 1756 "VPTESTMDZ128rm(b?)", 1757 "VPTESTMQZ128rm(b?)", 1758 "VPTESTMWZ128rm(b?)", 1759 "VPTESTNMBZ128rm(b?)", 1760 "VPTESTNMDZ128rm(b?)", 1761 "VPTESTNMQZ128rm(b?)", 1762 "VPTESTNMWZ128rm(b?)")>; 1763 1764def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1765 let Latency = 9; 1766 let NumMicroOps = 2; 1767 let ResourceCycles = [1,1]; 1768} 1769def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm", 1770 "(V?)CVTPS2PDrm")>; 1771 1772def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1773 let Latency = 9; 1774 let NumMicroOps = 4; 1775 let ResourceCycles = [2,1,1]; 1776} 1777def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm", 1778 "(V?)PHSUBSWrm")>; 1779 1780def ICXWriteResGroup146 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 1781 let Latency = 9; 1782 let NumMicroOps = 5; 1783 let ResourceCycles = [1,2,1,1]; 1784} 1785def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm", 1786 "LSL(16|32|64)rm")>; 1787 1788def ICXWriteResGroup148 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1789 let Latency = 10; 1790 let NumMicroOps = 2; 1791 let ResourceCycles = [1,1]; 1792} 1793def: InstRW<[ICXWriteResGroup148], (instrs VPCMPGTQYrm)>; 1794def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1795 "ILD_F(16|32|64)m", 1796 "VALIGND(Z|Z256)rm(b?)i", 1797 "VALIGNQ(Z|Z256)rm(b?)i", 1798 "VPMAXSQ(Z|Z256)rm(b?)", 1799 "VPMAXUQ(Z|Z256)rm(b?)", 1800 "VPMINSQ(Z|Z256)rm(b?)", 1801 "VPMINUQ(Z|Z256)rm(b?)")>; 1802 1803def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1804 let Latency = 11; 1805 let NumMicroOps = 2; 1806 let ResourceCycles = [1,1]; 1807} 1808def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i", 1809 "VCMPPS(Z|Z256)rm(b?)i", 1810 "VFPCLASSPD(Z|Z256)rm(b?)", 1811 "VFPCLASSPS(Z|Z256)rm(b?)", 1812 "VPCMPB(Z|Z256)rmi(b?)", 1813 "VPCMPD(Z|Z256)rmi(b?)", 1814 "VPCMPEQB(Z|Z256)rm(b?)", 1815 "VPCMPEQD(Z|Z256)rm(b?)", 1816 "VPCMPEQQ(Z|Z256)rm(b?)", 1817 "VPCMPEQW(Z|Z256)rm(b?)", 1818 "VPCMPGTB(Z|Z256)rm(b?)", 1819 "VPCMPGTD(Z|Z256)rm(b?)", 1820 "VPCMPGTQ(Z|Z256)rm(b?)", 1821 "VPCMPGTW(Z|Z256)rm(b?)", 1822 "VPCMPQ(Z|Z256)rmi(b?)", 1823 "VPCMPU(B|D|Q|W)Z256rmi(b?)", 1824 "VPCMPU(B|D|Q|W)Zrmi(b?)", 1825 "VPCMPW(Z|Z256)rmi(b?)", 1826 "VPTESTM(B|D|Q|W)Z256rm(b?)", 1827 "VPTESTM(B|D|Q|W)Zrm(b?)", 1828 "VPTESTNM(B|D|Q|W)Z256rm(b?)", 1829 "VPTESTNM(B|D|Q|W)Zrm(b?)")>; 1830 1831def ICXWriteResGroup149 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1832 let Latency = 10; 1833 let NumMicroOps = 2; 1834 let ResourceCycles = [1,1]; 1835} 1836def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", 1837 "VCVTDQ2PSZ128rm(b?)", 1838 "(V?)CVTDQ2PSrm", 1839 "VCVTPD2QQZ128rm(b?)", 1840 "VCVTPD2UQQZ128rm(b?)", 1841 "VCVTPH2PSZ128rm(b?)", 1842 "VCVTPS2DQZ128rm(b?)", 1843 "(V?)CVTPS2DQrm", 1844 "VCVTPS2PDZ128rm(b?)", 1845 "VCVTPS2QQZ128rm(b?)", 1846 "VCVTPS2UDQZ128rm(b?)", 1847 "VCVTPS2UQQZ128rm(b?)", 1848 "VCVTQQ2PDZ128rm(b?)", 1849 "VCVTQQ2PSZ128rm(b?)", 1850 "VCVTSS2SDZrm", 1851 "(V?)CVTSS2SDrm", 1852 "VCVTTPD2QQZ128rm(b?)", 1853 "VCVTTPD2UQQZ128rm(b?)", 1854 "VCVTTPS2DQZ128rm(b?)", 1855 "(V?)CVTTPS2DQrm", 1856 "VCVTTPS2QQZ128rm(b?)", 1857 "VCVTTPS2UDQZ128rm(b?)", 1858 "VCVTTPS2UQQZ128rm(b?)", 1859 "VCVTUDQ2PDZ128rm(b?)", 1860 "VCVTUDQ2PSZ128rm(b?)", 1861 "VCVTUQQ2PDZ128rm(b?)", 1862 "VCVTUQQ2PSZ128rm(b?)")>; 1863 1864def ICXWriteResGroup151 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1865 let Latency = 10; 1866 let NumMicroOps = 3; 1867 let ResourceCycles = [2,1]; 1868} 1869def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", 1870 "VEXPANDPSZ128rm(b?)", 1871 "VPEXPANDDZ128rm(b?)", 1872 "VPEXPANDQZ128rm(b?)")>; 1873 1874def ICXWriteResGroup153 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1875 let Latency = 10; 1876 let NumMicroOps = 3; 1877 let ResourceCycles = [1,1,1]; 1878} 1879def: InstRW<[ICXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; 1880 1881def ICXWriteResGroup154 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1882 let Latency = 10; 1883 let NumMicroOps = 4; 1884 let ResourceCycles = [2,1,1]; 1885} 1886def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm, 1887 VPHSUBSWYrm)>; 1888 1889def ICXWriteResGroup157 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1890 let Latency = 10; 1891 let NumMicroOps = 8; 1892 let ResourceCycles = [1,1,1,1,1,3]; 1893} 1894def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; 1895 1896def ICXWriteResGroup159 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 1897 let Latency = 11; 1898 let NumMicroOps = 1; 1899 let ResourceCycles = [1,3]; 1900} 1901def : SchedAlias<WriteFDivX, ICXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair 1902 1903def ICXWriteResGroup160 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1904 let Latency = 11; 1905 let NumMicroOps = 2; 1906 let ResourceCycles = [1,1]; 1907} 1908def: InstRW<[ICXWriteResGroup160], (instregex "MUL_F(32|64)m")>; 1909 1910def ICXWriteResGroup161 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1911 let Latency = 11; 1912 let NumMicroOps = 2; 1913 let ResourceCycles = [1,1]; 1914} 1915def: InstRW<[ICXWriteResGroup161], (instrs VCVTDQ2PSYrm, 1916 VCVTPS2PDYrm)>; 1917def: InstRW<[ICXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", 1918 "VCVTPH2PS(Z|Z256)rm(b?)", 1919 "VCVTPS2PD(Z|Z256)rm(b?)", 1920 "VCVTQQ2PD(Z|Z256)rm(b?)", 1921 "VCVTQQ2PSZ256rm(b?)", 1922 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1923 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1924 "VCVT(T?)PS2DQYrm", 1925 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1926 "VCVT(T?)PS2QQZ256rm(b?)", 1927 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1928 "VCVT(T?)PS2UQQZ256rm(b?)", 1929 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", 1930 "VCVTUQQ2PD(Z|Z256)rm(b?)", 1931 "VCVTUQQ2PSZ256rm(b?)")>; 1932 1933def ICXWriteResGroup162 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1934 let Latency = 11; 1935 let NumMicroOps = 3; 1936 let ResourceCycles = [2,1]; 1937} 1938def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", 1939 "VEXPANDPD(Z|Z256)rm(b?)", 1940 "VEXPANDPS(Z|Z256)rm(b?)", 1941 "VPEXPANDD(Z|Z256)rm(b?)", 1942 "VPEXPANDQ(Z|Z256)rm(b?)")>; 1943 1944def ICXWriteResGroup163 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1945 let Latency = 11; 1946 let NumMicroOps = 3; 1947 let ResourceCycles = [1,2]; 1948} 1949def: InstRW<[ICXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; 1950 1951def ICXWriteResGroup164 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1952 let Latency = 11; 1953 let NumMicroOps = 3; 1954 let ResourceCycles = [1,1,1]; 1955} 1956def: InstRW<[ICXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; 1957 1958def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1959 let Latency = 11; 1960 let NumMicroOps = 3; 1961 let ResourceCycles = [1,1,1]; 1962} 1963def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2PSrm, 1964 CVTPD2DQrm, 1965 CVTTPD2DQrm, 1966 MMX_CVTPD2PIrm, 1967 MMX_CVTTPD2PIrm)>; 1968 1969def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1970 let Latency = 11; 1971 let NumMicroOps = 4; 1972 let ResourceCycles = [2,1,1]; 1973} 1974def: InstRW<[ICXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; 1975 1976def ICXWriteResGroup169 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 1977 let Latency = 11; 1978 let NumMicroOps = 7; 1979 let ResourceCycles = [2,3,2]; 1980} 1981def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL", 1982 "RCR(16|32|64)rCL")>; 1983 1984def ICXWriteResGroup170 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 1985 let Latency = 11; 1986 let NumMicroOps = 9; 1987 let ResourceCycles = [1,5,1,2]; 1988} 1989def: InstRW<[ICXWriteResGroup170], (instrs RCL8rCL)>; 1990 1991def ICXWriteResGroup171 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1992 let Latency = 11; 1993 let NumMicroOps = 11; 1994 let ResourceCycles = [2,9]; 1995} 1996def: InstRW<[ICXWriteResGroup171], (instrs LOOPE, LOOPNE)>; 1997 1998def ICXWriteResGroup174 : SchedWriteRes<[ICXPort01]> { 1999 let Latency = 15; 2000 let NumMicroOps = 3; 2001 let ResourceCycles = [3]; 2002} 2003def: InstRW<[ICXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; 2004 2005def ICXWriteResGroup174z : SchedWriteRes<[ICXPort05]> { 2006 let Latency = 15; 2007 let NumMicroOps = 3; 2008 let ResourceCycles = [3]; 2009} 2010def: InstRW<[ICXWriteResGroup174z], (instregex "VPMULLQZrr")>; 2011 2012def ICXWriteResGroup175 : SchedWriteRes<[ICXPort5,ICXPort23]> { 2013 let Latency = 12; 2014 let NumMicroOps = 3; 2015 let ResourceCycles = [2,1]; 2016} 2017def: InstRW<[ICXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; 2018 2019def ICXWriteResGroup176 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015]> { 2020 let Latency = 12; 2021 let NumMicroOps = 3; 2022 let ResourceCycles = [1,1,1]; 2023} 2024def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 2025 "VCVT(T?)SS2USI64Zrm(b?)")>; 2026 2027def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2028 let Latency = 12; 2029 let NumMicroOps = 3; 2030 let ResourceCycles = [1,1,1]; 2031} 2032def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", 2033 "VCVT(T?)PS2UQQZrm(b?)")>; 2034 2035def ICXWriteResGroup179 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { 2036 let Latency = 12; 2037 let NumMicroOps = 4; 2038 let ResourceCycles = [1,1,1,1]; 2039} 2040def: InstRW<[ICXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; 2041 2042def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> { 2043 let Latency = 13; 2044 let NumMicroOps = 3; 2045 let ResourceCycles = [2,1]; 2046} 2047def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", 2048 "VPERMWZ256rm(b?)", 2049 "VPERMWZrm(b?)")>; 2050 2051def ICXWriteResGroup181 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2052 let Latency = 13; 2053 let NumMicroOps = 3; 2054 let ResourceCycles = [1,1,1]; 2055} 2056def: InstRW<[ICXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; 2057 2058def ICXWriteResGroup183 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2059 let Latency = 13; 2060 let NumMicroOps = 4; 2061 let ResourceCycles = [2,1,1]; 2062} 2063def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", 2064 "VPERMT2W128rm(b?)")>; 2065 2066def ICXWriteResGroup184 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 2067 let Latency = 14; 2068 let NumMicroOps = 1; 2069 let ResourceCycles = [1,3]; 2070} 2071def : SchedAlias<WriteFDiv64, ICXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2072def : SchedAlias<WriteFDiv64X, ICXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2073 2074def ICXWriteResGroup184_1 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 2075 let Latency = 14; 2076 let NumMicroOps = 1; 2077 let ResourceCycles = [1,5]; 2078} 2079def : SchedAlias<WriteFDiv64Y, ICXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair 2080 2081def ICXWriteResGroup187 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2082 let Latency = 14; 2083 let NumMicroOps = 3; 2084 let ResourceCycles = [1,1,1]; 2085} 2086def: InstRW<[ICXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; 2087 2088def ICXWriteResGroup188 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2089 let Latency = 14; 2090 let NumMicroOps = 3; 2091 let ResourceCycles = [1,1,1]; 2092} 2093def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", 2094 "VCVTPD2PSZrm(b?)", 2095 "VCVTPD2UDQZrm(b?)", 2096 "VCVTQQ2PSZrm(b?)", 2097 "VCVTTPD2DQZrm(b?)", 2098 "VCVTTPD2UDQZrm(b?)", 2099 "VCVTUQQ2PSZrm(b?)")>; 2100 2101def ICXWriteResGroup189 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2102 let Latency = 14; 2103 let NumMicroOps = 4; 2104 let ResourceCycles = [2,1,1]; 2105} 2106def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", 2107 "VPERMI2Wrm(b?)", 2108 "VPERMT2W256rm(b?)", 2109 "VPERMT2Wrm(b?)")>; 2110 2111def ICXWriteResGroup190 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 2112 let Latency = 14; 2113 let NumMicroOps = 10; 2114 let ResourceCycles = [2,4,1,3]; 2115} 2116def: InstRW<[ICXWriteResGroup190], (instrs RCR8rCL)>; 2117 2118def ICXWriteResGroup191 : SchedWriteRes<[ICXPort0]> { 2119 let Latency = 15; 2120 let NumMicroOps = 1; 2121 let ResourceCycles = [1]; 2122} 2123def: InstRW<[ICXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 2124 2125def ICXWriteResGroup194 : SchedWriteRes<[ICXPort1,ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2126 let Latency = 15; 2127 let NumMicroOps = 8; 2128 let ResourceCycles = [1,2,2,1,2]; 2129} 2130def: InstRW<[ICXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; 2131 2132def ICXWriteResGroup195 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2133 let Latency = 15; 2134 let NumMicroOps = 10; 2135 let ResourceCycles = [1,1,1,5,1,1]; 2136} 2137def: InstRW<[ICXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; 2138 2139def ICXWriteResGroup199 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2140 let Latency = 16; 2141 let NumMicroOps = 14; 2142 let ResourceCycles = [1,1,1,4,2,5]; 2143} 2144def: InstRW<[ICXWriteResGroup199], (instrs CMPXCHG8B)>; 2145 2146def ICXWriteResGroup200 : SchedWriteRes<[ICXPort1, ICXPort05, ICXPort6]> { 2147 let Latency = 12; 2148 let NumMicroOps = 34; 2149 let ResourceCycles = [1, 4, 5]; 2150} 2151def: InstRW<[ICXWriteResGroup200], (instrs VZEROALL)>; 2152 2153def ICXWriteResGroup201 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2154 let Latency = 17; 2155 let NumMicroOps = 2; 2156 let ResourceCycles = [1,1,5]; 2157} 2158def : SchedAlias<WriteFDivXLd, ICXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair 2159 2160def ICXWriteResGroup202 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156]> { 2161 let Latency = 17; 2162 let NumMicroOps = 15; 2163 let ResourceCycles = [2,1,2,4,2,4]; 2164} 2165def: InstRW<[ICXWriteResGroup202], (instrs XCH_F)>; 2166 2167def ICXWriteResGroup205 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2168 let Latency = 21; 2169 let NumMicroOps = 4; 2170 let ResourceCycles = [1,3]; 2171} 2172def: InstRW<[ICXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; 2173 2174def ICXWriteResGroup207 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort06,ICXPort0156]> { 2175 let Latency = 18; 2176 let NumMicroOps = 8; 2177 let ResourceCycles = [1,1,1,5]; 2178} 2179def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>; 2180 2181def ICXWriteResGroup208 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2182 let Latency = 18; 2183 let NumMicroOps = 11; 2184 let ResourceCycles = [2,1,1,4,1,2]; 2185} 2186def: InstRW<[ICXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; 2187 2188def ICXWriteResGroup209 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2189 let Latency = 19; 2190 let NumMicroOps = 2; 2191 let ResourceCycles = [1,1,4]; 2192} 2193def : SchedAlias<WriteFDiv64Ld, ICXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair 2194 2195def ICXWriteResGroup211 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2196 let Latency = 22; 2197 let NumMicroOps = 4; 2198 let ResourceCycles = [1,3]; 2199} 2200def: InstRW<[ICXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>; 2201 2202def ICXWriteResGroup211_1 : SchedWriteRes<[ICXPort23,ICXPort05]> { 2203 let Latency = 22; 2204 let NumMicroOps = 4; 2205 let ResourceCycles = [1,3]; 2206} 2207def: InstRW<[ICXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>; 2208 2209def ICXWriteResGroup215 : SchedWriteRes<[ICXPort0]> { 2210 let Latency = 20; 2211 let NumMicroOps = 1; 2212 let ResourceCycles = [1]; 2213} 2214def: InstRW<[ICXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 2215 2216def ICXWriteResGroup216 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2217 let Latency = 20; 2218 let NumMicroOps = 2; 2219 let ResourceCycles = [1,1,4]; 2220} 2221def : SchedAlias<WriteFDiv64XLd, ICXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair 2222 2223def ICXWriteGatherEVEX2 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2224 let Latency = 17; 2225 let NumMicroOps = 5; // 2 uops perform multiple loads 2226 let ResourceCycles = [1,2,1,1]; 2227} 2228def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm, 2229 VGATHERDPDZ128rm, VPGATHERDQZ128rm, 2230 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>; 2231 2232def ICXWriteGatherEVEX4 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2233 let Latency = 19; 2234 let NumMicroOps = 5; // 2 uops perform multiple loads 2235 let ResourceCycles = [1,4,1,1]; 2236} 2237def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm, 2238 VGATHERQPDZ256rm, VPGATHERQQZ256rm, 2239 VGATHERDPSZ128rm, VPGATHERDDZ128rm, 2240 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>; 2241 2242def ICXWriteGatherEVEX8 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2243 let Latency = 21; 2244 let NumMicroOps = 5; // 2 uops perform multiple loads 2245 let ResourceCycles = [1,8,1,1]; 2246} 2247def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm, 2248 VGATHERDPDZrm, VPGATHERDQZrm, 2249 VGATHERQPDZrm, VPGATHERQQZrm, 2250 VGATHERQPSZrm, VPGATHERQDZrm)>; 2251 2252def ICXWriteGatherEVEX16 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2253 let Latency = 25; 2254 let NumMicroOps = 5; // 2 uops perform multiple loads 2255 let ResourceCycles = [1,16,1,1]; 2256} 2257def: InstRW<[ICXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>; 2258 2259def ICXWriteResGroup219 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2260 let Latency = 20; 2261 let NumMicroOps = 8; 2262 let ResourceCycles = [1,1,1,1,1,1,2]; 2263} 2264def: InstRW<[ICXWriteResGroup219], (instrs INSB, INSL, INSW)>; 2265 2266def ICXWriteResGroup220 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort0156]> { 2267 let Latency = 20; 2268 let NumMicroOps = 10; 2269 let ResourceCycles = [1,2,7]; 2270} 2271def: InstRW<[ICXWriteResGroup220], (instrs MWAITrr)>; 2272 2273def ICXWriteResGroup222 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2274 let Latency = 21; 2275 let NumMicroOps = 2; 2276 let ResourceCycles = [1,1,8]; 2277} 2278def : SchedAlias<WriteFDiv64YLd, ICXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair 2279 2280def ICXWriteResGroup223 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2281 let Latency = 22; 2282 let NumMicroOps = 2; 2283 let ResourceCycles = [1,1]; 2284} 2285def: InstRW<[ICXWriteResGroup223], (instregex "DIV_F(32|64)m")>; 2286 2287def ICXWriteResGroupVEX2 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2288 let Latency = 18; 2289 let NumMicroOps = 5; // 2 uops perform multiple loads 2290 let ResourceCycles = [1,2,1,1]; 2291} 2292def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 2293 VGATHERQPDrm, VPGATHERQQrm, 2294 VGATHERQPSrm, VPGATHERQDrm)>; 2295 2296def ICXWriteResGroupVEX4 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2297 let Latency = 20; 2298 let NumMicroOps = 5; // 2 uops peform multiple loads 2299 let ResourceCycles = [1,4,1,1]; 2300} 2301def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 2302 VGATHERDPSrm, VPGATHERDDrm, 2303 VGATHERQPDYrm, VPGATHERQQYrm, 2304 VGATHERQPSYrm, VPGATHERQDYrm)>; 2305 2306def ICXWriteResGroupVEX8 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2307 let Latency = 22; 2308 let NumMicroOps = 5; // 2 uops perform multiple loads 2309 let ResourceCycles = [1,8,1,1]; 2310} 2311def: InstRW<[ICXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 2312 2313def ICXWriteResGroup225 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2314 let Latency = 22; 2315 let NumMicroOps = 14; 2316 let ResourceCycles = [5,5,4]; 2317} 2318def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", 2319 "VPCONFLICTQZ256rr")>; 2320 2321def ICXWriteResGroup228 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2322 let Latency = 23; 2323 let NumMicroOps = 19; 2324 let ResourceCycles = [2,1,4,1,1,4,6]; 2325} 2326def: InstRW<[ICXWriteResGroup228], (instrs CMPXCHG16B)>; 2327 2328def ICXWriteResGroup233 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2329 let Latency = 25; 2330 let NumMicroOps = 3; 2331 let ResourceCycles = [1,1,1]; 2332} 2333def: InstRW<[ICXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; 2334 2335def ICXWriteResGroup239 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2336 let Latency = 27; 2337 let NumMicroOps = 2; 2338 let ResourceCycles = [1,1]; 2339} 2340def: InstRW<[ICXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; 2341 2342def ICXWriteResGroup242 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2343 let Latency = 29; 2344 let NumMicroOps = 15; 2345 let ResourceCycles = [5,5,1,4]; 2346} 2347def: InstRW<[ICXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; 2348 2349def ICXWriteResGroup243 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2350 let Latency = 30; 2351 let NumMicroOps = 3; 2352 let ResourceCycles = [1,1,1]; 2353} 2354def: InstRW<[ICXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; 2355 2356def ICXWriteResGroup247 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort06,ICXPort0156]> { 2357 let Latency = 35; 2358 let NumMicroOps = 23; 2359 let ResourceCycles = [1,5,3,4,10]; 2360} 2361def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri", 2362 "IN(8|16|32)rr")>; 2363 2364def ICXWriteResGroup248 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2365 let Latency = 35; 2366 let NumMicroOps = 23; 2367 let ResourceCycles = [1,5,2,1,4,10]; 2368} 2369def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir", 2370 "OUT(8|16|32)rr")>; 2371 2372def ICXWriteResGroup249 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2373 let Latency = 37; 2374 let NumMicroOps = 21; 2375 let ResourceCycles = [9,7,5]; 2376} 2377def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", 2378 "VPCONFLICTQZrr")>; 2379 2380def ICXWriteResGroup250 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 2381 let Latency = 37; 2382 let NumMicroOps = 31; 2383 let ResourceCycles = [1,8,1,21]; 2384} 2385def: InstRW<[ICXWriteResGroup250], (instregex "XRSTOR(64)?")>; 2386 2387def ICXWriteResGroup252 : SchedWriteRes<[ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort15,ICXPort0156]> { 2388 let Latency = 40; 2389 let NumMicroOps = 18; 2390 let ResourceCycles = [1,1,2,3,1,1,1,8]; 2391} 2392def: InstRW<[ICXWriteResGroup252], (instrs VMCLEARm)>; 2393 2394def ICXWriteResGroup253 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2395 let Latency = 41; 2396 let NumMicroOps = 39; 2397 let ResourceCycles = [1,10,1,1,26]; 2398} 2399def: InstRW<[ICXWriteResGroup253], (instrs XSAVE64)>; 2400 2401def ICXWriteResGroup254 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 2402 let Latency = 42; 2403 let NumMicroOps = 22; 2404 let ResourceCycles = [2,20]; 2405} 2406def: InstRW<[ICXWriteResGroup254], (instrs RDTSCP)>; 2407 2408def ICXWriteResGroup255 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2409 let Latency = 42; 2410 let NumMicroOps = 40; 2411 let ResourceCycles = [1,11,1,1,26]; 2412} 2413def: InstRW<[ICXWriteResGroup255], (instrs XSAVE)>; 2414def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 2415 2416def ICXWriteResGroup256 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2417 let Latency = 44; 2418 let NumMicroOps = 22; 2419 let ResourceCycles = [9,7,1,5]; 2420} 2421def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", 2422 "VPCONFLICTQZrm(b?)")>; 2423 2424def ICXWriteResGroup258 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05,ICXPort06,ICXPort0156]> { 2425 let Latency = 62; 2426 let NumMicroOps = 64; 2427 let ResourceCycles = [2,8,5,10,39]; 2428} 2429def: InstRW<[ICXWriteResGroup258], (instrs FLDENVm)>; 2430 2431def ICXWriteResGroup259 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2432 let Latency = 63; 2433 let NumMicroOps = 88; 2434 let ResourceCycles = [4,4,31,1,2,1,45]; 2435} 2436def: InstRW<[ICXWriteResGroup259], (instrs FXRSTOR64)>; 2437 2438def ICXWriteResGroup260 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2439 let Latency = 63; 2440 let NumMicroOps = 90; 2441 let ResourceCycles = [4,2,33,1,2,1,47]; 2442} 2443def: InstRW<[ICXWriteResGroup260], (instrs FXRSTOR)>; 2444 2445def ICXWriteResGroup261 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2446 let Latency = 67; 2447 let NumMicroOps = 35; 2448 let ResourceCycles = [17,11,7]; 2449} 2450def: InstRW<[ICXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; 2451 2452def ICXWriteResGroup262 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2453 let Latency = 74; 2454 let NumMicroOps = 36; 2455 let ResourceCycles = [17,11,1,7]; 2456} 2457def: InstRW<[ICXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; 2458 2459def ICXWriteResGroup263 : SchedWriteRes<[ICXPort5,ICXPort05,ICXPort0156]> { 2460 let Latency = 75; 2461 let NumMicroOps = 15; 2462 let ResourceCycles = [6,3,6]; 2463} 2464def: InstRW<[ICXWriteResGroup263], (instrs FNINIT)>; 2465 2466def ICXWriteResGroup266 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort237,ICXPort06,ICXPort0156]> { 2467 let Latency = 106; 2468 let NumMicroOps = 100; 2469 let ResourceCycles = [9,1,11,16,1,11,21,30]; 2470} 2471def: InstRW<[ICXWriteResGroup266], (instrs FSTENVm)>; 2472 2473def ICXWriteResGroup267 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 2474 let Latency = 140; 2475 let NumMicroOps = 4; 2476 let ResourceCycles = [1,3]; 2477} 2478def: InstRW<[ICXWriteResGroup267], (instrs PAUSE)>; 2479 2480def: InstRW<[WriteZero], (instrs CLC)>; 2481 2482 2483// Instruction variants handled by the renamer. These might not need execution 2484// ports in certain conditions. 2485// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 2486// section "Skylake Pipeline" > "Register allocation and renaming". 2487// These can be investigated with llvm-exegesis, e.g. 2488// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2489// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2490 2491def ICXWriteZeroLatency : SchedWriteRes<[]> { 2492 let Latency = 0; 2493} 2494 2495def ICXWriteZeroIdiom : SchedWriteVariant<[ 2496 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2497 SchedVar<NoSchedPred, [WriteALU]> 2498]>; 2499def : InstRW<[ICXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 2500 XOR32rr, XOR64rr)>; 2501 2502def ICXWriteFZeroIdiom : SchedWriteVariant<[ 2503 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2504 SchedVar<NoSchedPred, [WriteFLogic]> 2505]>; 2506def : InstRW<[ICXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, 2507 XORPDrr, VXORPDrr, 2508 VXORPSZ128rr, 2509 VXORPDZ128rr)>; 2510 2511def ICXWriteFZeroIdiomY : SchedWriteVariant<[ 2512 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2513 SchedVar<NoSchedPred, [WriteFLogicY]> 2514]>; 2515def : InstRW<[ICXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, 2516 VXORPSZ256rr, VXORPDZ256rr)>; 2517 2518def ICXWriteFZeroIdiomZ : SchedWriteVariant<[ 2519 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2520 SchedVar<NoSchedPred, [WriteFLogicZ]> 2521]>; 2522def : InstRW<[ICXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; 2523 2524def ICXWriteVZeroIdiomLogicX : SchedWriteVariant<[ 2525 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2526 SchedVar<NoSchedPred, [WriteVecLogicX]> 2527]>; 2528def : InstRW<[ICXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, 2529 VPXORDZ128rr, VPXORQZ128rr)>; 2530 2531def ICXWriteVZeroIdiomLogicY : SchedWriteVariant<[ 2532 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2533 SchedVar<NoSchedPred, [WriteVecLogicY]> 2534]>; 2535def : InstRW<[ICXWriteVZeroIdiomLogicY], (instrs VPXORYrr, 2536 VPXORDZ256rr, VPXORQZ256rr)>; 2537 2538def ICXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ 2539 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2540 SchedVar<NoSchedPred, [WriteVecLogicZ]> 2541]>; 2542def : InstRW<[ICXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; 2543 2544def ICXWriteVZeroIdiomALUX : SchedWriteVariant<[ 2545 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2546 SchedVar<NoSchedPred, [WriteVecALUX]> 2547]>; 2548def : InstRW<[ICXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 2549 PCMPGTDrr, VPCMPGTDrr, 2550 PCMPGTWrr, VPCMPGTWrr)>; 2551 2552def ICXWriteVZeroIdiomALUY : SchedWriteVariant<[ 2553 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2554 SchedVar<NoSchedPred, [WriteVecALUY]> 2555]>; 2556def : InstRW<[ICXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 2557 VPCMPGTDYrr, 2558 VPCMPGTWYrr)>; 2559 2560def ICXWritePSUB : SchedWriteRes<[ICXPort015]> { 2561 let Latency = 1; 2562 let NumMicroOps = 1; 2563 let ResourceCycles = [1]; 2564} 2565 2566def ICXWriteVZeroIdiomPSUB : SchedWriteVariant<[ 2567 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2568 SchedVar<NoSchedPred, [ICXWritePSUB]> 2569]>; 2570 2571def : InstRW<[ICXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, 2572 PSUBDrr, VPSUBDrr, VPSUBDZ128rr, 2573 PSUBQrr, VPSUBQrr, VPSUBQZ128rr, 2574 PSUBWrr, VPSUBWrr, VPSUBWZ128rr, 2575 VPSUBBYrr, VPSUBBZ256rr, 2576 VPSUBDYrr, VPSUBDZ256rr, 2577 VPSUBQYrr, VPSUBQZ256rr, 2578 VPSUBWYrr, VPSUBWZ256rr, 2579 VPSUBBZrr, 2580 VPSUBDZrr, 2581 VPSUBQZrr, 2582 VPSUBWZrr)>; 2583def ICXWritePCMPGTQ : SchedWriteRes<[ICXPort5]> { 2584 let Latency = 3; 2585 let NumMicroOps = 1; 2586 let ResourceCycles = [1]; 2587} 2588 2589def ICXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 2590 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2591 SchedVar<NoSchedPred, [ICXWritePCMPGTQ]> 2592]>; 2593def : InstRW<[ICXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 2594 VPCMPGTQYrr)>; 2595 2596 2597// CMOVs that use both Z and C flag require an extra uop. 2598def ICXWriteCMOVA_CMOVBErr : SchedWriteRes<[ICXPort06]> { 2599 let Latency = 2; 2600 let ResourceCycles = [2]; 2601 let NumMicroOps = 2; 2602} 2603 2604def ICXWriteCMOVA_CMOVBErm : SchedWriteRes<[ICXPort23,ICXPort06]> { 2605 let Latency = 7; 2606 let ResourceCycles = [1,2]; 2607 let NumMicroOps = 3; 2608} 2609 2610def ICXCMOVA_CMOVBErr : SchedWriteVariant<[ 2611 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [ICXWriteCMOVA_CMOVBErr]>, 2612 SchedVar<NoSchedPred, [WriteCMOV]> 2613]>; 2614 2615def ICXCMOVA_CMOVBErm : SchedWriteVariant<[ 2616 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [ICXWriteCMOVA_CMOVBErm]>, 2617 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 2618]>; 2619 2620def : InstRW<[ICXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 2621def : InstRW<[ICXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 2622 2623// SETCCs that use both Z and C flag require an extra uop. 2624def ICXWriteSETA_SETBEr : SchedWriteRes<[ICXPort06]> { 2625 let Latency = 2; 2626 let ResourceCycles = [2]; 2627 let NumMicroOps = 2; 2628} 2629 2630def ICXWriteSETA_SETBEm : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06]> { 2631 let Latency = 3; 2632 let ResourceCycles = [1,1,2]; 2633 let NumMicroOps = 4; 2634} 2635 2636def ICXSETA_SETBErr : SchedWriteVariant<[ 2637 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [ICXWriteSETA_SETBEr]>, 2638 SchedVar<NoSchedPred, [WriteSETCC]> 2639]>; 2640 2641def ICXSETA_SETBErm : SchedWriteVariant<[ 2642 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [ICXWriteSETA_SETBEm]>, 2643 SchedVar<NoSchedPred, [WriteSETCCStore]> 2644]>; 2645 2646def : InstRW<[ICXSETA_SETBErr], (instrs SETCCr)>; 2647def : InstRW<[ICXSETA_SETBErm], (instrs SETCCm)>; 2648 2649/////////////////////////////////////////////////////////////////////////////// 2650// Dependency breaking instructions. 2651/////////////////////////////////////////////////////////////////////////////// 2652 2653def : IsZeroIdiomFunction<[ 2654 // GPR Zero-idioms. 2655 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 2656 2657 // SSE Zero-idioms. 2658 DepBreakingClass<[ 2659 // fp variants. 2660 XORPSrr, XORPDrr, 2661 2662 // int variants. 2663 PXORrr, 2664 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 2665 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 2666 ], ZeroIdiomPredicate>, 2667 2668 // AVX Zero-idioms. 2669 DepBreakingClass<[ 2670 // xmm fp variants. 2671 VXORPSrr, VXORPDrr, 2672 2673 // xmm int variants. 2674 VPXORrr, 2675 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 2676 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 2677 2678 // ymm variants. 2679 VXORPSYrr, VXORPDYrr, VPXORYrr, 2680 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 2681 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr, 2682 2683 // zmm variants. 2684 VXORPSZrr, VXORPDZrr, VPXORDZrr, VPXORQZrr, 2685 VXORPSZ128rr, VXORPDZ128rr, VPXORDZ128rr, VPXORQZ128rr, 2686 VXORPSZ256rr, VXORPDZ256rr, VPXORDZ256rr, VPXORQZ256rr, 2687 VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr, 2688 VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr, 2689 VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr, 2690 ], ZeroIdiomPredicate>, 2691]>; 2692 2693} // SchedModel 2694