1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the schedule class data for the Intel Atom 10// in order (Saltwell-32nm/Bonnell-45nm) processors. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// Scheduling information derived from the "Intel 64 and IA32 Architectures 16// Optimization Reference Manual", Chapter 13, Section 4. 17 18// Atom machine model. 19def AtomModel : SchedMachineModel { 20 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 21 let MicroOpBufferSize = 0; // In-order execution, always hide latency. 22 let LoadLatency = 3; // Expected cycles, may be overriden. 23 let HighLatency = 30;// Expected, may be overriden. 24 25 // On the Atom, the throughput for taken branches is 2 cycles. For small 26 // simple loops, expand by a small factor to hide the backedge cost. 27 let LoopMicroOpBufferSize = 10; 28 let PostRAScheduler = 1; 29 let CompleteModel = 0; 30} 31 32let SchedModel = AtomModel in { 33 34// Functional Units 35def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store 36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide 37def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA 38 // SIMD/FP: SIMD ALU, FP Adder 39 40// NOTE: This is for ops that can use EITHER port, not for ops that require BOTH ports. 41def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; 42 43// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 44// cycles after the memory operand. 45def : ReadAdvance<ReadAfterLd, 3>; 46def : ReadAdvance<ReadAfterVecLd, 3>; 47def : ReadAdvance<ReadAfterVecXLd, 3>; 48def : ReadAdvance<ReadAfterVecYLd, 3>; 49 50def : ReadAdvance<ReadInt2Fpu, 0>; 51 52// This multiclass defines the resource usage for variants with and without 53// folded loads. 54multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW, 55 list<ProcResourceKind> RRPorts, 56 list<ProcResourceKind> RMPorts, 57 int RRLat = 1, int RMLat = 1, 58 list<int> RRRes = [1], 59 list<int> RMRes = [1]> { 60 // Register variant. 61 def : WriteRes<SchedRW, RRPorts> { 62 let Latency = RRLat; 63 let ResourceCycles = RRRes; 64 } 65 66 // Memory variant. 67 def : WriteRes<SchedRW.Folded, RMPorts> { 68 let Latency = RMLat; 69 let ResourceCycles = RMRes; 70 } 71} 72 73// A folded store needs a cycle on Port0 for the store data. 74def : WriteRes<WriteRMW, [AtomPort0]>; 75 76//////////////////////////////////////////////////////////////////////////////// 77// Arithmetic. 78//////////////////////////////////////////////////////////////////////////////// 79 80defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>; 81defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>; 82 83defm : AtomWriteResPair<WriteIMul8, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>; 84defm : AtomWriteResPair<WriteIMul16, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 85defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 86defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 87defm : AtomWriteResPair<WriteIMul32, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 88defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 89defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 90defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 91defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>; 92defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 93defm : X86WriteResUnsupported<WriteIMulH>; 94 95defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>; 96defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>; 97defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>; 98defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>; 99defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>; 100 101defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>; 102defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 103defm : AtomWriteResPair<WriteDiv32, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 104defm : AtomWriteResPair<WriteDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 105defm : AtomWriteResPair<WriteIDiv8, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 106defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 107defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 108defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 109 110defm : X86WriteResPairUnsupported<WriteCRC32>; 111 112defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>; 113defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move. 114 115def : WriteRes<WriteSETCC, [AtomPort01]>; 116def : WriteRes<WriteSETCCStore, [AtomPort01]> { 117 let Latency = 2; 118 let ResourceCycles = [2]; 119} 120def : WriteRes<WriteLAHFSAHF, [AtomPort01]> { 121 let Latency = 2; 122 let ResourceCycles = [2]; 123} 124defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>; 125defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>; 126defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>; 127defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>; 128//defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>; 129//defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>; 130 131// This is for simple LEAs with one or two input operands. 132def : WriteRes<WriteLEA, [AtomPort1]>; 133 134// Bit counts. 135defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 136defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 137defm : X86WriteResPairUnsupported<WritePOPCNT>; 138defm : X86WriteResPairUnsupported<WriteLZCNT>; 139defm : X86WriteResPairUnsupported<WriteTZCNT>; 140 141// BMI1 BEXTR/BLS, BMI2 BZHI 142defm : X86WriteResPairUnsupported<WriteBEXTR>; 143defm : X86WriteResPairUnsupported<WriteBLS>; 144defm : X86WriteResPairUnsupported<WriteBZHI>; 145 146//////////////////////////////////////////////////////////////////////////////// 147// Integer shifts and rotates. 148//////////////////////////////////////////////////////////////////////////////// 149 150defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>; 151defm : AtomWriteResPair<WriteShiftCL, [AtomPort0], [AtomPort0]>; 152defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>; 153defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>; 154 155defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>; 156defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>; 157defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>; 158defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>; 159 160//////////////////////////////////////////////////////////////////////////////// 161// Loads, stores, and moves, not folded with other operations. 162//////////////////////////////////////////////////////////////////////////////// 163 164def : WriteRes<WriteLoad, [AtomPort0]>; 165def : WriteRes<WriteStore, [AtomPort0]>; 166def : WriteRes<WriteStoreNT, [AtomPort0]>; 167def : WriteRes<WriteMove, [AtomPort01]>; 168defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>; 169 170// Treat misc copies as a move. 171def : InstRW<[WriteMove], (instrs COPY)>; 172 173//////////////////////////////////////////////////////////////////////////////// 174// Idioms that clear a register, like xorps %xmm0, %xmm0. 175// These can often bypass execution ports completely. 176//////////////////////////////////////////////////////////////////////////////// 177 178def : WriteRes<WriteZero, []>; 179 180//////////////////////////////////////////////////////////////////////////////// 181// Branches don't produce values, so they have no latency, but they still 182// consume resources. Indirect branches can fold loads. 183//////////////////////////////////////////////////////////////////////////////// 184 185defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>; 186 187//////////////////////////////////////////////////////////////////////////////// 188// Special case scheduling classes. 189//////////////////////////////////////////////////////////////////////////////// 190 191def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; } 192def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; } 193def : WriteRes<WriteFence, [AtomPort0]>; 194 195// Nops don't have dependencies, so there's no actual latency, but we set this 196// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. 197def : WriteRes<WriteNop, [AtomPort01]>; 198 199//////////////////////////////////////////////////////////////////////////////// 200// Floating point. This covers both scalar and vector operations. 201//////////////////////////////////////////////////////////////////////////////// 202 203defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>; 204defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>; 205def : WriteRes<WriteFLoad, [AtomPort0]>; 206def : WriteRes<WriteFLoadX, [AtomPort0]>; 207defm : X86WriteResUnsupported<WriteFLoadY>; 208defm : X86WriteResUnsupported<WriteFMaskedLoad>; 209defm : X86WriteResUnsupported<WriteFMaskedLoadY>; 210 211def : WriteRes<WriteFStore, [AtomPort0]>; 212def : WriteRes<WriteFStoreX, [AtomPort0]>; 213defm : X86WriteResUnsupported<WriteFStoreY>; 214def : WriteRes<WriteFStoreNT, [AtomPort0]>; 215def : WriteRes<WriteFStoreNTX, [AtomPort0]>; 216defm : X86WriteResUnsupported<WriteFStoreNTY>; 217defm : X86WriteResUnsupported<WriteFMaskedStore32>; 218defm : X86WriteResUnsupported<WriteFMaskedStore32Y>; 219defm : X86WriteResUnsupported<WriteFMaskedStore64>; 220defm : X86WriteResUnsupported<WriteFMaskedStore64Y>; 221 222def : WriteRes<WriteFMove, [AtomPort01]>; 223def : WriteRes<WriteFMoveX, [AtomPort01]>; 224defm : X86WriteResUnsupported<WriteFMoveY>; 225 226defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>; 227 228defm : AtomWriteResPair<WriteFAdd, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 229defm : AtomWriteResPair<WriteFAddX, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 230defm : X86WriteResPairUnsupported<WriteFAddY>; 231defm : X86WriteResPairUnsupported<WriteFAddZ>; 232defm : AtomWriteResPair<WriteFAdd64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 233defm : AtomWriteResPair<WriteFAdd64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 234defm : X86WriteResPairUnsupported<WriteFAdd64Y>; 235defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 236defm : AtomWriteResPair<WriteFCmp, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 237defm : AtomWriteResPair<WriteFCmpX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 238defm : X86WriteResPairUnsupported<WriteFCmpY>; 239defm : X86WriteResPairUnsupported<WriteFCmpZ>; 240defm : AtomWriteResPair<WriteFCmp64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 241defm : AtomWriteResPair<WriteFCmp64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 242defm : X86WriteResPairUnsupported<WriteFCmp64Y>; 243defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 244defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 245defm : AtomWriteResPair<WriteFComX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 246defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [2], [2]>; 247defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 248defm : X86WriteResPairUnsupported<WriteFMulY>; 249defm : X86WriteResPairUnsupported<WriteFMulZ>; 250defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 251defm : AtomWriteResPair<WriteFMul64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9], [10,10]>; 252defm : X86WriteResPairUnsupported<WriteFMul64Y>; 253defm : X86WriteResPairUnsupported<WriteFMul64Z>; 254defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 255defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 256defm : X86WriteResPairUnsupported<WriteFRcpY>; 257defm : X86WriteResPairUnsupported<WriteFRcpZ>; 258defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 259defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 260defm : X86WriteResPairUnsupported<WriteFRsqrtY>; 261defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 262defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 263defm : AtomWriteResPair<WriteFDivX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 264defm : X86WriteResPairUnsupported<WriteFDivY>; 265defm : X86WriteResPairUnsupported<WriteFDivZ>; 266defm : AtomWriteResPair<WriteFDiv64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 267defm : AtomWriteResPair<WriteFDiv64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 268defm : X86WriteResPairUnsupported<WriteFDiv64Y>; 269defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 270defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 271defm : AtomWriteResPair<WriteFSqrtX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 272defm : X86WriteResPairUnsupported<WriteFSqrtY>; 273defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 274defm : AtomWriteResPair<WriteFSqrt64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 275defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 276defm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 277defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 278defm : AtomWriteResPair<WriteFSqrt80, [AtomPort01], [AtomPort01], 71, 71, [71], [71]>; 279defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>; 280defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 281defm : X86WriteResPairUnsupported<WriteFRndY>; 282defm : X86WriteResPairUnsupported<WriteFRndZ>; 283defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>; 284defm : X86WriteResPairUnsupported<WriteFLogicY>; 285defm : X86WriteResPairUnsupported<WriteFLogicZ>; 286defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>; 287defm : X86WriteResPairUnsupported<WriteFTestY>; 288defm : X86WriteResPairUnsupported<WriteFTestZ>; 289defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>; 290defm : X86WriteResPairUnsupported<WriteFShuffleY>; 291defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 292defm : X86WriteResPairUnsupported<WriteFVarShuffle>; 293defm : X86WriteResPairUnsupported<WriteFVarShuffleY>; 294defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 295defm : X86WriteResPairUnsupported<WriteFMA>; 296defm : X86WriteResPairUnsupported<WriteFMAX>; 297defm : X86WriteResPairUnsupported<WriteFMAY>; 298defm : X86WriteResPairUnsupported<WriteFMAZ>; 299defm : X86WriteResPairUnsupported<WriteDPPD>; 300defm : X86WriteResPairUnsupported<WriteDPPS>; 301defm : X86WriteResPairUnsupported<WriteDPPSY>; 302defm : X86WriteResPairUnsupported<WriteDPPSZ>; 303defm : X86WriteResPairUnsupported<WriteFBlend>; 304defm : X86WriteResPairUnsupported<WriteFBlendY>; 305defm : X86WriteResPairUnsupported<WriteFBlendZ>; 306defm : X86WriteResPairUnsupported<WriteFVarBlend>; 307defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 308defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 309defm : X86WriteResPairUnsupported<WriteFShuffle256>; 310defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 311 312//////////////////////////////////////////////////////////////////////////////// 313// Conversions. 314//////////////////////////////////////////////////////////////////////////////// 315 316defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [7,7], [6,6]>; 317defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 318defm : X86WriteResPairUnsupported<WriteCvtPS2IY>; 319defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 320defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [7,7], [6,6]>; 321defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7]>; 322defm : X86WriteResPairUnsupported<WriteCvtPD2IY>; 323defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 324 325defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 326defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 327defm : X86WriteResPairUnsupported<WriteCvtI2PSY>; 328defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 329defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 330defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7]>; 331defm : X86WriteResPairUnsupported<WriteCvtI2PDY>; 332defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 333 334defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 335defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7]>; 336defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>; 337defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 338defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6]>; 339defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7]>; 340defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>; 341defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 342 343defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 344defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 345defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 346defm : X86WriteResUnsupported<WriteCvtPS2PH>; 347defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 348defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 349defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 350defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 351defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 352 353//////////////////////////////////////////////////////////////////////////////// 354// Vector integer operations. 355//////////////////////////////////////////////////////////////////////////////// 356 357def : WriteRes<WriteVecLoad, [AtomPort0]>; 358def : WriteRes<WriteVecLoadX, [AtomPort0]>; 359defm : X86WriteResUnsupported<WriteVecLoadY>; 360def : WriteRes<WriteVecLoadNT, [AtomPort0]>; 361defm : X86WriteResUnsupported<WriteVecLoadNTY>; 362defm : X86WriteResUnsupported<WriteVecMaskedLoad>; 363defm : X86WriteResUnsupported<WriteVecMaskedLoadY>; 364 365def : WriteRes<WriteVecStore, [AtomPort0]>; 366def : WriteRes<WriteVecStoreX, [AtomPort0]>; 367defm : X86WriteResUnsupported<WriteVecStoreY>; 368def : WriteRes<WriteVecStoreNT, [AtomPort0]>; 369defm : X86WriteResUnsupported<WriteVecStoreNTY>; 370defm : X86WriteResUnsupported<WriteVecMaskedStore32>; 371defm : X86WriteResUnsupported<WriteVecMaskedStore64>; 372defm : X86WriteResUnsupported<WriteVecMaskedStore32Y>; 373defm : X86WriteResUnsupported<WriteVecMaskedStore64Y>; 374 375def : WriteRes<WriteVecMove, [AtomPort0]>; 376def : WriteRes<WriteVecMoveX, [AtomPort01]>; 377defm : X86WriteResUnsupported<WriteVecMoveY>; 378defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>; 379defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>; 380 381defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>; 382defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>; 383defm : X86WriteResPairUnsupported<WriteVecALUY>; 384defm : X86WriteResPairUnsupported<WriteVecALUZ>; 385defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>; 386defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>; 387defm : X86WriteResPairUnsupported<WriteVecLogicY>; 388defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 389defm : X86WriteResPairUnsupported<WriteVecTest>; 390defm : X86WriteResPairUnsupported<WriteVecTestY>; 391defm : X86WriteResPairUnsupported<WriteVecTestZ>; 392defm : AtomWriteResPair<WriteVecShift, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 2, 3, [1,1], [2,2]>; 393defm : AtomWriteResPair<WriteVecShiftX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 2, 3, [1,1], [2,2]>; 394defm : X86WriteResPairUnsupported<WriteVecShiftY>; 395defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 396defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort0], [AtomPort0], 1, 1>; 397defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort0], [AtomPort0], 1, 1>; 398defm : X86WriteResPairUnsupported<WriteVecShiftImmY>; 399defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 400defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>; 401defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 402defm : X86WriteResPairUnsupported<WriteVecIMulY>; 403defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 404defm : X86WriteResPairUnsupported<WritePMULLD>; 405defm : X86WriteResPairUnsupported<WritePMULLDY>; 406defm : X86WriteResPairUnsupported<WritePMULLDZ>; 407defm : X86WriteResPairUnsupported<WritePHMINPOS>; 408defm : X86WriteResPairUnsupported<WriteMPSAD>; 409defm : X86WriteResPairUnsupported<WriteMPSADY>; 410defm : X86WriteResPairUnsupported<WriteMPSADZ>; 411defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>; 412defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 413defm : X86WriteResPairUnsupported<WritePSADBWY>; 414defm : X86WriteResPairUnsupported<WritePSADBWZ>; 415defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>; 416defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>; 417defm : X86WriteResPairUnsupported<WriteShuffleY>; 418defm : X86WriteResPairUnsupported<WriteShuffleZ>; 419defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>; 420defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 4, 5, [3,3], [4,4]>; 421defm : X86WriteResPairUnsupported<WriteVarShuffleY>; 422defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 423defm : X86WriteResPairUnsupported<WriteBlend>; 424defm : X86WriteResPairUnsupported<WriteBlendY>; 425defm : X86WriteResPairUnsupported<WriteBlendZ>; 426defm : X86WriteResPairUnsupported<WriteVarBlend>; 427defm : X86WriteResPairUnsupported<WriteVarBlendY>; 428defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 429defm : X86WriteResPairUnsupported<WriteShuffle256>; 430defm : X86WriteResPairUnsupported<WriteVPMOV256>; 431defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 432defm : X86WriteResPairUnsupported<WriteVarVecShift>; 433defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 434defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 435 436//////////////////////////////////////////////////////////////////////////////// 437// Vector insert/extract operations. 438//////////////////////////////////////////////////////////////////////////////// 439 440defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>; 441def : WriteRes<WriteVecExtract, [AtomPort0]>; 442def : WriteRes<WriteVecExtractSt, [AtomPort0]>; 443 444//////////////////////////////////////////////////////////////////////////////// 445// SSE42 String instructions. 446//////////////////////////////////////////////////////////////////////////////// 447 448defm : X86WriteResPairUnsupported<WritePCmpIStrI>; 449defm : X86WriteResPairUnsupported<WritePCmpIStrM>; 450defm : X86WriteResPairUnsupported<WritePCmpEStrI>; 451defm : X86WriteResPairUnsupported<WritePCmpEStrM>; 452 453//////////////////////////////////////////////////////////////////////////////// 454// MOVMSK Instructions. 455//////////////////////////////////////////////////////////////////////////////// 456 457def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 458def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 459defm : X86WriteResUnsupported<WriteVecMOVMSKY>; 460def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 461 462//////////////////////////////////////////////////////////////////////////////// 463// AES instructions. 464//////////////////////////////////////////////////////////////////////////////// 465 466defm : X86WriteResPairUnsupported<WriteAESIMC>; 467defm : X86WriteResPairUnsupported<WriteAESKeyGen>; 468defm : X86WriteResPairUnsupported<WriteAESDecEnc>; 469 470//////////////////////////////////////////////////////////////////////////////// 471// Horizontal add/sub instructions. 472//////////////////////////////////////////////////////////////////////////////// 473 474defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 475defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 476defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 3, 4, [3], [4]>; 477defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 478defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 479 480//////////////////////////////////////////////////////////////////////////////// 481// Carry-less multiplication instructions. 482//////////////////////////////////////////////////////////////////////////////// 483 484defm : X86WriteResPairUnsupported<WriteCLMul>; 485 486//////////////////////////////////////////////////////////////////////////////// 487// Load/store MXCSR. 488//////////////////////////////////////////////////////////////////////////////// 489 490def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; } 491def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; } 492 493//////////////////////////////////////////////////////////////////////////////// 494// Special Cases. 495//////////////////////////////////////////////////////////////////////////////// 496 497// Port0 498def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { 499 let Latency = 1; 500 let ResourceCycles = [1]; 501} 502def : InstRW<[AtomWrite0_1], (instrs XAM_F, LD_Frr, 503 MOVSX64rr32)>; 504def : SchedAlias<WriteALURMW, AtomWrite0_1>; 505def : SchedAlias<WriteADCRMW, AtomWrite0_1>; 506def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", 507 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; 508 509// Port1 510def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { 511 let Latency = 1; 512 let ResourceCycles = [1]; 513} 514def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; 515def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>; 516 517def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { 518 let Latency = 5; 519 let ResourceCycles = [5]; 520} 521def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm, 522 MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>; 523 524// Port0 and Port1 525def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { 526 let Latency = 1; 527 let ResourceCycles = [1, 1]; 528} 529def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, 530 POP16rmr, POP32rmr, POP64rmr, 531 PUSH16r, PUSH32r, PUSH64r, 532 PUSHi16, PUSHi32, 533 PUSH16rmr, PUSH32rmr, PUSH64rmr, 534 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, 535 XCH_F)>; 536def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", 537 "IRET(16|32|64)?")>; 538 539def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { 540 let Latency = 5; 541 let ResourceCycles = [5, 5]; 542} 543def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; 544def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; 545 546// Port0 or Port1 547def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { 548 let Latency = 1; 549 let ResourceCycles = [1]; 550} 551def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, 552 LFENCE, 553 STOSB, STOSL, STOSQ, STOSW, 554 MOVSSrr, MOVSSrr_REV, 555 PSLLDQri, PSRLDQri)>; 556def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr", 557 "MMX_PUNPCKH(BW|DQ|WD)irr")>; 558 559def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { 560 let Latency = 2; 561 let ResourceCycles = [2]; 562} 563def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, 564 PUSH16rmm, PUSH32rmm, PUSH64rmm, 565 LODSB, LODSL, LODSQ, LODSW, 566 SCASB, SCASL, SCASQ, SCASW)>; 567def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", 568 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", 569 "MMX_P(ADD|SUB)Qirr", 570 "MOV(S|Z)X16rr8", 571 "MOV(UPS|UPD|DQU)mr", 572 "MASKMOVDQU(64)?", 573 "P(ADD|SUB)Qrr")>; 574def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>; 575 576def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { 577 let Latency = 3; 578 let ResourceCycles = [3]; 579} 580def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, 581 CMPSB, CMPSL, CMPSQ, CMPSW, 582 MOVSB, MOVSL, MOVSQ, MOVSW, 583 POP16rmm, POP32rmm, POP64rmm)>; 584def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", 585 "XCHG(8|16|32|64)rm", 586 "PH(ADD|SUB)Drr", 587 "MOV(S|Z)X16rm8", 588 "MMX_P(ADD|SUB)Qirm", 589 "MOV(UPS|UPD|DQU)rm", 590 "P(ADD|SUB)Qrm")>; 591 592def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { 593 let Latency = 4; 594 let ResourceCycles = [4]; 595} 596def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, 597 JCXZ, JECXZ, JRCXZ, 598 LD_F80m)>; 599def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", 600 "(MMX_)?PEXTRWrr(_REV)?")>; 601 602def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { 603 let Latency = 5; 604 let ResourceCycles = [5]; 605} 606def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; 607def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; 608 609def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { 610 let Latency = 6; 611 let ResourceCycles = [6]; 612} 613def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, 614 SHLD16rrCL, SHRD16rrCL, 615 SHLD16rri8, SHRD16rri8, 616 SHLD16mrCL, SHRD16mrCL, 617 SHLD16mri8, SHRD16mri8)>; 618def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m", 619 "MMX_PH(ADD|SUB)S?Wrm")>; 620 621def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { 622 let Latency = 7; 623 let ResourceCycles = [7]; 624} 625def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; 626 627def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { 628 let Latency = 8; 629 let ResourceCycles = [8]; 630} 631def : InstRW<[AtomWrite01_8], (instrs LOOPE, 632 PUSHA16, PUSHA32, 633 SHLD64rrCL, SHRD64rrCL, 634 FNSTCW16m)>; 635 636def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { 637 let Latency = 9; 638 let ResourceCycles = [9]; 639} 640def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32, 641 PUSHF16, PUSHF32, PUSHF64, 642 SHLD64mrCL, SHRD64mrCL, 643 SHLD64mri8, SHRD64mri8, 644 SHLD64rri8, SHRD64rri8, 645 CMPXCHG8rr)>; 646def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F", 647 "(U)?COMIS(D|S)rr", 648 "CVT(T)?SS2SI64rr(_Int)?")>; 649 650def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { 651 let Latency = 10; 652 let ResourceCycles = [10]; 653} 654def : SchedAlias<WriteFLDC, AtomWrite01_10>; 655def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm", 656 "CVT(T)?SS2SI64rm(_Int)?")>; 657 658def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { 659 let Latency = 11; 660 let ResourceCycles = [11]; 661} 662def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; 663def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>; 664 665def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { 666 let Latency = 13; 667 let ResourceCycles = [13]; 668} 669def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; 670 671def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { 672 let Latency = 14; 673 let ResourceCycles = [14]; 674} 675def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; 676 677def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { 678 let Latency = 17; 679 let ResourceCycles = [17]; 680} 681def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; 682 683def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { 684 let Latency = 18; 685 let ResourceCycles = [18]; 686} 687def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; 688 689def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { 690 let Latency = 20; 691 let ResourceCycles = [20]; 692} 693def : InstRW<[AtomWrite01_20], (instrs DAS)>; 694 695def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { 696 let Latency = 21; 697 let ResourceCycles = [21]; 698} 699def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; 700 701def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { 702 let Latency = 22; 703 let ResourceCycles = [22]; 704} 705def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; 706 707def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { 708 let Latency = 23; 709 let ResourceCycles = [23]; 710} 711def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; 712 713def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { 714 let Latency = 25; 715 let ResourceCycles = [25]; 716} 717def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; 718 719def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { 720 let Latency = 26; 721 let ResourceCycles = [26]; 722} 723def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; 724 725def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { 726 let Latency = 29; 727 let ResourceCycles = [29]; 728} 729def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; 730 731def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { 732 let Latency = 30; 733 let ResourceCycles = [30]; 734} 735def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; 736 737def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { 738 let Latency = 32; 739 let ResourceCycles = [32]; 740} 741def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; 742 743def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { 744 let Latency = 45; 745 let ResourceCycles = [45]; 746} 747def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>; 748 749def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { 750 let Latency = 46; 751 let ResourceCycles = [46]; 752} 753def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; 754 755def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { 756 let Latency = 48; 757 let ResourceCycles = [48]; 758} 759def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; 760 761def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { 762 let Latency = 55; 763 let ResourceCycles = [55]; 764} 765def : InstRW<[AtomWrite01_55], (instrs FPREM)>; 766 767def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { 768 let Latency = 59; 769 let ResourceCycles = [59]; 770} 771def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; 772 773def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { 774 let Latency = 63; 775 let ResourceCycles = [63]; 776} 777def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; 778 779def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { 780 let Latency = 68; 781 let ResourceCycles = [68]; 782} 783def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; 784 785def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { 786 let Latency = 71; 787 let ResourceCycles = [71]; 788} 789def : InstRW<[AtomWrite01_71], (instrs FPREM1, 790 INVLPG, INVLPGA32, INVLPGA64)>; 791 792def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { 793 let Latency = 72; 794 let ResourceCycles = [72]; 795} 796def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; 797 798def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { 799 let Latency = 74; 800 let ResourceCycles = [74]; 801} 802def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; 803 804def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { 805 let Latency = 77; 806 let ResourceCycles = [77]; 807} 808def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; 809 810def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { 811 let Latency = 78; 812 let ResourceCycles = [78]; 813} 814def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; 815 816def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { 817 let Latency = 79; 818 let ResourceCycles = [79]; 819} 820def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", 821 "LRETI?(L|Q|W)")>; 822 823def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { 824 let Latency = 92; 825 let ResourceCycles = [92]; 826} 827def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; 828 829def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { 830 let Latency = 94; 831 let ResourceCycles = [94]; 832} 833def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; 834 835def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { 836 let Latency = 99; 837 let ResourceCycles = [99]; 838} 839def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; 840 841def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { 842 let Latency = 121; 843 let ResourceCycles = [121]; 844} 845def : InstRW<[AtomWrite01_121], (instrs CPUID)>; 846 847def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { 848 let Latency = 127; 849 let ResourceCycles = [127]; 850} 851def : InstRW<[AtomWrite01_127], (instrs INT)>; 852 853def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { 854 let Latency = 130; 855 let ResourceCycles = [130]; 856} 857def : InstRW<[AtomWrite01_130], (instrs INT3)>; 858 859def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { 860 let Latency = 140; 861 let ResourceCycles = [140]; 862} 863def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; 864 865def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { 866 let Latency = 141; 867 let ResourceCycles = [141]; 868} 869def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; 870 871def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { 872 let Latency = 146; 873 let ResourceCycles = [146]; 874} 875def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; 876 877def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { 878 let Latency = 147; 879 let ResourceCycles = [147]; 880} 881def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; 882 883def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { 884 let Latency = 168; 885 let ResourceCycles = [168]; 886} 887def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; 888 889def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { 890 let Latency = 174; 891 let ResourceCycles = [174]; 892} 893def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>; 894 895def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { 896 let Latency = 183; 897 let ResourceCycles = [183]; 898} 899def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; 900 901def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { 902 let Latency = 202; 903 let ResourceCycles = [202]; 904} 905def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; 906 907} // SchedModel 908