1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the schedule class data for the Intel Atom
10// in order (Saltwell-32nm/Bonnell-45nm) processors.
11//
12//===----------------------------------------------------------------------===//
13
14//
15// Scheduling information derived from the "Intel 64 and IA32 Architectures
16// Optimization Reference Manual", Chapter 13, Section 4.
17
18// Atom machine model.
19def AtomModel : SchedMachineModel {
20  let IssueWidth = 2;  // Allows 2 instructions per scheduling group.
21  let MicroOpBufferSize = 0; // In-order execution, always hide latency.
22  let LoadLatency = 3; // Expected cycles, may be overriden.
23  let HighLatency = 30;// Expected, may be overriden.
24
25  // On the Atom, the throughput for taken branches is 2 cycles. For small
26  // simple loops, expand by a small factor to hide the backedge cost.
27  let LoopMicroOpBufferSize = 10;
28  let PostRAScheduler = 1;
29  let CompleteModel = 0;
30}
31
32let SchedModel = AtomModel in {
33
34// Functional Units
35def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store
36                                 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
37def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA
38                                 // SIMD/FP: SIMD ALU, FP Adder
39
40def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>;
41
42// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
43// cycles after the memory operand.
44def : ReadAdvance<ReadAfterLd, 3>;
45def : ReadAdvance<ReadAfterVecLd, 3>;
46def : ReadAdvance<ReadAfterVecXLd, 3>;
47def : ReadAdvance<ReadAfterVecYLd, 3>;
48
49def : ReadAdvance<ReadInt2Fpu, 0>;
50
51// Many SchedWrites are defined in pairs with and without a folded load.
52// Instructions with folded loads are usually micro-fused, so they only appear
53// as two micro-ops when dispatched by the schedulers.
54// This multiclass defines the resource usage for variants with and without
55// folded loads.
56multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
57                            list<ProcResourceKind> RRPorts,
58                            list<ProcResourceKind> RMPorts,
59                            int RRLat = 1, int RMLat = 1,
60                            list<int> RRRes = [1],
61                            list<int> RMRes = [1]> {
62  // Register variant is using a single cycle on ExePort.
63  def : WriteRes<SchedRW, RRPorts> {
64    let Latency = RRLat;
65    let ResourceCycles = RRRes;
66  }
67
68  // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
69  // latency.
70  def : WriteRes<SchedRW.Folded, RMPorts> {
71    let Latency = RMLat;
72    let ResourceCycles = RMRes;
73  }
74}
75
76// A folded store needs a cycle on Port0 for the store data.
77def : WriteRes<WriteRMW, [AtomPort0]>;
78
79////////////////////////////////////////////////////////////////////////////////
80// Arithmetic.
81////////////////////////////////////////////////////////////////////////////////
82
83defm : AtomWriteResPair<WriteALU,    [AtomPort01], [AtomPort0]>;
84defm : AtomWriteResPair<WriteADC,    [AtomPort01], [AtomPort0]>;
85
86defm : AtomWriteResPair<WriteIMul8,     [AtomPort01], [AtomPort01],  7,  7,  [7],  [7]>;
87defm : AtomWriteResPair<WriteIMul16,    [AtomPort01], [AtomPort01],  7,  8,  [7],  [8]>;
88defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort01], [AtomPort01],  6,  7,  [6],  [7]>;
89defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort01], [AtomPort01],  6,  7,  [6],  [7]>;
90defm : AtomWriteResPair<WriteIMul32,    [AtomPort01], [AtomPort01],  6,  7,  [6],  [7]>;
91defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0],  [AtomPort0],   5,  5,  [5],  [5]>;
92defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0],  [AtomPort0],   5,  5,  [5],  [5]>;
93defm : AtomWriteResPair<WriteIMul64,    [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
94defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>;
95defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>;
96defm : X86WriteResUnsupported<WriteIMulH>;
97
98defm : X86WriteRes<WriteXCHG,        [AtomPort01], 2, [2], 1>;
99defm : X86WriteRes<WriteBSWAP32,     [AtomPort0], 1, [1], 1>;
100defm : X86WriteRes<WriteBSWAP64,     [AtomPort0], 1, [1], 1>;
101defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>;
102defm : X86WriteRes<WriteCMPXCHGRMW,   [AtomPort01, AtomPort0], 1, [1, 1], 1>;
103
104defm : AtomWriteResPair<WriteDiv8,   [AtomPort01], [AtomPort01], 50, 68, [50], [68]>;
105defm : AtomWriteResPair<WriteDiv16,  [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
106defm : AtomWriteResPair<WriteDiv32,  [AtomPort01], [AtomPort01], 50, 50, [50], [50]>;
107defm : AtomWriteResPair<WriteDiv64,  [AtomPort01], [AtomPort01],130,130,[130],[130]>;
108defm : AtomWriteResPair<WriteIDiv8,  [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
109defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
110defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
111defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>;
112
113defm : X86WriteResPairUnsupported<WriteCRC32>;
114
115defm : AtomWriteResPair<WriteCMOV,  [AtomPort01], [AtomPort0]>;
116defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move.
117
118def  : WriteRes<WriteSETCC, [AtomPort01]>;
119def  : WriteRes<WriteSETCCStore, [AtomPort01]> {
120  let Latency = 2;
121  let ResourceCycles = [2];
122}
123def  : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
124  let Latency = 2;
125  let ResourceCycles = [2];
126}
127defm : X86WriteRes<WriteBitTest,         [AtomPort1],  1, [1], 1>;
128defm : X86WriteRes<WriteBitTestImmLd,    [AtomPort0],  1, [1], 1>;
129defm : X86WriteRes<WriteBitTestRegLd,    [AtomPort01], 9, [9], 1>;
130defm : X86WriteRes<WriteBitTestSet,      [AtomPort1],  1, [1], 1>;
131//defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1],  1, [1], 1>;
132//defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1],  1, [1], 1>;
133
134// This is for simple LEAs with one or two input operands.
135def : WriteRes<WriteLEA, [AtomPort1]>;
136
137// Bit counts.
138defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
139defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>;
140defm : X86WriteResPairUnsupported<WritePOPCNT>;
141defm : X86WriteResPairUnsupported<WriteLZCNT>;
142defm : X86WriteResPairUnsupported<WriteTZCNT>;
143
144// BMI1 BEXTR/BLS, BMI2 BZHI
145defm : X86WriteResPairUnsupported<WriteBEXTR>;
146defm : X86WriteResPairUnsupported<WriteBLS>;
147defm : X86WriteResPairUnsupported<WriteBZHI>;
148
149////////////////////////////////////////////////////////////////////////////////
150// Integer shifts and rotates.
151////////////////////////////////////////////////////////////////////////////////
152
153defm : AtomWriteResPair<WriteShift,    [AtomPort0], [AtomPort0]>;
154defm : AtomWriteResPair<WriteShiftCL,  [AtomPort0], [AtomPort0]>;
155defm : AtomWriteResPair<WriteRotate,   [AtomPort0], [AtomPort0]>;
156defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>;
157
158defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>;
159defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>;
160defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>;
161defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>;
162
163////////////////////////////////////////////////////////////////////////////////
164// Loads, stores, and moves, not folded with other operations.
165////////////////////////////////////////////////////////////////////////////////
166
167def : WriteRes<WriteLoad,    [AtomPort0]>;
168def : WriteRes<WriteStore,   [AtomPort0]>;
169def : WriteRes<WriteStoreNT, [AtomPort0]>;
170def : WriteRes<WriteMove,    [AtomPort01]>;
171
172// Treat misc copies as a move.
173def : InstRW<[WriteMove], (instrs COPY)>;
174
175////////////////////////////////////////////////////////////////////////////////
176// Idioms that clear a register, like xorps %xmm0, %xmm0.
177// These can often bypass execution ports completely.
178////////////////////////////////////////////////////////////////////////////////
179
180def : WriteRes<WriteZero,  []>;
181
182////////////////////////////////////////////////////////////////////////////////
183// Branches don't produce values, so they have no latency, but they still
184// consume resources. Indirect branches can fold loads.
185////////////////////////////////////////////////////////////////////////////////
186
187defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>;
188
189////////////////////////////////////////////////////////////////////////////////
190// Special case scheduling classes.
191////////////////////////////////////////////////////////////////////////////////
192
193def : WriteRes<WriteSystem,     [AtomPort01]> { let Latency = 100; }
194def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; }
195def : WriteRes<WriteFence,      [AtomPort0]>;
196
197// Nops don't have dependencies, so there's no actual latency, but we set this
198// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
199def : WriteRes<WriteNop, [AtomPort01]>;
200
201////////////////////////////////////////////////////////////////////////////////
202// Floating point. This covers both scalar and vector operations.
203////////////////////////////////////////////////////////////////////////////////
204
205defm : X86WriteRes<WriteFLD0,       [AtomPort01], 1, [1], 1>;
206defm : X86WriteRes<WriteFLD1,       [AtomPort01], 6, [6], 1>;
207def  : WriteRes<WriteFLoad,         [AtomPort0]>;
208def  : WriteRes<WriteFLoadX,        [AtomPort0]>;
209defm : X86WriteResUnsupported<WriteFLoadY>;
210defm : X86WriteResUnsupported<WriteFMaskedLoad>;
211defm : X86WriteResUnsupported<WriteFMaskedLoadY>;
212
213def  : WriteRes<WriteFStore,        [AtomPort0]>;
214def  : WriteRes<WriteFStoreX,       [AtomPort0]>;
215defm : X86WriteResUnsupported<WriteFStoreY>;
216def  : WriteRes<WriteFStoreNT,      [AtomPort0]>;
217def  : WriteRes<WriteFStoreNTX,     [AtomPort0]>;
218defm : X86WriteResUnsupported<WriteFStoreNTY>;
219defm : X86WriteResUnsupported<WriteFMaskedStore32>;
220defm : X86WriteResUnsupported<WriteFMaskedStore32Y>;
221defm : X86WriteResUnsupported<WriteFMaskedStore64>;
222defm : X86WriteResUnsupported<WriteFMaskedStore64Y>;
223
224def  : WriteRes<WriteFMove,         [AtomPort01]>;
225def  : WriteRes<WriteFMoveX,        [AtomPort01]>;
226defm : X86WriteResUnsupported<WriteFMoveY>;
227
228defm : X86WriteRes<WriteEMMS,       [AtomPort01], 5, [5], 1>;
229
230defm : AtomWriteResPair<WriteFAdd,           [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
231defm : AtomWriteResPair<WriteFAddX,          [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
232defm : X86WriteResPairUnsupported<WriteFAddY>;
233defm : X86WriteResPairUnsupported<WriteFAddZ>;
234defm : AtomWriteResPair<WriteFAdd64,         [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
235defm : AtomWriteResPair<WriteFAdd64X,       [AtomPort01], [AtomPort01],  6,  7,  [6],  [7]>;
236defm : X86WriteResPairUnsupported<WriteFAdd64Y>;
237defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
238defm : AtomWriteResPair<WriteFCmp,           [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
239defm : AtomWriteResPair<WriteFCmpX,          [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
240defm : X86WriteResPairUnsupported<WriteFCmpY>;
241defm : X86WriteResPairUnsupported<WriteFCmpZ>;
242defm : AtomWriteResPair<WriteFCmp64,         [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
243defm : AtomWriteResPair<WriteFCmp64X,       [AtomPort01], [AtomPort01],  6,  7,  [6],  [7]>;
244defm : X86WriteResPairUnsupported<WriteFCmp64Y>;
245defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
246defm : AtomWriteResPair<WriteFCom,           [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
247defm : AtomWriteResPair<WriteFMul,           [AtomPort0],  [AtomPort0],  4,  4,  [4],  [4]>;
248defm : AtomWriteResPair<WriteFMulX,          [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
249defm : X86WriteResPairUnsupported<WriteFMulY>;
250defm : X86WriteResPairUnsupported<WriteFMulZ>;
251defm : AtomWriteResPair<WriteFMul64,         [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
252defm : AtomWriteResPair<WriteFMul64X,       [AtomPort01], [AtomPort01],  9, 10,  [9], [10]>;
253defm : X86WriteResPairUnsupported<WriteFMul64Y>;
254defm : X86WriteResPairUnsupported<WriteFMul64Z>;
255defm : AtomWriteResPair<WriteFRcp,           [AtomPort0],  [AtomPort0],  4,  4,  [4],  [4]>;
256defm : AtomWriteResPair<WriteFRcpX,         [AtomPort01], [AtomPort01],  9, 10,  [9], [10]>;
257defm : X86WriteResPairUnsupported<WriteFRcpY>;
258defm : X86WriteResPairUnsupported<WriteFRcpZ>;
259defm : AtomWriteResPair<WriteFRsqrt,         [AtomPort0],  [AtomPort0],  4,  4,  [4],  [4]>;
260defm : AtomWriteResPair<WriteFRsqrtX,       [AtomPort01], [AtomPort01],  9, 10,  [9], [10]>;
261defm : X86WriteResPairUnsupported<WriteFRsqrtY>;
262defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
263defm : AtomWriteResPair<WriteFDiv,          [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
264defm : AtomWriteResPair<WriteFDivX,         [AtomPort01], [AtomPort01], 70, 70, [70], [70]>;
265defm : X86WriteResPairUnsupported<WriteFDivY>;
266defm : X86WriteResPairUnsupported<WriteFDivZ>;
267defm : AtomWriteResPair<WriteFDiv64,        [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
268defm : AtomWriteResPair<WriteFDiv64X,       [AtomPort01], [AtomPort01],125,125,[125],[125]>;
269defm : X86WriteResPairUnsupported<WriteFDiv64Y>;
270defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
271defm : AtomWriteResPair<WriteFSqrt,         [AtomPort01], [AtomPort01], 34, 34, [34], [34]>;
272defm : AtomWriteResPair<WriteFSqrtX,        [AtomPort01], [AtomPort01], 70, 70, [70], [70]>;
273defm : X86WriteResPairUnsupported<WriteFSqrtY>;
274defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
275defm : AtomWriteResPair<WriteFSqrt64,       [AtomPort01], [AtomPort01], 62, 62, [62], [62]>;
276defm : AtomWriteResPair<WriteFSqrt64X,      [AtomPort01], [AtomPort01],125,125,[125],[125]>;
277defm : X86WriteResPairUnsupported<WriteFSqrt64Y>;
278defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
279defm : AtomWriteResPair<WriteFSqrt80,       [AtomPort01], [AtomPort01], 71, 71, [71], [71]>;
280defm : AtomWriteResPair<WriteFSign,          [AtomPort1],  [AtomPort1]>;
281defm : AtomWriteResPair<WriteFRnd,           [AtomPort0],  [AtomPort0],  5,  5,  [5],  [5]>;
282defm : X86WriteResPairUnsupported<WriteFRndY>;
283defm : X86WriteResPairUnsupported<WriteFRndZ>;
284defm : AtomWriteResPair<WriteFLogic,        [AtomPort01],  [AtomPort0]>;
285defm : X86WriteResPairUnsupported<WriteFLogicY>;
286defm : X86WriteResPairUnsupported<WriteFLogicZ>;
287defm : AtomWriteResPair<WriteFTest,         [AtomPort01],  [AtomPort0]>;
288defm : X86WriteResPairUnsupported<WriteFTestY>;
289defm : X86WriteResPairUnsupported<WriteFTestZ>;
290defm : AtomWriteResPair<WriteFShuffle,       [AtomPort0],  [AtomPort0]>;
291defm : X86WriteResPairUnsupported<WriteFShuffleY>;
292defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
293defm : X86WriteResPairUnsupported<WriteFVarShuffle>;
294defm : X86WriteResPairUnsupported<WriteFVarShuffleY>;
295defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
296defm : X86WriteResPairUnsupported<WriteFMA>;
297defm : X86WriteResPairUnsupported<WriteFMAX>;
298defm : X86WriteResPairUnsupported<WriteFMAY>;
299defm : X86WriteResPairUnsupported<WriteFMAZ>;
300defm : X86WriteResPairUnsupported<WriteDPPD>;
301defm : X86WriteResPairUnsupported<WriteDPPS>;
302defm : X86WriteResPairUnsupported<WriteDPPSY>;
303defm : X86WriteResPairUnsupported<WriteDPPSZ>;
304defm : X86WriteResPairUnsupported<WriteFBlend>;
305defm : X86WriteResPairUnsupported<WriteFBlendY>;
306defm : X86WriteResPairUnsupported<WriteFBlendZ>;
307defm : X86WriteResPairUnsupported<WriteFVarBlend>;
308defm : X86WriteResPairUnsupported<WriteFVarBlendY>;
309defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
310defm : X86WriteResPairUnsupported<WriteFShuffle256>;
311defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
312
313////////////////////////////////////////////////////////////////////////////////
314// Conversions.
315////////////////////////////////////////////////////////////////////////////////
316
317defm : AtomWriteResPair<WriteCvtSS2I,   [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
318defm : AtomWriteResPair<WriteCvtPS2I,   [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
319defm : X86WriteResPairUnsupported<WriteCvtPS2IY>;
320defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
321defm : AtomWriteResPair<WriteCvtSD2I,   [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
322defm : AtomWriteResPair<WriteCvtPD2I,   [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
323defm : X86WriteResPairUnsupported<WriteCvtPD2IY>;
324defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
325
326defm : AtomWriteResPair<WriteCvtI2SS,   [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
327defm : AtomWriteResPair<WriteCvtI2PS,   [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
328defm : X86WriteResPairUnsupported<WriteCvtI2PSY>;
329defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
330defm : AtomWriteResPair<WriteCvtI2SD,   [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
331defm : AtomWriteResPair<WriteCvtI2PD,   [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
332defm : X86WriteResPairUnsupported<WriteCvtI2PDY>;
333defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
334
335defm : AtomWriteResPair<WriteCvtSS2SD,  [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
336defm : AtomWriteResPair<WriteCvtPS2PD,  [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
337defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>;
338defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
339defm : AtomWriteResPair<WriteCvtSD2SS,  [AtomPort01], [AtomPort01], 6, 7, [6], [7]>;
340defm : AtomWriteResPair<WriteCvtPD2PS,  [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
341defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>;
342defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
343
344defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;
345defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;
346defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
347defm : X86WriteResUnsupported<WriteCvtPS2PH>;
348defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;
349defm : X86WriteResUnsupported<WriteCvtPS2PHY>;
350defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
351defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;
352defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
353
354////////////////////////////////////////////////////////////////////////////////
355// Vector integer operations.
356////////////////////////////////////////////////////////////////////////////////
357
358def  : WriteRes<WriteVecLoad,         [AtomPort0]>;
359def  : WriteRes<WriteVecLoadX,        [AtomPort0]>;
360defm : X86WriteResUnsupported<WriteVecLoadY>;
361def  : WriteRes<WriteVecLoadNT,       [AtomPort0]>;
362defm : X86WriteResUnsupported<WriteVecLoadNTY>;
363defm : X86WriteResUnsupported<WriteVecMaskedLoad>;
364defm : X86WriteResUnsupported<WriteVecMaskedLoadY>;
365
366def  : WriteRes<WriteVecStore,        [AtomPort0]>;
367def  : WriteRes<WriteVecStoreX,       [AtomPort0]>;
368defm : X86WriteResUnsupported<WriteVecStoreY>;
369def  : WriteRes<WriteVecStoreNT,      [AtomPort0]>;
370defm : X86WriteResUnsupported<WriteVecStoreNTY>;
371def  : WriteRes<WriteVecMaskedStore,  [AtomPort0]>;
372defm : X86WriteResUnsupported<WriteVecMaskedStoreY>;
373
374def  : WriteRes<WriteVecMove,          [AtomPort0]>;
375def  : WriteRes<WriteVecMoveX,        [AtomPort01]>;
376defm : X86WriteResUnsupported<WriteVecMoveY>;
377defm : X86WriteRes<WriteVecMoveToGpr,   [AtomPort0], 3, [3], 1>;
378defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>;
379
380defm : AtomWriteResPair<WriteVecALU,       [AtomPort01],  [AtomPort0], 1, 1>;
381defm : AtomWriteResPair<WriteVecALUX,      [AtomPort01],  [AtomPort0], 1, 1>;
382defm : X86WriteResPairUnsupported<WriteVecALUY>;
383defm : X86WriteResPairUnsupported<WriteVecALUZ>;
384defm : AtomWriteResPair<WriteVecLogic,     [AtomPort01],  [AtomPort0], 1, 1>;
385defm : AtomWriteResPair<WriteVecLogicX,    [AtomPort01],  [AtomPort0], 1, 1>;
386defm : X86WriteResPairUnsupported<WriteVecLogicY>;
387defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
388defm : AtomWriteResPair<WriteVecTest,      [AtomPort01],  [AtomPort0], 1, 1>;
389defm : X86WriteResPairUnsupported<WriteVecTestY>;
390defm : X86WriteResPairUnsupported<WriteVecTestZ>;
391defm : AtomWriteResPair<WriteVecShift,     [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
392defm : AtomWriteResPair<WriteVecShiftX,    [AtomPort01], [AtomPort01], 2, 3, [2], [3]>;
393defm : X86WriteResPairUnsupported<WriteVecShiftY>;
394defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
395defm : AtomWriteResPair<WriteVecShiftImm,  [AtomPort01], [AtomPort01], 1, 1, [1], [1]>;
396defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>;
397defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;
398defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
399defm : AtomWriteResPair<WriteVecIMul,       [AtomPort0],  [AtomPort0], 4, 4, [4], [4]>;
400defm : AtomWriteResPair<WriteVecIMulX,      [AtomPort0],  [AtomPort0], 5, 5, [5], [5]>;
401defm : X86WriteResPairUnsupported<WriteVecIMulY>;
402defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
403defm : X86WriteResPairUnsupported<WritePMULLD>;
404defm : X86WriteResPairUnsupported<WritePMULLDY>;
405defm : X86WriteResPairUnsupported<WritePMULLDZ>;
406defm : X86WriteResPairUnsupported<WritePHMINPOS>;
407defm : X86WriteResPairUnsupported<WriteMPSAD>;
408defm : X86WriteResPairUnsupported<WriteMPSADY>;
409defm : X86WriteResPairUnsupported<WriteMPSADZ>;
410defm : AtomWriteResPair<WritePSADBW,       [AtomPort01], [AtomPort01], 4, 4, [4], [4]>;
411defm : AtomWriteResPair<WritePSADBWX,       [AtomPort0],  [AtomPort0], 5, 5, [5], [5]>;
412defm : X86WriteResPairUnsupported<WritePSADBWY>;
413defm : X86WriteResPairUnsupported<WritePSADBWZ>;
414defm : AtomWriteResPair<WriteShuffle,       [AtomPort0],  [AtomPort0], 1, 1>;
415defm : AtomWriteResPair<WriteShuffleX,      [AtomPort0],  [AtomPort0], 1, 1>;
416defm : X86WriteResPairUnsupported<WriteShuffleY>;
417defm : X86WriteResPairUnsupported<WriteShuffleZ>;
418defm : AtomWriteResPair<WriteVarShuffle,    [AtomPort0],  [AtomPort0], 1, 1>;
419defm : AtomWriteResPair<WriteVarShuffleX,  [AtomPort01], [AtomPort01], 4, 5, [4], [5]>;
420defm : X86WriteResPairUnsupported<WriteVarShuffleY>;
421defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
422defm : X86WriteResPairUnsupported<WriteBlend>;
423defm : X86WriteResPairUnsupported<WriteBlendY>;
424defm : X86WriteResPairUnsupported<WriteBlendZ>;
425defm : X86WriteResPairUnsupported<WriteVarBlend>;
426defm : X86WriteResPairUnsupported<WriteVarBlendY>;
427defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
428defm : X86WriteResPairUnsupported<WriteShuffle256>;
429defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
430defm : X86WriteResPairUnsupported<WriteVarVecShift>;
431defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
432defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
433
434////////////////////////////////////////////////////////////////////////////////
435// Vector insert/extract operations.
436////////////////////////////////////////////////////////////////////////////////
437
438defm : AtomWriteResPair<WriteVecInsert,     [AtomPort0],  [AtomPort0], 1, 1>;
439def  : WriteRes<WriteVecExtract,   [AtomPort0]>;
440def  : WriteRes<WriteVecExtractSt, [AtomPort0]>;
441
442////////////////////////////////////////////////////////////////////////////////
443// SSE42 String instructions.
444////////////////////////////////////////////////////////////////////////////////
445
446defm : X86WriteResPairUnsupported<WritePCmpIStrI>;
447defm : X86WriteResPairUnsupported<WritePCmpIStrM>;
448defm : X86WriteResPairUnsupported<WritePCmpEStrI>;
449defm : X86WriteResPairUnsupported<WritePCmpEStrM>;
450
451////////////////////////////////////////////////////////////////////////////////
452// MOVMSK Instructions.
453////////////////////////////////////////////////////////////////////////////////
454
455def  : WriteRes<WriteFMOVMSK,    [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
456def  : WriteRes<WriteVecMOVMSK,  [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
457defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
458def  : WriteRes<WriteMMXMOVMSK,  [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
459
460////////////////////////////////////////////////////////////////////////////////
461// AES instructions.
462////////////////////////////////////////////////////////////////////////////////
463
464defm : X86WriteResPairUnsupported<WriteAESIMC>;
465defm : X86WriteResPairUnsupported<WriteAESKeyGen>;
466defm : X86WriteResPairUnsupported<WriteAESDecEnc>;
467
468////////////////////////////////////////////////////////////////////////////////
469// Horizontal add/sub  instructions.
470////////////////////////////////////////////////////////////////////////////////
471
472defm : AtomWriteResPair<WriteFHAdd,  [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
473defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>;
474defm : AtomWriteResPair<WritePHAdd,  [AtomPort01], [AtomPort01], 3, 4, [3], [4]>;
475defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
476defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>;
477
478////////////////////////////////////////////////////////////////////////////////
479// Carry-less multiplication instructions.
480////////////////////////////////////////////////////////////////////////////////
481
482defm : X86WriteResPairUnsupported<WriteCLMul>;
483
484////////////////////////////////////////////////////////////////////////////////
485// Load/store MXCSR.
486////////////////////////////////////////////////////////////////////////////////
487
488def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; }
489def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; }
490
491////////////////////////////////////////////////////////////////////////////////
492// Special Cases.
493////////////////////////////////////////////////////////////////////////////////
494
495// Port0
496def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {
497  let Latency = 1;
498  let ResourceCycles = [1];
499}
500def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr,
501                                     MOVSX64rr32)>;
502def : SchedAlias<WriteALURMW, AtomWrite0_1>;
503def : SchedAlias<WriteADCRMW, AtomWrite0_1>;
504def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
505                                        "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>;
506
507// Port1
508def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
509  let Latency = 1;
510  let ResourceCycles = [1];
511}
512def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
513def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>;
514
515def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
516  let Latency = 5;
517  let ResourceCycles = [5];
518}
519def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm,
520                                     MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>;
521
522// Port0 and Port1
523def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
524  let Latency = 1;
525  let ResourceCycles = [1, 1];
526}
527def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
528                                       POP16rmr, POP32rmr, POP64rmr,
529                                       PUSH16r, PUSH32r, PUSH64r,
530                                       PUSHi16, PUSHi32,
531                                       PUSH16rmr, PUSH32rmr, PUSH64rmr,
532                                       PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
533                                       XCH_F)>;
534def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$",
535                                          "IRET(16|32|64)?")>;
536
537def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
538  let Latency = 5;
539  let ResourceCycles = [5, 5];
540}
541def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>;
542def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
543
544// Port0 or Port1
545def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {
546  let Latency = 1;
547  let ResourceCycles = [1];
548}
549def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
550                                      LFENCE,
551                                      STOSB, STOSL, STOSQ, STOSW,
552                                      MOVSSrr, MOVSSrr_REV,
553                                      PSLLDQri, PSRLDQri)>;
554def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr",
555                                         "MMX_PUNPCKH(BW|DQ|WD)irr")>;
556
557def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {
558  let Latency = 2;
559  let ResourceCycles = [2];
560}
561def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
562                                      PUSH16rmm, PUSH32rmm, PUSH64rmm,
563                                      LODSB, LODSL, LODSQ, LODSW,
564                                      SCASB, SCASL, SCASQ, SCASW)>;
565def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)",
566                                         "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)",
567                                         "MMX_P(ADD|SUB)Qirr",
568                                         "MOV(S|Z)X16rr8",
569                                         "MOV(UPS|UPD|DQU)mr",
570                                         "MASKMOVDQU(64)?",
571                                         "P(ADD|SUB)Qrr")>;
572def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>;
573
574def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {
575  let Latency = 3;
576  let ResourceCycles = [3];
577}
578def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
579                                      CMPSB, CMPSL, CMPSQ, CMPSW,
580                                      MOVSB, MOVSL, MOVSQ, MOVSW,
581                                      POP16rmm, POP32rmm, POP64rmm)>;
582def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
583                                         "XCHG(8|16|32|64)rm",
584                                         "PH(ADD|SUB)Drr",
585                                         "MOV(S|Z)X16rm8",
586                                         "MMX_P(ADD|SUB)Qirm",
587                                         "MOV(UPS|UPD|DQU)rm",
588                                         "P(ADD|SUB)Qrm")>;
589
590def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {
591  let Latency = 4;
592  let ResourceCycles = [4];
593}
594def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
595                                      JCXZ, JECXZ, JRCXZ,
596                                      LD_F80m)>;
597def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm",
598                                         "(MMX_)?PEXTRWrr(_REV)?")>;
599
600def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {
601  let Latency = 5;
602  let ResourceCycles = [5];
603}
604def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>;
605def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>;
606
607def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {
608  let Latency = 6;
609  let ResourceCycles = [6];
610}
611def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT,
612                                      SHLD16rrCL, SHRD16rrCL,
613                                      SHLD16rri8, SHRD16rri8,
614                                      SHLD16mrCL, SHRD16mrCL,
615                                      SHLD16mri8, SHRD16mri8)>;
616def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m",
617                                         "MMX_PH(ADD|SUB)S?Wrm")>;
618
619def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
620  let Latency = 7;
621  let ResourceCycles = [7];
622}
623def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>;
624
625def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
626  let Latency = 8;
627  let ResourceCycles = [8];
628}
629def : InstRW<[AtomWrite01_8], (instrs LOOPE,
630                                      PUSHA16, PUSHA32,
631                                      SHLD64rrCL, SHRD64rrCL,
632                                      FNSTCW16m)>;
633
634def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
635  let Latency = 9;
636  let ResourceCycles = [9];
637}
638def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,
639                                      PUSHF16, PUSHF32, PUSHF64,
640                                      SHLD64mrCL, SHRD64mrCL,
641                                      SHLD64mri8, SHRD64mri8,
642                                      SHLD64rri8, SHRD64rri8,
643                                      CMPXCHG8rr)>;
644def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F",
645                                         "(U)?COMIS(D|S)rr",
646                                         "CVT(T)?SS2SI64rr(_Int)?")>;
647
648def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
649  let Latency = 10;
650  let ResourceCycles = [10];
651}
652def : SchedAlias<WriteFLDC, AtomWrite01_10>;
653def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm",
654                                          "CVT(T)?SS2SI64rm(_Int)?")>;
655
656def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {
657  let Latency = 11;
658  let ResourceCycles = [11];
659}
660def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;
661def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>;
662
663def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {
664  let Latency = 13;
665  let ResourceCycles = [13];
666}
667def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;
668
669def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {
670  let Latency = 14;
671  let ResourceCycles = [14];
672}
673def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
674
675def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
676  let Latency = 17;
677  let ResourceCycles = [17];
678}
679def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;
680
681def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {
682  let Latency = 18;
683  let ResourceCycles = [18];
684}
685def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;
686
687def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {
688  let Latency = 20;
689  let ResourceCycles = [20];
690}
691def : InstRW<[AtomWrite01_20], (instrs DAS)>;
692
693def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {
694  let Latency = 21;
695  let ResourceCycles = [21];
696}
697def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;
698
699def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {
700  let Latency = 22;
701  let ResourceCycles = [22];
702}
703def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;
704
705def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {
706  let Latency = 23;
707  let ResourceCycles = [23];
708}
709def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;
710
711def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {
712  let Latency = 25;
713  let ResourceCycles = [25];
714}
715def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;
716
717def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {
718  let Latency = 26;
719  let ResourceCycles = [26];
720}
721def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;
722
723def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {
724  let Latency = 29;
725  let ResourceCycles = [29];
726}
727def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;
728
729def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {
730  let Latency = 30;
731  let ResourceCycles = [30];
732}
733def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;
734
735def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {
736  let Latency = 32;
737  let ResourceCycles = [32];
738}
739def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;
740
741def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {
742  let Latency = 45;
743  let ResourceCycles = [45];
744}
745def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>;
746
747def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {
748  let Latency = 46;
749  let ResourceCycles = [46];
750}
751def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;
752
753def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {
754  let Latency = 48;
755  let ResourceCycles = [48];
756}
757def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;
758
759def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {
760  let Latency = 55;
761  let ResourceCycles = [55];
762}
763def : InstRW<[AtomWrite01_55], (instrs FPREM)>;
764
765def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {
766  let Latency = 59;
767  let ResourceCycles = [59];
768}
769def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;
770
771def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {
772  let Latency = 63;
773  let ResourceCycles = [63];
774}
775def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;
776
777def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {
778  let Latency = 68;
779  let ResourceCycles = [68];
780}
781def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;
782
783def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {
784  let Latency = 71;
785  let ResourceCycles = [71];
786}
787def : InstRW<[AtomWrite01_71], (instrs FPREM1,
788                                       INVLPG, INVLPGA32, INVLPGA64)>;
789
790def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {
791  let Latency = 72;
792  let ResourceCycles = [72];
793}
794def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;
795
796def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {
797  let Latency = 74;
798  let ResourceCycles = [74];
799}
800def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;
801
802def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {
803  let Latency = 77;
804  let ResourceCycles = [77];
805}
806def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
807
808def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
809  let Latency = 78;
810  let ResourceCycles = [78];
811}
812def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
813
814def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
815  let Latency = 79;
816  let ResourceCycles = [79];
817}
818def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$",
819                                          "LRETI?(L|Q|W)")>;
820
821def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
822  let Latency = 92;
823  let ResourceCycles = [92];
824}
825def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
826
827def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
828  let Latency = 94;
829  let ResourceCycles = [94];
830}
831def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;
832
833def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {
834  let Latency = 99;
835  let ResourceCycles = [99];
836}
837def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;
838
839def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {
840  let Latency = 121;
841  let ResourceCycles = [121];
842}
843def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
844
845def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {
846  let Latency = 127;
847  let ResourceCycles = [127];
848}
849def : InstRW<[AtomWrite01_127], (instrs INT)>;
850
851def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {
852  let Latency = 130;
853  let ResourceCycles = [130];
854}
855def : InstRW<[AtomWrite01_130], (instrs INT3)>;
856
857def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {
858  let Latency = 140;
859  let ResourceCycles = [140];
860}
861def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;
862
863def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {
864  let Latency = 141;
865  let ResourceCycles = [141];
866}
867def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;
868
869def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {
870  let Latency = 146;
871  let ResourceCycles = [146];
872}
873def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;
874
875def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {
876  let Latency = 147;
877  let ResourceCycles = [147];
878}
879def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;
880
881def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {
882  let Latency = 168;
883  let ResourceCycles = [168];
884}
885def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;
886
887def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {
888  let Latency = 174;
889  let ResourceCycles = [174];
890}
891def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
892
893def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {
894  let Latency = 183;
895  let ResourceCycles = [183];
896}
897def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;
898
899def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {
900  let Latency = 202;
901  let ResourceCycles = [202];
902}
903def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;
904
905} // SchedModel
906