1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86SelectionDAGInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86SelectionDAGInfo.h"
14 #include "X86ISelLowering.h"
15 #include "X86InstrInfo.h"
16 #include "X86RegisterInfo.h"
17 #include "X86Subtarget.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/TargetLowering.h"
21 #include "llvm/IR/DerivedTypes.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "x86-selectiondag-info"
26 
27 static cl::opt<bool>
28     UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false),
29                      cl::desc("Use fast short rep mov in memcpy lowering"));
30 
31 bool X86SelectionDAGInfo::isBaseRegConflictPossible(
32     SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
33   // We cannot use TRI->hasBasePointer() until *after* we select all basic
34   // blocks.  Legalization may introduce new stack temporaries with large
35   // alignment requirements.  Fall back to generic code if there are any
36   // dynamic stack adjustments (hopefully rare) and the base pointer would
37   // conflict if we had to use it.
38   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
39   if (!MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
40     return false;
41 
42   const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
43       DAG.getSubtarget().getRegisterInfo());
44   return llvm::is_contained(ClobberSet, TRI->getBaseRegister());
45 }
46 
47 SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
48     SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val,
49     SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
50     MachinePointerInfo DstPtrInfo) const {
51   ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
52   const X86Subtarget &Subtarget =
53       DAG.getMachineFunction().getSubtarget<X86Subtarget>();
54 
55 #ifndef NDEBUG
56   // If the base register might conflict with our physical registers, bail out.
57   const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
58                                   X86::ECX, X86::EAX, X86::EDI};
59   assert(!isBaseRegConflictPossible(DAG, ClobberSet));
60 #endif
61 
62   // If to a segment-relative address space, use the default lowering.
63   if (DstPtrInfo.getAddrSpace() >= 256)
64     return SDValue();
65 
66   // If not DWORD aligned or size is more than the threshold, call the library.
67   // The libc version is likely to be faster for these cases. It can use the
68   // address value and run time information about the CPU.
69   if (Alignment < Align(4) || !ConstantSize ||
70       ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold())
71     return SDValue();
72 
73   uint64_t SizeVal = ConstantSize->getZExtValue();
74   SDValue InFlag;
75   EVT AVT;
76   SDValue Count;
77   unsigned BytesLeft = 0;
78   if (auto *ValC = dyn_cast<ConstantSDNode>(Val)) {
79     unsigned ValReg;
80     uint64_t Val = ValC->getZExtValue() & 255;
81 
82     // If the value is a constant, then we can potentially use larger sets.
83     if (Alignment > Align(2)) {
84       // DWORD aligned
85       AVT = MVT::i32;
86       ValReg = X86::EAX;
87       Val = (Val << 8)  | Val;
88       Val = (Val << 16) | Val;
89       if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned
90         AVT = MVT::i64;
91         ValReg = X86::RAX;
92         Val = (Val << 32) | Val;
93       }
94     } else if (Alignment == Align(2)) {
95       // WORD aligned
96       AVT = MVT::i16;
97       ValReg = X86::AX;
98       Val = (Val << 8) | Val;
99     } else {
100       // Byte aligned
101       AVT = MVT::i8;
102       ValReg = X86::AL;
103       Count = DAG.getIntPtrConstant(SizeVal, dl);
104     }
105 
106     if (AVT.bitsGT(MVT::i8)) {
107       unsigned UBytes = AVT.getSizeInBits() / 8;
108       Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);
109       BytesLeft = SizeVal % UBytes;
110     }
111 
112     Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),
113                              InFlag);
114     InFlag = Chain.getValue(1);
115   } else {
116     AVT = MVT::i8;
117     Count  = DAG.getIntPtrConstant(SizeVal, dl);
118     Chain  = DAG.getCopyToReg(Chain, dl, X86::AL, Val, InFlag);
119     InFlag = Chain.getValue(1);
120   }
121 
122   bool Use64BitRegs = Subtarget.isTarget64BitLP64();
123   Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX,
124                            Count, InFlag);
125   InFlag = Chain.getValue(1);
126   Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RDI : X86::EDI,
127                            Dst, InFlag);
128   InFlag = Chain.getValue(1);
129 
130   SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
131   SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
132   Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
133 
134   if (BytesLeft) {
135     // Handle the last 1 - 7 bytes.
136     unsigned Offset = SizeVal - BytesLeft;
137     EVT AddrVT = Dst.getValueType();
138     EVT SizeVT = Size.getValueType();
139 
140     Chain =
141         DAG.getMemset(Chain, dl,
142                       DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
143                                   DAG.getConstant(Offset, dl, AddrVT)),
144                       Val, DAG.getConstant(BytesLeft, dl, SizeVT), Alignment,
145                       isVolatile, AlwaysInline,
146                       /* isTailCall */ false, DstPtrInfo.getWithOffset(Offset));
147   }
148 
149   // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
150   return Chain;
151 }
152 
153 /// Emit a single REP MOVS{B,W,D,Q} instruction.
154 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG,
155                            const SDLoc &dl, SDValue Chain, SDValue Dst,
156                            SDValue Src, SDValue Size, MVT AVT) {
157   const bool Use64BitRegs = Subtarget.isTarget64BitLP64();
158   const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX;
159   const unsigned DI = Use64BitRegs ? X86::RDI : X86::EDI;
160   const unsigned SI = Use64BitRegs ? X86::RSI : X86::ESI;
161 
162   SDValue InFlag;
163   Chain = DAG.getCopyToReg(Chain, dl, CX, Size, InFlag);
164   InFlag = Chain.getValue(1);
165   Chain = DAG.getCopyToReg(Chain, dl, DI, Dst, InFlag);
166   InFlag = Chain.getValue(1);
167   Chain = DAG.getCopyToReg(Chain, dl, SI, Src, InFlag);
168   InFlag = Chain.getValue(1);
169 
170   SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
171   SDValue Ops[] = {Chain, DAG.getValueType(AVT), InFlag};
172   return DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
173 }
174 
175 /// Emit a single REP MOVSB instruction for a particular constant size.
176 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG,
177                             const SDLoc &dl, SDValue Chain, SDValue Dst,
178                             SDValue Src, uint64_t Size) {
179   return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
180                      DAG.getIntPtrConstant(Size, dl), MVT::i8);
181 }
182 
183 /// Returns the best type to use with repmovs depending on alignment.
184 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget,
185                                  uint64_t Align) {
186   assert((Align != 0) && "Align is normalized");
187   assert(isPowerOf2_64(Align) && "Align is a power of 2");
188   switch (Align) {
189   case 1:
190     return MVT::i8;
191   case 2:
192     return MVT::i16;
193   case 4:
194     return MVT::i32;
195   default:
196     return Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
197   }
198 }
199 
200 /// Returns a REP MOVS instruction, possibly with a few load/stores to implement
201 /// a constant size memory copy. In some cases where we know REP MOVS is
202 /// inefficient we return an empty SDValue so the calling code can either
203 /// generate a load/store sequence or call the runtime memcpy function.
204 static SDValue emitConstantSizeRepmov(
205     SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl,
206     SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT,
207     unsigned Align, bool isVolatile, bool AlwaysInline,
208     MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) {
209 
210   /// TODO: Revisit next line: big copy with ERMSB on march >= haswell are very
211   /// efficient.
212   if (!AlwaysInline && Size > Subtarget.getMaxInlineSizeThreshold())
213     return SDValue();
214 
215   /// If we have enhanced repmovs we use it.
216   if (Subtarget.hasERMSB())
217     return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
218 
219   assert(!Subtarget.hasERMSB() && "No efficient RepMovs");
220   /// We assume runtime memcpy will do a better job for unaligned copies when
221   /// ERMS is not present.
222   if (!AlwaysInline && (Align & 3) != 0)
223     return SDValue();
224 
225   const MVT BlockType = getOptimalRepmovsType(Subtarget, Align);
226   const uint64_t BlockBytes = BlockType.getSizeInBits() / 8;
227   const uint64_t BlockCount = Size / BlockBytes;
228   const uint64_t BytesLeft = Size % BlockBytes;
229   SDValue RepMovs =
230       emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
231                   DAG.getIntPtrConstant(BlockCount, dl), BlockType);
232 
233   /// RepMov can process the whole length.
234   if (BytesLeft == 0)
235     return RepMovs;
236 
237   assert(BytesLeft && "We have leftover at this point");
238 
239   /// In case we optimize for size we use repmovsb even if it's less efficient
240   /// so we can save the loads/stores of the leftover.
241   if (DAG.getMachineFunction().getFunction().hasMinSize())
242     return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
243 
244   // Handle the last 1 - 7 bytes.
245   SmallVector<SDValue, 4> Results;
246   Results.push_back(RepMovs);
247   unsigned Offset = Size - BytesLeft;
248   EVT DstVT = Dst.getValueType();
249   EVT SrcVT = Src.getValueType();
250   Results.push_back(DAG.getMemcpy(
251       Chain, dl,
252       DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
253       DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
254       DAG.getConstant(BytesLeft, dl, SizeVT), llvm::Align(Align), isVolatile,
255       /*AlwaysInline*/ true, /*isTailCall*/ false,
256       DstPtrInfo.getWithOffset(Offset), SrcPtrInfo.getWithOffset(Offset)));
257   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
258 }
259 
260 SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
261     SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
262     SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
263     MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
264   // If to a segment-relative address space, use the default lowering.
265   if (DstPtrInfo.getAddrSpace() >= 256 || SrcPtrInfo.getAddrSpace() >= 256)
266     return SDValue();
267 
268   // If the base registers conflict with our physical registers, use the default
269   // lowering.
270   const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
271                                   X86::ECX, X86::ESI, X86::EDI};
272   if (isBaseRegConflictPossible(DAG, ClobberSet))
273     return SDValue();
274 
275   const X86Subtarget &Subtarget =
276       DAG.getMachineFunction().getSubtarget<X86Subtarget>();
277 
278   // If enabled and available, use fast short rep mov.
279   if (UseFSRMForMemcpy && Subtarget.hasFSRM())
280     return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, Size, MVT::i8);
281 
282   /// Handle constant sizes,
283   if (ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size))
284     return emitConstantSizeRepmov(
285         DAG, Subtarget, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
286         Size.getValueType(), Alignment.value(), isVolatile, AlwaysInline,
287         DstPtrInfo, SrcPtrInfo);
288 
289   return SDValue();
290 }
291