1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file a TargetTransformInfo::Concept conforming object specific to the 10 /// X86 target machine. It uses the target's detailed information to 11 /// provide more precise answers to certain TTI queries, while letting the 12 /// target independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H 17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H 18 19 #include "X86TargetMachine.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/BasicTTIImpl.h" 22 23 namespace llvm { 24 25 class InstCombiner; 26 27 class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> { 28 typedef BasicTTIImplBase<X86TTIImpl> BaseT; 29 typedef TargetTransformInfo TTI; 30 friend BaseT; 31 32 const X86Subtarget *ST; 33 const X86TargetLowering *TLI; 34 35 const X86Subtarget *getST() const { return ST; } 36 const X86TargetLowering *getTLI() const { return TLI; } 37 38 const FeatureBitset InlineFeatureIgnoreList = { 39 // This indicates the CPU is 64 bit capable not that we are in 64-bit 40 // mode. 41 X86::FeatureX86_64, 42 43 // These features don't have any intrinsics or ABI effect. 44 X86::FeatureNOPL, 45 X86::FeatureCX16, 46 X86::FeatureLAHFSAHF64, 47 48 // Some older targets can be setup to fold unaligned loads. 49 X86::FeatureSSEUnalignedMem, 50 51 // Codegen control options. 52 X86::TuningFast11ByteNOP, 53 X86::TuningFast15ByteNOP, 54 X86::TuningFastBEXTR, 55 X86::TuningFastHorizontalOps, 56 X86::TuningFastLZCNT, 57 X86::TuningFastScalarFSQRT, 58 X86::TuningFastSHLDRotate, 59 X86::TuningFastScalarShiftMasks, 60 X86::TuningFastVectorShiftMasks, 61 X86::TuningFastVariableCrossLaneShuffle, 62 X86::TuningFastVariablePerLaneShuffle, 63 X86::TuningFastVectorFSQRT, 64 X86::TuningLEAForSP, 65 X86::TuningLEAUsesAG, 66 X86::TuningLZCNTFalseDeps, 67 X86::TuningBranchFusion, 68 X86::TuningMacroFusion, 69 X86::TuningPadShortFunctions, 70 X86::TuningPOPCNTFalseDeps, 71 X86::TuningMULCFalseDeps, 72 X86::TuningPERMFalseDeps, 73 X86::TuningRANGEFalseDeps, 74 X86::TuningGETMANTFalseDeps, 75 X86::TuningMULLQFalseDeps, 76 X86::TuningSlow3OpsLEA, 77 X86::TuningSlowDivide32, 78 X86::TuningSlowDivide64, 79 X86::TuningSlowIncDec, 80 X86::TuningSlowLEA, 81 X86::TuningSlowPMADDWD, 82 X86::TuningSlowPMULLD, 83 X86::TuningSlowSHLD, 84 X86::TuningSlowTwoMemOps, 85 X86::TuningSlowUAMem16, 86 X86::TuningPreferMaskRegisters, 87 X86::TuningInsertVZEROUPPER, 88 X86::TuningUseSLMArithCosts, 89 X86::TuningUseGLMDivSqrtCosts, 90 91 // Perf-tuning flags. 92 X86::TuningFastGather, 93 X86::TuningSlowUAMem32, 94 95 // Based on whether user set the -mprefer-vector-width command line. 96 X86::TuningPrefer128Bit, 97 X86::TuningPrefer256Bit, 98 99 // CPU name enums. These just follow CPU string. 100 X86::ProcIntelAtom 101 }; 102 103 public: 104 explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F) 105 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 106 TLI(ST->getTargetLowering()) {} 107 108 /// \name Scalar TTI Implementations 109 /// @{ 110 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); 111 112 /// @} 113 114 /// \name Cache TTI Implementation 115 /// @{ 116 llvm::Optional<unsigned> getCacheSize( 117 TargetTransformInfo::CacheLevel Level) const override; 118 llvm::Optional<unsigned> getCacheAssociativity( 119 TargetTransformInfo::CacheLevel Level) const override; 120 /// @} 121 122 /// \name Vector TTI Implementations 123 /// @{ 124 125 unsigned getNumberOfRegisters(unsigned ClassID) const; 126 TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; 127 unsigned getLoadStoreVecRegBitWidth(unsigned AS) const; 128 unsigned getMaxInterleaveFactor(unsigned VF); 129 InstructionCost getArithmeticInstrCost( 130 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, 131 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, 132 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, 133 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, 134 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, 135 ArrayRef<const Value *> Args = ArrayRef<const Value *>(), 136 const Instruction *CxtI = nullptr); 137 InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, 138 ArrayRef<int> Mask, int Index, 139 VectorType *SubTp, 140 ArrayRef<const Value *> Args = None); 141 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 142 TTI::CastContextHint CCH, 143 TTI::TargetCostKind CostKind, 144 const Instruction *I = nullptr); 145 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 146 CmpInst::Predicate VecPred, 147 TTI::TargetCostKind CostKind, 148 const Instruction *I = nullptr); 149 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, 150 unsigned Index); 151 InstructionCost getScalarizationOverhead(VectorType *Ty, 152 const APInt &DemandedElts, 153 bool Insert, bool Extract); 154 InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, 155 int VF, 156 const APInt &DemandedDstElts, 157 TTI::TargetCostKind CostKind); 158 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, 159 MaybeAlign Alignment, unsigned AddressSpace, 160 TTI::TargetCostKind CostKind, 161 const Instruction *I = nullptr); 162 InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, 163 Align Alignment, unsigned AddressSpace, 164 TTI::TargetCostKind CostKind); 165 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, 166 const Value *Ptr, bool VariableMask, 167 Align Alignment, 168 TTI::TargetCostKind CostKind, 169 const Instruction *I); 170 InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, 171 const SCEV *Ptr); 172 173 Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, 174 IntrinsicInst &II) const; 175 Optional<Value *> 176 simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, 177 APInt DemandedMask, KnownBits &Known, 178 bool &KnownBitsComputed) const; 179 Optional<Value *> simplifyDemandedVectorEltsIntrinsic( 180 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, 181 APInt &UndefElts2, APInt &UndefElts3, 182 std::function<void(Instruction *, unsigned, APInt, APInt &)> 183 SimplifyAndSetOp) const; 184 185 unsigned getAtomicMemIntrinsicMaxElementSize() const; 186 187 InstructionCost 188 getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 189 TTI::TargetCostKind CostKind); 190 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 191 TTI::TargetCostKind CostKind); 192 193 InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, 194 Optional<FastMathFlags> FMF, 195 TTI::TargetCostKind CostKind); 196 197 InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned); 198 199 InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, 200 bool IsUnsigned, 201 TTI::TargetCostKind CostKind); 202 203 InstructionCost getInterleavedMemoryOpCost( 204 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 205 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, 206 bool UseMaskForCond = false, bool UseMaskForGaps = false); 207 InstructionCost getInterleavedMemoryOpCostAVX512( 208 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 209 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 210 TTI::TargetCostKind CostKind, bool UseMaskForCond = false, 211 bool UseMaskForGaps = false); 212 213 InstructionCost getIntImmCost(int64_t); 214 215 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, 216 TTI::TargetCostKind CostKind); 217 218 InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, 219 const Instruction *I = nullptr); 220 221 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, 222 const APInt &Imm, Type *Ty, 223 TTI::TargetCostKind CostKind, 224 Instruction *Inst = nullptr); 225 InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 226 const APInt &Imm, Type *Ty, 227 TTI::TargetCostKind CostKind); 228 bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, 229 const TargetTransformInfo::LSRCost &C2); 230 bool canMacroFuseCmp(); 231 bool isLegalMaskedLoad(Type *DataType, Align Alignment); 232 bool isLegalMaskedStore(Type *DataType, Align Alignment); 233 bool isLegalNTLoad(Type *DataType, Align Alignment); 234 bool isLegalNTStore(Type *DataType, Align Alignment); 235 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const; 236 bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment); 237 bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) { 238 return forceScalarizeMaskedGather(VTy, Alignment); 239 } 240 bool isLegalMaskedGather(Type *DataType, Align Alignment); 241 bool isLegalMaskedScatter(Type *DataType, Align Alignment); 242 bool isLegalMaskedExpandLoad(Type *DataType); 243 bool isLegalMaskedCompressStore(Type *DataType); 244 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, 245 const SmallBitVector &OpcodeMask) const; 246 bool hasDivRemOp(Type *DataType, bool IsSigned); 247 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty); 248 bool areInlineCompatible(const Function *Caller, 249 const Function *Callee) const; 250 bool areTypesABICompatible(const Function *Caller, const Function *Callee, 251 const ArrayRef<Type *> &Type) const; 252 TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, 253 bool IsZeroCmp) const; 254 bool prefersVectorizedAddressing() const; 255 bool supportsEfficientVectorElementLoadStore() const; 256 bool enableInterleavedAccessVectorization(); 257 258 private: 259 bool supportsGather() const; 260 InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy, 261 bool VariableMask, Align Alignment, 262 unsigned AddressSpace); 263 InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy, 264 const Value *Ptr, Align Alignment, 265 unsigned AddressSpace); 266 267 int getGatherOverhead() const; 268 int getScatterOverhead() const; 269 270 /// @} 271 }; 272 273 } // end namespace llvm 274 275 #endif 276