1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file is part of the XCore Disassembler.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "TargetInfo/XCoreTargetInfo.h"
15 #include "XCore.h"
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDecoderOps.h"
19 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/MC/TargetRegistry.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "xcore-disassembler"
27 
28 typedef MCDisassembler::DecodeStatus DecodeStatus;
29 
30 namespace {
31 
32 /// A disassembler class for XCore.
33 class XCoreDisassembler : public MCDisassembler {
34 public:
35   XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
36     MCDisassembler(STI, Ctx) {}
37 
38   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39                               ArrayRef<uint8_t> Bytes, uint64_t Address,
40                               raw_ostream &CStream) const override;
41 };
42 }
43 
44 static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
45                               uint64_t &Size, uint16_t &Insn) {
46   // We want to read exactly 2 Bytes of data.
47   if (Bytes.size() < 2) {
48     Size = 0;
49     return false;
50   }
51   // Encoded as a little-endian 16-bit word in the stream.
52   Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
53   return true;
54 }
55 
56 static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
57                               uint64_t &Size, uint32_t &Insn) {
58   // We want to read exactly 4 Bytes of data.
59   if (Bytes.size() < 4) {
60     Size = 0;
61     return false;
62   }
63   // Encoded as a little-endian 32-bit word in the stream.
64   Insn =
65       (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
66   return true;
67 }
68 
69 static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
70   const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
71   return *(RegInfo->getRegClass(RC).begin() + RegNo);
72 }
73 
74 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
75                                               uint64_t Address,
76                                               const MCDisassembler *Decoder);
77 
78 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
79                                              uint64_t Address,
80                                              const MCDisassembler *Decoder);
81 
82 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
83                                       uint64_t Address,
84                                       const MCDisassembler *Decoder);
85 
86 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
87                                         uint64_t Address,
88                                         const MCDisassembler *Decoder);
89 
90 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
91                                         uint64_t Address,
92                                         const MCDisassembler *Decoder);
93 
94 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
95                                            uint64_t Address,
96                                            const MCDisassembler *Decoder);
97 
98 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
99                                          uint64_t Address,
100                                          const MCDisassembler *Decoder);
101 
102 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
103                                               uint64_t Address,
104                                               const MCDisassembler *Decoder);
105 
106 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
107                                          uint64_t Address,
108                                          const MCDisassembler *Decoder);
109 
110 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
111                                              uint64_t Address,
112                                              const MCDisassembler *Decoder);
113 
114 static DecodeStatus
115 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
116                                const MCDisassembler *Decoder);
117 
118 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn,
119                                          uint64_t Address,
120                                          const MCDisassembler *Decoder);
121 
122 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn,
123                                           uint64_t Address,
124                                           const MCDisassembler *Decoder);
125 
126 static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn,
127                                         uint64_t Address,
128                                         const MCDisassembler *Decoder);
129 
130 static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn,
131                                            uint64_t Address,
132                                            const MCDisassembler *Decoder);
133 
134 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn,
135                                           uint64_t Address,
136                                           const MCDisassembler *Decoder);
137 
138 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
139                                               uint64_t Address,
140                                               const MCDisassembler *Decoder);
141 
142 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,
143                                          uint64_t Address,
144                                          const MCDisassembler *Decoder);
145 
146 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,
147                                                uint64_t Address,
148                                                const MCDisassembler *Decoder);
149 
150 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,
151                                            uint64_t Address,
152                                            const MCDisassembler *Decoder);
153 
154 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
155                                                uint64_t Address,
156                                                const MCDisassembler *Decoder);
157 
158 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn,
159                                          uint64_t Address,
160                                          const MCDisassembler *Decoder);
161 
162 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn,
163                                          uint64_t Address,
164                                          const MCDisassembler *Decoder);
165 
166 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn,
167                                                uint64_t Address,
168                                                const MCDisassembler *Decoder);
169 
170 static DecodeStatus
171 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
172                                  const MCDisassembler *Decoder);
173 
174 #include "XCoreGenDisassemblerTables.inc"
175 
176 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
177                                               uint64_t Address,
178                                               const MCDisassembler *Decoder) {
179   if (RegNo > 11)
180     return MCDisassembler::Fail;
181   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
182   Inst.addOperand(MCOperand::createReg(Reg));
183   return MCDisassembler::Success;
184 }
185 
186 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
187                                              uint64_t Address,
188                                              const MCDisassembler *Decoder) {
189   if (RegNo > 15)
190     return MCDisassembler::Fail;
191   unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
192   Inst.addOperand(MCOperand::createReg(Reg));
193   return MCDisassembler::Success;
194 }
195 
196 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
197                                       uint64_t Address,
198                                       const MCDisassembler *Decoder) {
199   if (Val > 11)
200     return MCDisassembler::Fail;
201   static const unsigned Values[] = {
202     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
203   };
204   Inst.addOperand(MCOperand::createImm(Values[Val]));
205   return MCDisassembler::Success;
206 }
207 
208 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
209                                         uint64_t Address,
210                                         const MCDisassembler *Decoder) {
211   Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
212   return MCDisassembler::Success;
213 }
214 
215 static DecodeStatus
216 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
217   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
218   if (Combined < 27)
219     return MCDisassembler::Fail;
220   if (fieldFromInstruction(Insn, 5, 1)) {
221     if (Combined == 31)
222       return MCDisassembler::Fail;
223     Combined += 5;
224   }
225   Combined -= 27;
226   unsigned Op1High = Combined % 3;
227   unsigned Op2High = Combined / 3;
228   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
229   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
230   return MCDisassembler::Success;
231 }
232 
233 static DecodeStatus
234 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
235                      unsigned &Op3) {
236   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
237   if (Combined >= 27)
238     return MCDisassembler::Fail;
239 
240   unsigned Op1High = Combined % 3;
241   unsigned Op2High = (Combined / 3) % 3;
242   unsigned Op3High = Combined / 9;
243   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
244   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
245   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
246   return MCDisassembler::Success;
247 }
248 
249 static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn,
250                                              uint64_t Address,
251                                              const MCDisassembler *Decoder) {
252   // Try and decode as a 3R instruction.
253   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
254   switch (Opcode) {
255   case 0x0:
256     Inst.setOpcode(XCore::STW_2rus);
257     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
258   case 0x1:
259     Inst.setOpcode(XCore::LDW_2rus);
260     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
261   case 0x2:
262     Inst.setOpcode(XCore::ADD_3r);
263     return Decode3RInstruction(Inst, Insn, Address, Decoder);
264   case 0x3:
265     Inst.setOpcode(XCore::SUB_3r);
266     return Decode3RInstruction(Inst, Insn, Address, Decoder);
267   case 0x4:
268     Inst.setOpcode(XCore::SHL_3r);
269     return Decode3RInstruction(Inst, Insn, Address, Decoder);
270   case 0x5:
271     Inst.setOpcode(XCore::SHR_3r);
272     return Decode3RInstruction(Inst, Insn, Address, Decoder);
273   case 0x6:
274     Inst.setOpcode(XCore::EQ_3r);
275     return Decode3RInstruction(Inst, Insn, Address, Decoder);
276   case 0x7:
277     Inst.setOpcode(XCore::AND_3r);
278     return Decode3RInstruction(Inst, Insn, Address, Decoder);
279   case 0x8:
280     Inst.setOpcode(XCore::OR_3r);
281     return Decode3RInstruction(Inst, Insn, Address, Decoder);
282   case 0x9:
283     Inst.setOpcode(XCore::LDW_3r);
284     return Decode3RInstruction(Inst, Insn, Address, Decoder);
285   case 0x10:
286     Inst.setOpcode(XCore::LD16S_3r);
287     return Decode3RInstruction(Inst, Insn, Address, Decoder);
288   case 0x11:
289     Inst.setOpcode(XCore::LD8U_3r);
290     return Decode3RInstruction(Inst, Insn, Address, Decoder);
291   case 0x12:
292     Inst.setOpcode(XCore::ADD_2rus);
293     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
294   case 0x13:
295     Inst.setOpcode(XCore::SUB_2rus);
296     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
297   case 0x14:
298     Inst.setOpcode(XCore::SHL_2rus);
299     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
300   case 0x15:
301     Inst.setOpcode(XCore::SHR_2rus);
302     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
303   case 0x16:
304     Inst.setOpcode(XCore::EQ_2rus);
305     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
306   case 0x17:
307     Inst.setOpcode(XCore::TSETR_3r);
308     return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
309   case 0x18:
310     Inst.setOpcode(XCore::LSS_3r);
311     return Decode3RInstruction(Inst, Insn, Address, Decoder);
312   case 0x19:
313     Inst.setOpcode(XCore::LSU_3r);
314     return Decode3RInstruction(Inst, Insn, Address, Decoder);
315   }
316   return MCDisassembler::Fail;
317 }
318 
319 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
320                                         uint64_t Address,
321                                         const MCDisassembler *Decoder) {
322   unsigned Op1, Op2;
323   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
324   if (S != MCDisassembler::Success)
325     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
326 
327   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
328   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
329   return S;
330 }
331 
332 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
333                                            uint64_t Address,
334                                            const MCDisassembler *Decoder) {
335   unsigned Op1, Op2;
336   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
337   if (S != MCDisassembler::Success)
338     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
339 
340   Inst.addOperand(MCOperand::createImm(Op1));
341   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
342   return S;
343 }
344 
345 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
346                                          uint64_t Address,
347                                          const MCDisassembler *Decoder) {
348   unsigned Op1, Op2;
349   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
350   if (S != MCDisassembler::Success)
351     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
352 
353   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
354   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
355   return S;
356 }
357 
358 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
359                                               uint64_t Address,
360                                               const MCDisassembler *Decoder) {
361   unsigned Op1, Op2;
362   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
363   if (S != MCDisassembler::Success)
364     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
365 
366   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
367   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
368   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
369   return S;
370 }
371 
372 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
373                                          uint64_t Address,
374                                          const MCDisassembler *Decoder) {
375   unsigned Op1, Op2;
376   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
377   if (S != MCDisassembler::Success)
378     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
379 
380   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
381   Inst.addOperand(MCOperand::createImm(Op2));
382   return S;
383 }
384 
385 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
386                                              uint64_t Address,
387                                              const MCDisassembler *Decoder) {
388   unsigned Op1, Op2;
389   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
390   if (S != MCDisassembler::Success)
391     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
392 
393   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
394   DecodeBitpOperand(Inst, Op2, Address, Decoder);
395   return S;
396 }
397 
398 static DecodeStatus
399 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
400                                const MCDisassembler *Decoder) {
401   unsigned Op1, Op2;
402   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
403   if (S != MCDisassembler::Success)
404     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
405 
406   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
407   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
408   DecodeBitpOperand(Inst, Op2, Address, Decoder);
409   return S;
410 }
411 
412 static DecodeStatus DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn,
413                                               uint64_t Address,
414                                               const MCDisassembler *Decoder) {
415   // Try and decode as a L3R / L2RUS instruction.
416   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
417                     fieldFromInstruction(Insn, 27, 5) << 4;
418   switch (Opcode) {
419   case 0x0c:
420     Inst.setOpcode(XCore::STW_l3r);
421     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
422   case 0x1c:
423     Inst.setOpcode(XCore::XOR_l3r);
424     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
425   case 0x2c:
426     Inst.setOpcode(XCore::ASHR_l3r);
427     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
428   case 0x3c:
429     Inst.setOpcode(XCore::LDAWF_l3r);
430     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
431   case 0x4c:
432     Inst.setOpcode(XCore::LDAWB_l3r);
433     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
434   case 0x5c:
435     Inst.setOpcode(XCore::LDA16F_l3r);
436     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
437   case 0x6c:
438     Inst.setOpcode(XCore::LDA16B_l3r);
439     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
440   case 0x7c:
441     Inst.setOpcode(XCore::MUL_l3r);
442     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
443   case 0x8c:
444     Inst.setOpcode(XCore::DIVS_l3r);
445     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
446   case 0x9c:
447     Inst.setOpcode(XCore::DIVU_l3r);
448     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
449   case 0x10c:
450     Inst.setOpcode(XCore::ST16_l3r);
451     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
452   case 0x11c:
453     Inst.setOpcode(XCore::ST8_l3r);
454     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
455   case 0x12c:
456     Inst.setOpcode(XCore::ASHR_l2rus);
457     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
458   case 0x12d:
459     Inst.setOpcode(XCore::OUTPW_l2rus);
460     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
461   case 0x12e:
462     Inst.setOpcode(XCore::INPW_l2rus);
463     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
464   case 0x13c:
465     Inst.setOpcode(XCore::LDAWF_l2rus);
466     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
467   case 0x14c:
468     Inst.setOpcode(XCore::LDAWB_l2rus);
469     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
470   case 0x15c:
471     Inst.setOpcode(XCore::CRC_l3r);
472     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
473   case 0x18c:
474     Inst.setOpcode(XCore::REMS_l3r);
475     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
476   case 0x19c:
477     Inst.setOpcode(XCore::REMU_l3r);
478     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
479   }
480   return MCDisassembler::Fail;
481 }
482 
483 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn,
484                                          uint64_t Address,
485                                          const MCDisassembler *Decoder) {
486   unsigned Op1, Op2;
487   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
488                                         Op1, Op2);
489   if (S != MCDisassembler::Success)
490     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
491 
492   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
493   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
494   return S;
495 }
496 
497 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn,
498                                           uint64_t Address,
499                                           const MCDisassembler *Decoder) {
500   unsigned Op1, Op2;
501   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
502                                         Op1, Op2);
503   if (S != MCDisassembler::Success)
504     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
505 
506   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
507   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
508   return S;
509 }
510 
511 static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn,
512                                         uint64_t Address,
513                                         const MCDisassembler *Decoder) {
514   unsigned Op1, Op2, Op3;
515   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
516   if (S == MCDisassembler::Success) {
517     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
518     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
519     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
520   }
521   return S;
522 }
523 
524 static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn,
525                                            uint64_t Address,
526                                            const MCDisassembler *Decoder) {
527   unsigned Op1, Op2, Op3;
528   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
529   if (S == MCDisassembler::Success) {
530     Inst.addOperand(MCOperand::createImm(Op1));
531     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
532     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
533   }
534   return S;
535 }
536 
537 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn,
538                                           uint64_t Address,
539                                           const MCDisassembler *Decoder) {
540   unsigned Op1, Op2, Op3;
541   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
542   if (S == MCDisassembler::Success) {
543     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
544     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
545     Inst.addOperand(MCOperand::createImm(Op3));
546   }
547   return S;
548 }
549 
550 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
551                                               uint64_t Address,
552                                               const MCDisassembler *Decoder) {
553   unsigned Op1, Op2, Op3;
554   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
555   if (S == MCDisassembler::Success) {
556     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
557     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
558     DecodeBitpOperand(Inst, Op3, Address, Decoder);
559   }
560   return S;
561 }
562 
563 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,
564                                          uint64_t Address,
565                                          const MCDisassembler *Decoder) {
566   unsigned Op1, Op2, Op3;
567   DecodeStatus S =
568     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
569   if (S == MCDisassembler::Success) {
570     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
571     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
572     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
573   }
574   return S;
575 }
576 
577 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,
578                                                uint64_t Address,
579                                                const MCDisassembler *Decoder) {
580   unsigned Op1, Op2, Op3;
581   DecodeStatus S =
582   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
583   if (S == MCDisassembler::Success) {
584     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
585     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
586     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
587     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
588   }
589   return S;
590 }
591 
592 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,
593                                            uint64_t Address,
594                                            const MCDisassembler *Decoder) {
595   unsigned Op1, Op2, Op3;
596   DecodeStatus S =
597   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
598   if (S == MCDisassembler::Success) {
599     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
600     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
601     Inst.addOperand(MCOperand::createImm(Op3));
602   }
603   return S;
604 }
605 
606 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
607                                                uint64_t Address,
608                                                const MCDisassembler *Decoder) {
609   unsigned Op1, Op2, Op3;
610   DecodeStatus S =
611   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
612   if (S == MCDisassembler::Success) {
613     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
614     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
615     DecodeBitpOperand(Inst, Op3, Address, Decoder);
616   }
617   return S;
618 }
619 
620 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn,
621                                          uint64_t Address,
622                                          const MCDisassembler *Decoder) {
623   unsigned Op1, Op2, Op3, Op4, Op5, Op6;
624   DecodeStatus S =
625     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
626   if (S != MCDisassembler::Success)
627     return S;
628   S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
629   if (S != MCDisassembler::Success)
630     return S;
631   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
632   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
633   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
634   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
635   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
636   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
637   return S;
638 }
639 
640 static DecodeStatus DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn,
641                                              uint64_t Address,
642                                              const MCDisassembler *Decoder) {
643   // Try and decode as a L6R instruction.
644   Inst.clear();
645   unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
646   switch (Opcode) {
647   case 0x00:
648     Inst.setOpcode(XCore::LMUL_l6r);
649     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
650   }
651   return MCDisassembler::Fail;
652 }
653 
654 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn,
655                                          uint64_t Address,
656                                          const MCDisassembler *Decoder) {
657   unsigned Op1, Op2, Op3, Op4, Op5;
658   DecodeStatus S =
659     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
660   if (S != MCDisassembler::Success)
661     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
662   S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
663   if (S != MCDisassembler::Success)
664     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
665 
666   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
667   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
668   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
669   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
670   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
671   return S;
672 }
673 
674 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn,
675                                                uint64_t Address,
676                                                const MCDisassembler *Decoder) {
677   unsigned Op1, Op2, Op3;
678   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
679   DecodeStatus S =
680     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
681   if (S == MCDisassembler::Success) {
682     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
683     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
684   }
685   if (S == MCDisassembler::Success) {
686     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
687     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
688     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
689   }
690   return S;
691 }
692 
693 static DecodeStatus
694 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
695                                  const MCDisassembler *Decoder) {
696   unsigned Op1, Op2, Op3;
697   unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
698   DecodeStatus S =
699   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
700   if (S == MCDisassembler::Success) {
701     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
702     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
703   }
704   if (S == MCDisassembler::Success) {
705     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
706     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
707     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
708     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
709   }
710   return S;
711 }
712 
713 MCDisassembler::DecodeStatus
714 XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size,
715                                   ArrayRef<uint8_t> Bytes, uint64_t Address,
716                                   raw_ostream &cStream) const {
717   uint16_t insn16;
718 
719   if (!readInstruction16(Bytes, Address, Size, insn16)) {
720     return Fail;
721   }
722 
723   // Calling the auto-generated decoder function.
724   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
725                                           Address, this, STI);
726   if (Result != Fail) {
727     Size = 2;
728     return Result;
729   }
730 
731   uint32_t insn32;
732 
733   if (!readInstruction32(Bytes, Address, Size, insn32)) {
734     return Fail;
735   }
736 
737   // Calling the auto-generated decoder function.
738   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
739   if (Result != Fail) {
740     Size = 4;
741     return Result;
742   }
743 
744   return Fail;
745 }
746 
747 static MCDisassembler *createXCoreDisassembler(const Target &T,
748                                                const MCSubtargetInfo &STI,
749                                                MCContext &Ctx) {
750   return new XCoreDisassembler(STI, Ctx);
751 }
752 
753 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXCoreDisassembler() {
754   // Register the disassembler.
755   TargetRegistry::RegisterMCDisassembler(getTheXCoreTarget(),
756                                          createXCoreDisassembler);
757 }
758