1//===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// Instruction format superclass
11//===----------------------------------------------------------------------===//
12class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
13    : Instruction {
14  field bits<32> Inst;
15
16  let Namespace = "XCore";
17  dag OutOperandList = outs;
18  dag InOperandList = ins;
19  let AsmString   = asmstr;
20  let Pattern = pattern;
21  let Size = sz;
22  field bits<32> SoftFail = 0;
23}
24
25// XCore pseudo instructions format
26class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
27   : InstXCore<0, outs, ins, asmstr, pattern> {
28  let isPseudo = 1;
29}
30
31//===----------------------------------------------------------------------===//
32// Instruction formats
33//===----------------------------------------------------------------------===//
34
35class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
36    : InstXCore<2, outs, ins, asmstr, pattern> {
37  let Inst{15-11} = opc;
38  let DecoderMethod = "Decode3RInstruction";
39}
40
41// 3R with first operand as an immediate. Used for TSETR where the first
42// operand is treated as an immediate since it refers to a register number in
43// another thread.
44class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45    : _F3R<opc, outs, ins, asmstr, pattern> {
46  let DecoderMethod = "Decode3RImmInstruction";
47}
48
49class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
50    : InstXCore<4, outs, ins, asmstr, pattern> {
51  let Inst{31-27} = opc{8-4};
52  let Inst{26-20} = 0b1111110;
53  let Inst{19-16} = opc{3-0};
54
55  let Inst{15-11} = 0b11111;
56  let DecoderMethod = "DecodeL3RInstruction";
57}
58
59// L3R with first operand as both a source and a destination.
60class _FL3RSrcDst<bits<9> opc, dag outs, dag ins, string asmstr,
61                  list<dag> pattern> : _FL3R<opc, outs, ins, asmstr, pattern> {
62  let DecoderMethod = "DecodeL3RSrcDstInstruction";
63}
64
65class _F2RUS<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
66    : InstXCore<2, outs, ins, asmstr, pattern> {
67  let Inst{15-11} = opc;
68  let DecoderMethod = "Decode2RUSInstruction";
69}
70
71// 2RUS with bitp operand
72class _F2RUSBitp<bits<5> opc, dag outs, dag ins, string asmstr,
73                 list<dag> pattern>
74    : _F2RUS<opc, outs, ins, asmstr, pattern> {
75  let DecoderMethod = "Decode2RUSBitpInstruction";
76}
77
78class _FL2RUS<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
79    : InstXCore<4, outs, ins, asmstr, pattern> {
80  let Inst{31-27} = opc{8-4};
81  let Inst{26-20} = 0b1111110;
82  let Inst{19-16} = opc{3-0};
83
84  let Inst{15-11} = 0b11111;
85  let DecoderMethod = "DecodeL2RUSInstruction";
86}
87
88// L2RUS with bitp operand
89class _FL2RUSBitp<bits<9> opc, dag outs, dag ins, string asmstr,
90                  list<dag> pattern>
91    : _FL2RUS<opc, outs, ins, asmstr, pattern> {
92  let DecoderMethod = "DecodeL2RUSBitpInstruction";
93}
94
95class _FRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
96    : InstXCore<2, outs, ins, asmstr, pattern> {
97  bits<4> a;
98  bits<6> b;
99
100  let Inst{15-10} = opc;
101  let Inst{9-6} = a;
102  let Inst{5-0} = b;
103}
104
105class _FLRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
106    : InstXCore<4, outs, ins, asmstr, pattern> {
107  bits<4> a;
108  bits<16> b;
109
110  let Inst{31-26} = opc;
111  let Inst{25-22} = a;
112  let Inst{21-16} = b{5-0};
113  let Inst{15-10} = 0b111100;
114  let Inst{9-0} = b{15-6};
115}
116
117class _FU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
118    : InstXCore<2, outs, ins, asmstr, pattern> {
119  bits<6> a;
120
121  let Inst{15-6} = opc;
122  let Inst{5-0} = a;
123}
124
125class _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
126    : InstXCore<4, outs, ins, asmstr, pattern> {
127  bits<16> a;
128
129  let Inst{31-22} = opc;
130  let Inst{21-16} = a{5-0};
131  let Inst{15-10} = 0b111100;
132  let Inst{9-0} = a{15-6};
133}
134
135class _FU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
136    : InstXCore<2, outs, ins, asmstr, pattern> {
137  bits<10> a;
138
139  let Inst{15-10} = opc;
140  let Inst{9-0} = a;
141}
142
143class _FLU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
144    : InstXCore<4, outs, ins, asmstr, pattern> {
145  bits<20> a;
146
147  let Inst{31-26} = opc;
148  let Inst{25-16} = a{9-0};
149  let Inst{15-10} = 0b111100;
150  let Inst{9-0} = a{19-10};
151}
152
153class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
154    : InstXCore<2, outs, ins, asmstr, pattern> {
155  let Inst{15-11} = opc{5-1};
156  let Inst{4} = opc{0};
157  let DecoderMethod = "Decode2RInstruction";
158}
159
160// 2R with first operand as an immediate. Used for TSETMR where the first
161// operand is treated as an immediate since it refers to a register number in
162// another thread.
163class _F2RImm<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
164    : _F2R<opc, outs, ins, asmstr, pattern> {
165  let DecoderMethod = "Decode2RImmInstruction";
166}
167
168// 2R with first operand as both a source and a destination.
169class _F2RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
170                 list<dag> pattern> : _F2R<opc, outs, ins, asmstr, pattern> {
171  let DecoderMethod = "Decode2RSrcDstInstruction";
172}
173
174// Same as 2R with last two operands swapped
175class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
176    : _F2R<opc, outs, ins, asmstr, pattern> {
177  let DecoderMethod = "DecodeR2RInstruction";
178}
179
180class _FRUS<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
181    : InstXCore<2, outs, ins, asmstr, pattern> {
182  let Inst{15-11} = opc{5-1};
183  let Inst{4} = opc{0};
184  let DecoderMethod = "DecodeRUSInstruction";
185}
186
187// RUS with bitp operand
188class _FRUSBitp<bits<6> opc, dag outs, dag ins, string asmstr,
189                list<dag> pattern>
190    : _FRUS<opc, outs, ins, asmstr, pattern> {
191  let DecoderMethod = "DecodeRUSBitpInstruction";
192}
193
194// RUS with first operand as both a source and a destination and a bitp second
195// operand
196class _FRUSSrcDstBitp<bits<6> opc, dag outs, dag ins, string asmstr,
197                      list<dag> pattern>
198    : _FRUS<opc, outs, ins, asmstr, pattern> {
199  let DecoderMethod = "DecodeRUSSrcDstBitpInstruction";
200}
201
202class _FL2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
203    : InstXCore<4, outs, ins, asmstr, pattern> {
204  let Inst{31-27} = opc{9-5};
205  let Inst{26-20} = 0b1111110;
206  let Inst{19-16} = opc{4-1};
207
208  let Inst{15-11} = 0b11111;
209  let Inst{4} = opc{0};
210  let DecoderMethod = "DecodeL2RInstruction";
211}
212
213// Same as L2R with last two operands swapped
214class _FLR2R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
215    : _FL2R<opc, outs, ins, asmstr, pattern> {
216  let DecoderMethod = "DecodeLR2RInstruction";
217}
218
219class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
220    : InstXCore<2, outs, ins, asmstr, pattern> {
221  bits<4> a;
222
223  let Inst{15-11} = opc{5-1};
224  let Inst{10-5} = 0b111111;
225  let Inst{4} = opc{0};
226  let Inst{3-0} = a;
227}
228
229class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
230    : InstXCore<2, outs, ins, asmstr, pattern> {
231  let Inst{15-11} = opc{9-5};
232  let Inst{10-5} = 0b111111;
233  let Inst{4-0} = opc{4-0};
234}
235
236class _FL4R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
237    : InstXCore<4, outs, ins, asmstr, pattern> {
238  bits<4> d;
239
240  let Inst{31-27} = opc{5-1};
241  let Inst{26-21} = 0b111111;
242  let Inst{20} = opc{0};
243  let Inst{19-16} = d;
244  let Inst{15-11} = 0b11111;
245}
246
247// L4R with 4th operand as both a source and a destination.
248class _FL4RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
249                  list<dag> pattern>
250    : _FL4R<opc, outs, ins, asmstr, pattern> {
251  let DecoderMethod = "DecodeL4RSrcDstInstruction";
252}
253
254// L4R with 1st and 4th operand as both a source and a destination.
255class _FL4RSrcDstSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
256                        list<dag> pattern>
257    : _FL4R<opc, outs, ins, asmstr, pattern> {
258  let DecoderMethod = "DecodeL4RSrcDstSrcDstInstruction";
259}
260
261class _FL5R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
262    : InstXCore<4, outs, ins, asmstr, pattern> {
263  let Inst{31-27} = opc{5-1};
264  let Inst{20} = opc{0};
265  let Inst{15-11} = 0b11111;
266
267  let DecoderMethod = "DecodeL5RInstruction";
268}
269
270class _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
271    : InstXCore<4, outs, ins, asmstr, pattern> {
272  let Inst{31-27} = opc;
273  let Inst{15-11} = 0b11111;
274
275  let DecoderMethod = "DecodeL6RInstruction";
276}
277