1 //===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the XCore implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "XCoreInstrInfo.h" 14 #include "XCore.h" 15 #include "XCoreMachineFunctionInfo.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/CodeGen/MachineConstantPool.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/IR/Constants.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/MC/MCContext.h" 24 #include "llvm/MC/TargetRegistry.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 28 using namespace llvm; 29 30 #define GET_INSTRINFO_CTOR_DTOR 31 #include "XCoreGenInstrInfo.inc" 32 33 namespace llvm { 34 namespace XCore { 35 36 // XCore Condition Codes 37 enum CondCode { 38 COND_TRUE, 39 COND_FALSE, 40 COND_INVALID 41 }; 42 } 43 } 44 45 // Pin the vtable to this file. 46 void XCoreInstrInfo::anchor() {} 47 48 XCoreInstrInfo::XCoreInstrInfo() 49 : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), 50 RI() { 51 } 52 53 static bool isZeroImm(const MachineOperand &op) { 54 return op.isImm() && op.getImm() == 0; 55 } 56 57 /// isLoadFromStackSlot - If the specified machine instruction is a direct 58 /// load from a stack slot, return the virtual or physical register number of 59 /// the destination along with the FrameIndex of the loaded stack slot. If 60 /// not, return 0. This predicate must return 0 if the instruction has 61 /// any side effects other than loading from the stack slot. 62 unsigned XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 63 int &FrameIndex) const { 64 int Opcode = MI.getOpcode(); 65 if (Opcode == XCore::LDWFI) 66 { 67 if ((MI.getOperand(1).isFI()) && // is a stack slot 68 (MI.getOperand(2).isImm()) && // the imm is zero 69 (isZeroImm(MI.getOperand(2)))) { 70 FrameIndex = MI.getOperand(1).getIndex(); 71 return MI.getOperand(0).getReg(); 72 } 73 } 74 return 0; 75 } 76 77 /// isStoreToStackSlot - If the specified machine instruction is a direct 78 /// store to a stack slot, return the virtual or physical register number of 79 /// the source reg along with the FrameIndex of the loaded stack slot. If 80 /// not, return 0. This predicate must return 0 if the instruction has 81 /// any side effects other than storing to the stack slot. 82 unsigned XCoreInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 83 int &FrameIndex) const { 84 int Opcode = MI.getOpcode(); 85 if (Opcode == XCore::STWFI) 86 { 87 if ((MI.getOperand(1).isFI()) && // is a stack slot 88 (MI.getOperand(2).isImm()) && // the imm is zero 89 (isZeroImm(MI.getOperand(2)))) { 90 FrameIndex = MI.getOperand(1).getIndex(); 91 return MI.getOperand(0).getReg(); 92 } 93 } 94 return 0; 95 } 96 97 //===----------------------------------------------------------------------===// 98 // Branch Analysis 99 //===----------------------------------------------------------------------===// 100 101 static inline bool IsBRU(unsigned BrOpc) { 102 return BrOpc == XCore::BRFU_u6 103 || BrOpc == XCore::BRFU_lu6 104 || BrOpc == XCore::BRBU_u6 105 || BrOpc == XCore::BRBU_lu6; 106 } 107 108 static inline bool IsBRT(unsigned BrOpc) { 109 return BrOpc == XCore::BRFT_ru6 110 || BrOpc == XCore::BRFT_lru6 111 || BrOpc == XCore::BRBT_ru6 112 || BrOpc == XCore::BRBT_lru6; 113 } 114 115 static inline bool IsBRF(unsigned BrOpc) { 116 return BrOpc == XCore::BRFF_ru6 117 || BrOpc == XCore::BRFF_lru6 118 || BrOpc == XCore::BRBF_ru6 119 || BrOpc == XCore::BRBF_lru6; 120 } 121 122 static inline bool IsCondBranch(unsigned BrOpc) { 123 return IsBRF(BrOpc) || IsBRT(BrOpc); 124 } 125 126 static inline bool IsBR_JT(unsigned BrOpc) { 127 return BrOpc == XCore::BR_JT 128 || BrOpc == XCore::BR_JT32; 129 } 130 131 /// GetCondFromBranchOpc - Return the XCore CC that matches 132 /// the correspondent Branch instruction opcode. 133 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) 134 { 135 if (IsBRT(BrOpc)) { 136 return XCore::COND_TRUE; 137 } else if (IsBRF(BrOpc)) { 138 return XCore::COND_FALSE; 139 } else { 140 return XCore::COND_INVALID; 141 } 142 } 143 144 /// GetCondBranchFromCond - Return the Branch instruction 145 /// opcode that matches the cc. 146 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) 147 { 148 switch (CC) { 149 default: llvm_unreachable("Illegal condition code!"); 150 case XCore::COND_TRUE : return XCore::BRFT_lru6; 151 case XCore::COND_FALSE : return XCore::BRFF_lru6; 152 } 153 } 154 155 /// GetOppositeBranchCondition - Return the inverse of the specified 156 /// condition, e.g. turning COND_E to COND_NE. 157 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) 158 { 159 switch (CC) { 160 default: llvm_unreachable("Illegal condition code!"); 161 case XCore::COND_TRUE : return XCore::COND_FALSE; 162 case XCore::COND_FALSE : return XCore::COND_TRUE; 163 } 164 } 165 166 /// analyzeBranch - Analyze the branching code at the end of MBB, returning 167 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 168 /// implemented for a target). Upon success, this returns false and returns 169 /// with the following information in various cases: 170 /// 171 /// 1. If this block ends with no branches (it just falls through to its succ) 172 /// just return false, leaving TBB/FBB null. 173 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 174 /// the destination block. 175 /// 3. If this block ends with an conditional branch and it falls through to 176 /// an successor block, it sets TBB to be the branch destination block and a 177 /// list of operands that evaluate the condition. These 178 /// operands can be passed to other TargetInstrInfo methods to create new 179 /// branches. 180 /// 4. If this block ends with an conditional branch and an unconditional 181 /// block, it returns the 'true' destination in TBB, the 'false' destination 182 /// in FBB, and a list of operands that evaluate the condition. These 183 /// operands can be passed to other TargetInstrInfo methods to create new 184 /// branches. 185 /// 186 /// Note that removeBranch and insertBranch must be implemented to support 187 /// cases where this method returns success. 188 /// 189 bool XCoreInstrInfo::analyzeBranch(MachineBasicBlock &MBB, 190 MachineBasicBlock *&TBB, 191 MachineBasicBlock *&FBB, 192 SmallVectorImpl<MachineOperand> &Cond, 193 bool AllowModify) const { 194 // If the block has no terminators, it just falls into the block after it. 195 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 196 if (I == MBB.end()) 197 return false; 198 199 if (!isUnpredicatedTerminator(*I)) 200 return false; 201 202 // Get the last instruction in the block. 203 MachineInstr *LastInst = &*I; 204 205 // If there is only one terminator instruction, process it. 206 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 207 if (IsBRU(LastInst->getOpcode())) { 208 TBB = LastInst->getOperand(0).getMBB(); 209 return false; 210 } 211 212 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 213 if (BranchCode == XCore::COND_INVALID) 214 return true; // Can't handle indirect branch. 215 216 // Conditional branch 217 // Block ends with fall-through condbranch. 218 219 TBB = LastInst->getOperand(1).getMBB(); 220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 221 Cond.push_back(LastInst->getOperand(0)); 222 return false; 223 } 224 225 // Get the instruction before it if it's a terminator. 226 MachineInstr *SecondLastInst = &*I; 227 228 // If there are three terminators, we don't know what sort of block this is. 229 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) 230 return true; 231 232 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 233 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); 234 235 // If the block ends with conditional branch followed by unconditional, 236 // handle it. 237 if (BranchCode != XCore::COND_INVALID 238 && IsBRU(LastInst->getOpcode())) { 239 240 TBB = SecondLastInst->getOperand(1).getMBB(); 241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 242 Cond.push_back(SecondLastInst->getOperand(0)); 243 244 FBB = LastInst->getOperand(0).getMBB(); 245 return false; 246 } 247 248 // If the block ends with two unconditional branches, handle it. The second 249 // one is not executed, so remove it. 250 if (IsBRU(SecondLastInst->getOpcode()) && 251 IsBRU(LastInst->getOpcode())) { 252 TBB = SecondLastInst->getOperand(0).getMBB(); 253 I = LastInst; 254 if (AllowModify) 255 I->eraseFromParent(); 256 return false; 257 } 258 259 // Likewise if it ends with a branch table followed by an unconditional branch. 260 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { 261 I = LastInst; 262 if (AllowModify) 263 I->eraseFromParent(); 264 return true; 265 } 266 267 // Otherwise, can't handle this. 268 return true; 269 } 270 271 unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB, 272 MachineBasicBlock *TBB, 273 MachineBasicBlock *FBB, 274 ArrayRef<MachineOperand> Cond, 275 const DebugLoc &DL, 276 int *BytesAdded) const { 277 // Shouldn't be a fall through. 278 assert(TBB && "insertBranch must not be told to insert a fallthrough"); 279 assert((Cond.size() == 2 || Cond.size() == 0) && 280 "Unexpected number of components!"); 281 assert(!BytesAdded && "code size not handled"); 282 283 if (!FBB) { // One way branch. 284 if (Cond.empty()) { 285 // Unconditional branch 286 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); 287 } else { 288 // Conditional branch. 289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 291 .addMBB(TBB); 292 } 293 return 1; 294 } 295 296 // Two-way Conditional branch. 297 assert(Cond.size() == 2 && "Unexpected number of components!"); 298 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); 299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) 300 .addMBB(TBB); 301 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); 302 return 2; 303 } 304 305 unsigned 306 XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { 307 assert(!BytesRemoved && "code size not handled"); 308 309 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 310 if (I == MBB.end()) 311 return 0; 312 313 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) 314 return 0; 315 316 // Remove the branch. 317 I->eraseFromParent(); 318 319 I = MBB.end(); 320 321 if (I == MBB.begin()) return 1; 322 --I; 323 if (!IsCondBranch(I->getOpcode())) 324 return 1; 325 326 // Remove the branch. 327 I->eraseFromParent(); 328 return 2; 329 } 330 331 void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 332 MachineBasicBlock::iterator I, 333 const DebugLoc &DL, MCRegister DestReg, 334 MCRegister SrcReg, bool KillSrc) const { 335 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); 336 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); 337 338 if (GRDest && GRSrc) { 339 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) 340 .addReg(SrcReg, getKillRegState(KillSrc)) 341 .addImm(0); 342 return; 343 } 344 345 if (GRDest && SrcReg == XCore::SP) { 346 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); 347 return; 348 } 349 350 if (DestReg == XCore::SP && GRSrc) { 351 BuildMI(MBB, I, DL, get(XCore::SETSP_1r)) 352 .addReg(SrcReg, getKillRegState(KillSrc)); 353 return; 354 } 355 llvm_unreachable("Impossible reg-to-reg copy"); 356 } 357 358 void XCoreInstrInfo::storeRegToStackSlot( 359 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg, 360 bool isKill, int FrameIndex, const TargetRegisterClass *RC, 361 const TargetRegisterInfo *TRI, Register VReg) const { 362 DebugLoc DL; 363 if (I != MBB.end() && !I->isDebugInstr()) 364 DL = I->getDebugLoc(); 365 MachineFunction *MF = MBB.getParent(); 366 const MachineFrameInfo &MFI = MF->getFrameInfo(); 367 MachineMemOperand *MMO = MF->getMachineMemOperand( 368 MachinePointerInfo::getFixedStack(*MF, FrameIndex), 369 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex), 370 MFI.getObjectAlign(FrameIndex)); 371 BuildMI(MBB, I, DL, get(XCore::STWFI)) 372 .addReg(SrcReg, getKillRegState(isKill)) 373 .addFrameIndex(FrameIndex) 374 .addImm(0) 375 .addMemOperand(MMO); 376 } 377 378 void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 379 MachineBasicBlock::iterator I, 380 Register DestReg, int FrameIndex, 381 const TargetRegisterClass *RC, 382 const TargetRegisterInfo *TRI, 383 Register VReg) const { 384 DebugLoc DL; 385 if (I != MBB.end() && !I->isDebugInstr()) 386 DL = I->getDebugLoc(); 387 MachineFunction *MF = MBB.getParent(); 388 const MachineFrameInfo &MFI = MF->getFrameInfo(); 389 MachineMemOperand *MMO = MF->getMachineMemOperand( 390 MachinePointerInfo::getFixedStack(*MF, FrameIndex), 391 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex), 392 MFI.getObjectAlign(FrameIndex)); 393 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) 394 .addFrameIndex(FrameIndex) 395 .addImm(0) 396 .addMemOperand(MMO); 397 } 398 399 bool XCoreInstrInfo:: 400 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 401 assert((Cond.size() == 2) && 402 "Invalid XCore branch condition!"); 403 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); 404 return false; 405 } 406 407 static inline bool isImmU6(unsigned val) { 408 return val < (1 << 6); 409 } 410 411 static inline bool isImmU16(unsigned val) { 412 return val < (1 << 16); 413 } 414 415 static bool isImmMskBitp(unsigned val) { 416 if (!isMask_32(val)) { 417 return false; 418 } 419 int N = llvm::bit_width(val); 420 return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32; 421 } 422 423 MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate( 424 MachineBasicBlock &MBB, 425 MachineBasicBlock::iterator MI, 426 unsigned Reg, uint64_t Value) const { 427 DebugLoc dl; 428 if (MI != MBB.end() && !MI->isDebugInstr()) 429 dl = MI->getDebugLoc(); 430 if (isImmMskBitp(Value)) { 431 int N = llvm::bit_width(Value); 432 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg) 433 .addImm(N) 434 .getInstr(); 435 } 436 if (isImmU16(Value)) { 437 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; 438 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr(); 439 } 440 MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool(); 441 const Constant *C = ConstantInt::get( 442 Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), Value); 443 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align(4)); 444 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg) 445 .addConstantPoolIndex(Idx) 446 .getInstr(); 447 } 448