1//===- XtensaInstrFormats.td - Xtensa Instruction Formats --*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
6// See https://llvm.org/LICENSE.txt for license information.
7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8//
9//===----------------------------------------------------------------------===//
10
11// Base class for Xtensa 16 & 24 bit Formats
12class XtensaInst<int size, dag outs, dag ins, string asmstr, list<dag> pattern,
13                 InstrItinClass itin = NoItinerary>
14  : Instruction {
15  let Namespace = "Xtensa";
16
17  let Size = size;
18
19  let OutOperandList = outs;
20  let InOperandList  = ins;
21
22  let AsmString   = asmstr;
23  let Pattern     = pattern;
24  let Itinerary   = itin;
25
26}
27
28// Base class for Xtensa 24 bit Format
29class XtensaInst24<dag outs, dag ins, string asmstr, list<dag> pattern,
30                   InstrItinClass itin = NoItinerary>
31  : XtensaInst<3, outs, ins, asmstr, pattern, itin> {
32  field bits<24> Inst;
33  field bits<24> SoftFail = 0;
34}
35
36// Base class for Xtensa 16 bit Format
37class XtensaInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
38                   InstrItinClass itin = NoItinerary>
39  : XtensaInst<2, outs, ins, asmstr, pattern, itin> {
40  field bits<16> Inst;
41  field bits<16> SoftFail = 0;
42  let Predicates = [HasDensity];
43}
44
45class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
46               string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
47  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
48  bits<4> r;
49  bits<4> s;
50  bits<4> t;
51
52  let Inst{23-20} = op2;
53  let Inst{19-16} = op1;
54  let Inst{15-12} = r;
55  let Inst{11-8} = s;
56  let Inst{7-4} = t;
57  let Inst{3-0} = op0;
58}
59
60class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
61                string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
62  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
63  bits<4> r;
64  bits<4> s;
65  bits<4> t;
66  bits<4> imm4;
67
68  let Inst{23-20} = imm4;
69  let Inst{19-16} = op1;
70  let Inst{15-12} = r;
71  let Inst{11-8} = s;
72  let Inst{7-4} = t;
73  let Inst{3-0} = op0;
74}
75
76class RRI8_Inst<bits<4> op0, dag outs, dag ins,
77                string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
78  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
79  bits<4> r;
80  bits<4> s;
81  bits<4> t;
82  bits<8> imm8;
83
84  let Inst{23-16} = imm8;
85  let Inst{15-12} = r;
86  let Inst{11-8} = s;
87  let Inst{7-4} = t;
88  let Inst{3-0} = op0;
89}
90
91class RI16_Inst<bits<4> op0, dag outs, dag ins,
92                string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
93  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
94  bits<4> t;
95  bits<16> imm16;
96
97  let Inst{23-8} = imm16;
98  let Inst{7-4} = t;
99  let Inst{3-0} = op0;
100}
101
102class RSR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
103               string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
104  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
105  bits<8> sr;
106  bits<4> t;
107
108  let Inst{23-20} = op2;
109  let Inst{19-16} = op1;
110  let Inst{15-8} = sr;
111  let Inst{7-4} = t;
112  let Inst{3-0} = op0;
113}
114
115class CALL_Inst<bits<4> op0, dag outs, dag ins,
116                string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
117  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
118  bits<18> offset;
119  bits<2> n;
120
121  let Inst{23-6} = offset;
122  let Inst{5-4} = n;
123  let Inst{3-0} = op0;
124}
125
126class CALLX_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
127                 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
128  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
129  bits<4> r;
130  bits<4> s;
131  bits<2> m;
132  bits<2> n;
133
134  let Inst{23-20} = op2;
135  let Inst{19-16} = op1;
136  let Inst{15-12} = r;
137  let Inst{11-8} = s;
138  let Inst{7-6} = m;
139  let Inst{5-4} = n;
140  let Inst{3-0} = op0;
141}
142
143class BRI8_Inst<bits<4> op0, dag outs, dag ins,
144                string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
145  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
146  bits<8> imm8;
147  bits<4> r;
148  bits<4> s;
149  bits<2> m;
150  bits<2> n;
151
152  let Inst{23-16} = imm8;
153  let Inst{15-12} = r;
154  let Inst{11-8} = s;
155  let Inst{7-6} = m;
156  let Inst{5-4} = n;
157  let Inst{3-0} = op0;
158}
159
160class BRI12_Inst<bits<4> op0, bits<2> n, bits<2> m, dag outs, dag ins,
161                 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
162  : XtensaInst24<outs, ins, asmstr, pattern, itin> {
163  bits<12> imm12;
164  bits<4> s;
165
166  let Inst{23-12} = imm12;
167  let Inst{11-8} = s;
168  let Inst{7-6} = m;
169  let Inst{5-4} = n;
170  let Inst{3-0} = op0;
171}
172
173class RRRN_Inst<bits<4> op0, dag outs, dag ins,
174                string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
175  : XtensaInst16<outs, ins, asmstr, pattern, itin> {
176  bits<4> r;
177  bits<4> s;
178  bits<4> t;
179
180  let Inst{15-12} = r;
181  let Inst{11-8} = s;
182  let Inst{7-4} = t;
183  let Inst{3-0} = op0;
184}
185
186class RI7_Inst<bits<4> op0, bits<1> i, dag outs, dag ins,
187               string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
188  : XtensaInst16<outs, ins, asmstr, pattern, itin> {
189  bits<7> imm7;
190  bits<4> s;
191
192  let Inst{15-12} = imm7{3-0};
193  let Inst{11-8} = s;
194  let Inst{7} = i;
195  let Inst{6-4} = imm7{6-4};
196  let Inst{3-0} = op0;
197}
198
199class RI6_Inst<bits<4> op0, bits<1> i,  bits<1> z, dag outs, dag ins,
200               string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
201  : XtensaInst16<outs, ins, asmstr, pattern, itin> {
202  bits<6> imm6;
203  bits<4> s;
204
205  let Inst{15-12} = imm6{3-0};
206  let Inst{11-8} = s;
207  let Inst{7} = i;
208  let Inst{6} = z;
209  let Inst{5-4} = imm6{5-4};
210  let Inst{3-0} = op0;
211}
212
213// Pseudo instructions
214class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
215  : XtensaInst<2, outs, ins, asmstr, pattern> {
216  let isPseudo = 1;
217  let isCodeGenOnly = 1;
218}
219