1 //===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a wrapper class for the 'Instruction' TableGen class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
14 #define LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
15 
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/Support/MachineValueType.h"
19 #include "llvm/Support/SMLoc.h"
20 #include <cassert>
21 #include <string>
22 #include <utility>
23 #include <vector>
24 
25 namespace llvm {
26 template <typename T> class ArrayRef;
27   class Record;
28   class DagInit;
29   class CodeGenTarget;
30 
31   class CGIOperandList {
32   public:
33     class ConstraintInfo {
34       enum { None, EarlyClobber, Tied } Kind = None;
35       unsigned OtherTiedOperand = 0;
36 
37     public:
38       ConstraintInfo() = default;
39 
40       static ConstraintInfo getEarlyClobber() {
41         ConstraintInfo I;
42         I.Kind = EarlyClobber;
43         I.OtherTiedOperand = 0;
44         return I;
45       }
46 
47       static ConstraintInfo getTied(unsigned Op) {
48         ConstraintInfo I;
49         I.Kind = Tied;
50         I.OtherTiedOperand = Op;
51         return I;
52       }
53 
54       bool isNone() const { return Kind == None; }
55       bool isEarlyClobber() const { return Kind == EarlyClobber; }
56       bool isTied() const { return Kind == Tied; }
57 
58       unsigned getTiedOperand() const {
59         assert(isTied());
60         return OtherTiedOperand;
61       }
62 
63       bool operator==(const ConstraintInfo &RHS) const {
64         if (Kind != RHS.Kind)
65           return false;
66         if (Kind == Tied && OtherTiedOperand != RHS.OtherTiedOperand)
67           return false;
68         return true;
69       }
70       bool operator!=(const ConstraintInfo &RHS) const {
71         return !(*this == RHS);
72       }
73     };
74 
75     /// OperandInfo - The information we keep track of for each operand in the
76     /// operand list for a tablegen instruction.
77     struct OperandInfo {
78       /// Rec - The definition this operand is declared as.
79       ///
80       Record *Rec;
81 
82       /// Name - If this operand was assigned a symbolic name, this is it,
83       /// otherwise, it's empty.
84       std::string Name;
85 
86       /// PrinterMethodName - The method used to print operands of this type in
87       /// the asmprinter.
88       std::string PrinterMethodName;
89 
90       /// EncoderMethodName - The method used to get the machine operand value
91       /// for binary encoding. "getMachineOpValue" by default.
92       std::string EncoderMethodName;
93 
94       /// OperandType - A value from MCOI::OperandType representing the type of
95       /// the operand.
96       std::string OperandType;
97 
98       /// MIOperandNo - Currently (this is meant to be phased out), some logical
99       /// operands correspond to multiple MachineInstr operands.  In the X86
100       /// target for example, one address operand is represented as 4
101       /// MachineOperands.  Because of this, the operand number in the
102       /// OperandList may not match the MachineInstr operand num.  Until it
103       /// does, this contains the MI operand index of this operand.
104       unsigned MIOperandNo;
105       unsigned MINumOperands;   // The number of operands.
106 
107       /// DoNotEncode - Bools are set to true in this vector for each operand in
108       /// the DisableEncoding list.  These should not be emitted by the code
109       /// emitter.
110       BitVector DoNotEncode;
111 
112       /// MIOperandInfo - Default MI operand type. Note an operand may be made
113       /// up of multiple MI operands.
114       DagInit *MIOperandInfo;
115 
116       /// Constraint info for this operand.  This operand can have pieces, so we
117       /// track constraint info for each.
118       std::vector<ConstraintInfo> Constraints;
119 
120       OperandInfo(Record *R, const std::string &N, const std::string &PMN,
121                   const std::string &EMN, const std::string &OT, unsigned MION,
122                   unsigned MINO, DagInit *MIOI)
123       : Rec(R), Name(N), PrinterMethodName(PMN), EncoderMethodName(EMN),
124         OperandType(OT), MIOperandNo(MION), MINumOperands(MINO),
125         MIOperandInfo(MIOI) {}
126 
127 
128       /// getTiedOperand - If this operand is tied to another one, return the
129       /// other operand number.  Otherwise, return -1.
130       int getTiedRegister() const {
131         for (unsigned j = 0, e = Constraints.size(); j != e; ++j) {
132           const CGIOperandList::ConstraintInfo &CI = Constraints[j];
133           if (CI.isTied()) return CI.getTiedOperand();
134         }
135         return -1;
136       }
137     };
138 
139     CGIOperandList(Record *D);
140 
141     Record *TheDef;            // The actual record containing this OperandList.
142 
143     /// NumDefs - Number of def operands declared, this is the number of
144     /// elements in the instruction's (outs) list.
145     ///
146     unsigned NumDefs;
147 
148     /// OperandList - The list of declared operands, along with their declared
149     /// type (which is a record).
150     std::vector<OperandInfo> OperandList;
151 
152     // Information gleaned from the operand list.
153     bool isPredicable;
154     bool hasOptionalDef;
155     bool isVariadic;
156 
157     // Provide transparent accessors to the operand list.
158     bool empty() const { return OperandList.empty(); }
159     unsigned size() const { return OperandList.size(); }
160     const OperandInfo &operator[](unsigned i) const { return OperandList[i]; }
161     OperandInfo &operator[](unsigned i) { return OperandList[i]; }
162     OperandInfo &back() { return OperandList.back(); }
163     const OperandInfo &back() const { return OperandList.back(); }
164 
165     typedef std::vector<OperandInfo>::iterator iterator;
166     typedef std::vector<OperandInfo>::const_iterator const_iterator;
167     iterator begin() { return OperandList.begin(); }
168     const_iterator begin() const { return OperandList.begin(); }
169     iterator end() { return OperandList.end(); }
170     const_iterator end() const { return OperandList.end(); }
171 
172     /// getOperandNamed - Return the index of the operand with the specified
173     /// non-empty name.  If the instruction does not have an operand with the
174     /// specified name, abort.
175     unsigned getOperandNamed(StringRef Name) const;
176 
177     /// hasOperandNamed - Query whether the instruction has an operand of the
178     /// given name. If so, return true and set OpIdx to the index of the
179     /// operand. Otherwise, return false.
180     bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
181 
182     /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
183     /// where $foo is a whole operand and $foo.bar refers to a suboperand.
184     /// This aborts if the name is invalid.  If AllowWholeOp is true, references
185     /// to operands with suboperands are allowed, otherwise not.
186     std::pair<unsigned,unsigned> ParseOperandName(StringRef Op,
187                                                   bool AllowWholeOp = true);
188 
189     /// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
190     /// flat machineinstr operand #.
191     unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
192       return OperandList[Op.first].MIOperandNo + Op.second;
193     }
194 
195     /// getSubOperandNumber - Unflatten a operand number into an
196     /// operand/suboperand pair.
197     std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
198       for (unsigned i = 0; ; ++i) {
199         assert(i < OperandList.size() && "Invalid flat operand #");
200         if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
201           return std::make_pair(i, Op-OperandList[i].MIOperandNo);
202       }
203     }
204 
205 
206     /// isFlatOperandNotEmitted - Return true if the specified flat operand #
207     /// should not be emitted with the code emitter.
208     bool isFlatOperandNotEmitted(unsigned FlatOpNo) const {
209       std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo);
210       if (OperandList[Op.first].DoNotEncode.size() > Op.second)
211         return OperandList[Op.first].DoNotEncode[Op.second];
212       return false;
213     }
214 
215     void ProcessDisableEncoding(StringRef Value);
216   };
217 
218 
219   class CodeGenInstruction {
220   public:
221     Record *TheDef;            // The actual record defining this instruction.
222     StringRef Namespace;       // The namespace the instruction is in.
223 
224     /// AsmString - The format string used to emit a .s file for the
225     /// instruction.
226     std::string AsmString;
227 
228     /// Operands - This is information about the (ins) and (outs) list specified
229     /// to the instruction.
230     CGIOperandList Operands;
231 
232     /// ImplicitDefs/ImplicitUses - These are lists of registers that are
233     /// implicitly defined and used by the instruction.
234     std::vector<Record*> ImplicitDefs, ImplicitUses;
235 
236     // Various boolean values we track for the instruction.
237     bool isPreISelOpcode : 1;
238     bool isReturn : 1;
239     bool isEHScopeReturn : 1;
240     bool isBranch : 1;
241     bool isIndirectBranch : 1;
242     bool isCompare : 1;
243     bool isMoveImm : 1;
244     bool isMoveReg : 1;
245     bool isBitcast : 1;
246     bool isSelect : 1;
247     bool isBarrier : 1;
248     bool isCall : 1;
249     bool isAdd : 1;
250     bool isTrap : 1;
251     bool canFoldAsLoad : 1;
252     bool mayLoad : 1;
253     bool mayLoad_Unset : 1;
254     bool mayStore : 1;
255     bool mayStore_Unset : 1;
256     bool mayRaiseFPException : 1;
257     bool isPredicable : 1;
258     bool isConvertibleToThreeAddress : 1;
259     bool isCommutable : 1;
260     bool isTerminator : 1;
261     bool isReMaterializable : 1;
262     bool hasDelaySlot : 1;
263     bool usesCustomInserter : 1;
264     bool hasPostISelHook : 1;
265     bool hasCtrlDep : 1;
266     bool isNotDuplicable : 1;
267     bool hasSideEffects : 1;
268     bool hasSideEffects_Unset : 1;
269     bool isAsCheapAsAMove : 1;
270     bool hasExtraSrcRegAllocReq : 1;
271     bool hasExtraDefRegAllocReq : 1;
272     bool isCodeGenOnly : 1;
273     bool isPseudo : 1;
274     bool isRegSequence : 1;
275     bool isExtractSubreg : 1;
276     bool isInsertSubreg : 1;
277     bool isConvergent : 1;
278     bool hasNoSchedulingInfo : 1;
279     bool FastISelShouldIgnore : 1;
280     bool hasChain : 1;
281     bool hasChain_Inferred : 1;
282     bool variadicOpsAreDefs : 1;
283     bool isAuthenticated : 1;
284 
285     std::string DeprecatedReason;
286     bool HasComplexDeprecationPredicate;
287 
288     /// Are there any undefined flags?
289     bool hasUndefFlags() const {
290       return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
291     }
292 
293     // The record used to infer instruction flags, or NULL if no flag values
294     // have been inferred.
295     Record *InferredFrom;
296 
297     CodeGenInstruction(Record *R);
298 
299     /// HasOneImplicitDefWithKnownVT - If the instruction has at least one
300     /// implicit def and it has a known VT, return the VT, otherwise return
301     /// MVT::Other.
302     MVT::SimpleValueType
303       HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const;
304 
305 
306     /// FlattenAsmStringVariants - Flatten the specified AsmString to only
307     /// include text from the specified variant, returning the new string.
308     static std::string FlattenAsmStringVariants(StringRef AsmString,
309                                                 unsigned Variant);
310 
311     // Is the specified operand in a generic instruction implicitly a pointer.
312     // This can be used on intructions that use typeN or ptypeN to identify
313     // operands that should be considered as pointers even though SelectionDAG
314     // didn't make a distinction between integer and pointers.
315     bool isOperandAPointer(unsigned i) const {
316       return isOperandImpl(i, "IsPointer");
317     }
318 
319     /// Check if the operand is required to be an immediate.
320     bool isOperandImmArg(unsigned i) const {
321       return isOperandImpl(i, "IsImmediate");
322     }
323 
324   private:
325     bool isOperandImpl(unsigned i, StringRef PropertyName) const;
326   };
327 
328 
329   /// CodeGenInstAlias - This represents an InstAlias definition.
330   class CodeGenInstAlias {
331   public:
332     Record *TheDef;            // The actual record defining this InstAlias.
333 
334     /// AsmString - The format string used to emit a .s file for the
335     /// instruction.
336     std::string AsmString;
337 
338     /// Result - The result instruction.
339     DagInit *Result;
340 
341     /// ResultInst - The instruction generated by the alias (decoded from
342     /// Result).
343     CodeGenInstruction *ResultInst;
344 
345 
346     struct ResultOperand {
347     private:
348       std::string Name;
349       Record *R = nullptr;
350       int64_t Imm = 0;
351 
352     public:
353       enum {
354         K_Record,
355         K_Imm,
356         K_Reg
357       } Kind;
358 
359       ResultOperand(std::string N, Record *r)
360           : Name(std::move(N)), R(r), Kind(K_Record) {}
361       ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
362       ResultOperand(Record *r) : R(r), Kind(K_Reg) {}
363 
364       bool isRecord() const { return Kind == K_Record; }
365       bool isImm() const { return Kind == K_Imm; }
366       bool isReg() const { return Kind == K_Reg; }
367 
368       StringRef getName() const { assert(isRecord()); return Name; }
369       Record *getRecord() const { assert(isRecord()); return R; }
370       int64_t getImm() const { assert(isImm()); return Imm; }
371       Record *getRegister() const { assert(isReg()); return R; }
372 
373       unsigned getMINumOperands() const;
374     };
375 
376     /// ResultOperands - The decoded operands for the result instruction.
377     std::vector<ResultOperand> ResultOperands;
378 
379     /// ResultInstOperandIndex - For each operand, this vector holds a pair of
380     /// indices to identify the corresponding operand in the result
381     /// instruction.  The first index specifies the operand and the second
382     /// index specifies the suboperand.  If there are no suboperands or if all
383     /// of them are matched by the operand, the second value should be -1.
384     std::vector<std::pair<unsigned, int> > ResultInstOperandIndex;
385 
386     CodeGenInstAlias(Record *R, CodeGenTarget &T);
387 
388     bool tryAliasOpMatch(DagInit *Result, unsigned AliasOpNo,
389                          Record *InstOpRec, bool hasSubOps, ArrayRef<SMLoc> Loc,
390                          CodeGenTarget &T, ResultOperand &ResOp);
391   };
392 }
393 
394 #endif
395