1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines structures to encapsulate information gleaned from the 10 // target register and register class definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 15 #define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 16 17 #include "InfoByHwMode.h" 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/ADT/BitVector.h" 20 #include "llvm/ADT/DenseMap.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/SetVector.h" 23 #include "llvm/ADT/SmallPtrSet.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/ADT/SparseBitVector.h" 26 #include "llvm/ADT/StringMap.h" 27 #include "llvm/ADT/StringRef.h" 28 #include "llvm/MC/LaneBitmask.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/TableGen/Record.h" 31 #include "llvm/TableGen/SetTheory.h" 32 #include <cassert> 33 #include <cstdint> 34 #include <deque> 35 #include <list> 36 #include <map> 37 #include <string> 38 #include <utility> 39 #include <vector> 40 41 namespace llvm { 42 43 class CodeGenRegBank; 44 template <typename T, typename Vector, typename Set> class SetVector; 45 46 /// Used to encode a step in a register lane mask transformation. 47 /// Mask the bits specified in Mask, then rotate them Rol bits to the left 48 /// assuming a wraparound at 32bits. 49 struct MaskRolPair { 50 LaneBitmask Mask; 51 uint8_t RotateLeft; 52 53 bool operator==(const MaskRolPair Other) const { 54 return Mask == Other.Mask && RotateLeft == Other.RotateLeft; 55 } 56 bool operator!=(const MaskRolPair Other) const { 57 return Mask != Other.Mask || RotateLeft != Other.RotateLeft; 58 } 59 }; 60 61 /// CodeGenSubRegIndex - Represents a sub-register index. 62 class CodeGenSubRegIndex { 63 Record *const TheDef; 64 std::string Name; 65 std::string Namespace; 66 67 public: 68 uint16_t Size; 69 uint16_t Offset; 70 const unsigned EnumValue; 71 mutable LaneBitmask LaneMask; 72 mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform; 73 74 /// A list of subregister indexes concatenated resulting in this 75 /// subregister index. This is the reverse of CodeGenRegBank::ConcatIdx. 76 SmallVector<CodeGenSubRegIndex*,4> ConcatenationOf; 77 78 // Are all super-registers containing this SubRegIndex covered by their 79 // sub-registers? 80 bool AllSuperRegsCovered; 81 // A subregister index is "artificial" if every subregister obtained 82 // from applying this index is artificial. Artificial subregister 83 // indexes are not used to create new register classes. 84 bool Artificial; 85 86 CodeGenSubRegIndex(Record *R, unsigned Enum); 87 CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum); 88 CodeGenSubRegIndex(CodeGenSubRegIndex&) = delete; 89 90 const std::string &getName() const { return Name; } 91 const std::string &getNamespace() const { return Namespace; } 92 std::string getQualifiedName() const; 93 94 // Map of composite subreg indices. 95 typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *, 96 deref<std::less<>>> 97 CompMap; 98 99 // Returns the subreg index that results from composing this with Idx. 100 // Returns NULL if this and Idx don't compose. 101 CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const { 102 CompMap::const_iterator I = Composed.find(Idx); 103 return I == Composed.end() ? nullptr : I->second; 104 } 105 106 // Add a composite subreg index: this+A = B. 107 // Return a conflicting composite, or NULL 108 CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A, 109 CodeGenSubRegIndex *B) { 110 assert(A && B); 111 std::pair<CompMap::iterator, bool> Ins = 112 Composed.insert(std::make_pair(A, B)); 113 // Synthetic subreg indices that aren't contiguous (for instance ARM 114 // register tuples) don't have a bit range, so it's OK to let 115 // B->Offset == -1. For the other cases, accumulate the offset and set 116 // the size here. Only do so if there is no offset yet though. 117 if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) && 118 (B->Offset == (uint16_t)-1)) { 119 B->Offset = Offset + A->Offset; 120 B->Size = A->Size; 121 } 122 return (Ins.second || Ins.first->second == B) ? nullptr 123 : Ins.first->second; 124 } 125 126 // Update the composite maps of components specified in 'ComposedOf'. 127 void updateComponents(CodeGenRegBank&); 128 129 // Return the map of composites. 130 const CompMap &getComposites() const { return Composed; } 131 132 // Compute LaneMask from Composed. Return LaneMask. 133 LaneBitmask computeLaneMask() const; 134 135 void setConcatenationOf(ArrayRef<CodeGenSubRegIndex*> Parts); 136 137 /// Replaces subregister indexes in the `ConcatenationOf` list with 138 /// list of subregisters they are composed of (if any). Do this recursively. 139 void computeConcatTransitiveClosure(); 140 141 bool operator<(const CodeGenSubRegIndex &RHS) const { 142 return this->EnumValue < RHS.EnumValue; 143 } 144 145 private: 146 CompMap Composed; 147 }; 148 149 /// CodeGenRegister - Represents a register definition. 150 struct CodeGenRegister { 151 Record *TheDef; 152 unsigned EnumValue; 153 std::vector<int64_t> CostPerUse; 154 bool CoveredBySubRegs; 155 bool HasDisjunctSubRegs; 156 bool Artificial; 157 158 // Map SubRegIndex -> Register. 159 typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, 160 deref<std::less<>>> 161 SubRegMap; 162 163 CodeGenRegister(Record *R, unsigned Enum); 164 165 StringRef getName() const; 166 167 // Extract more information from TheDef. This is used to build an object 168 // graph after all CodeGenRegister objects have been created. 169 void buildObjectGraph(CodeGenRegBank&); 170 171 // Lazily compute a map of all sub-registers. 172 // This includes unique entries for all sub-sub-registers. 173 const SubRegMap &computeSubRegs(CodeGenRegBank&); 174 175 // Compute extra sub-registers by combining the existing sub-registers. 176 void computeSecondarySubRegs(CodeGenRegBank&); 177 178 // Add this as a super-register to all sub-registers after the sub-register 179 // graph has been built. 180 void computeSuperRegs(CodeGenRegBank&); 181 182 const SubRegMap &getSubRegs() const { 183 assert(SubRegsComplete && "Must precompute sub-registers"); 184 return SubRegs; 185 } 186 187 // Add sub-registers to OSet following a pre-order defined by the .td file. 188 void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, 189 CodeGenRegBank&) const; 190 191 // Return the sub-register index naming Reg as a sub-register of this 192 // register. Returns NULL if Reg is not a sub-register. 193 CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const { 194 return SubReg2Idx.lookup(Reg); 195 } 196 197 typedef std::vector<const CodeGenRegister*> SuperRegList; 198 199 // Get the list of super-registers in topological order, small to large. 200 // This is valid after computeSubRegs visits all registers during RegBank 201 // construction. 202 const SuperRegList &getSuperRegs() const { 203 assert(SubRegsComplete && "Must precompute sub-registers"); 204 return SuperRegs; 205 } 206 207 // Get the list of ad hoc aliases. The graph is symmetric, so the list 208 // contains all registers in 'Aliases', and all registers that mention this 209 // register in 'Aliases'. 210 ArrayRef<CodeGenRegister*> getExplicitAliases() const { 211 return ExplicitAliases; 212 } 213 214 // Get the topological signature of this register. This is a small integer 215 // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have 216 // identical sub-register structure. That is, they support the same set of 217 // sub-register indices mapping to the same kind of sub-registers 218 // (TopoSig-wise). 219 unsigned getTopoSig() const { 220 assert(SuperRegsComplete && "TopoSigs haven't been computed yet."); 221 return TopoSig; 222 } 223 224 // List of register units in ascending order. 225 typedef SparseBitVector<> RegUnitList; 226 typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList; 227 228 // How many entries in RegUnitList are native? 229 RegUnitList NativeRegUnits; 230 231 // Get the list of register units. 232 // This is only valid after computeSubRegs() completes. 233 const RegUnitList &getRegUnits() const { return RegUnits; } 234 235 ArrayRef<LaneBitmask> getRegUnitLaneMasks() const { 236 return makeArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count()); 237 } 238 239 // Get the native register units. This is a prefix of getRegUnits(). 240 RegUnitList getNativeRegUnits() const { 241 return NativeRegUnits; 242 } 243 244 void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) { 245 RegUnitLaneMasks = LaneMasks; 246 } 247 248 // Inherit register units from subregisters. 249 // Return true if the RegUnits changed. 250 bool inheritRegUnits(CodeGenRegBank &RegBank); 251 252 // Adopt a register unit for pressure tracking. 253 // A unit is adopted iff its unit number is >= NativeRegUnits.count(). 254 void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); } 255 256 // Get the sum of this register's register unit weights. 257 unsigned getWeight(const CodeGenRegBank &RegBank) const; 258 259 // Canonically ordered set. 260 typedef std::vector<const CodeGenRegister*> Vec; 261 262 private: 263 bool SubRegsComplete; 264 bool SuperRegsComplete; 265 unsigned TopoSig; 266 267 // The sub-registers explicit in the .td file form a tree. 268 SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices; 269 SmallVector<CodeGenRegister*, 8> ExplicitSubRegs; 270 271 // Explicit ad hoc aliases, symmetrized to form an undirected graph. 272 SmallVector<CodeGenRegister*, 8> ExplicitAliases; 273 274 // Super-registers where this is the first explicit sub-register. 275 SuperRegList LeadingSuperRegs; 276 277 SubRegMap SubRegs; 278 SuperRegList SuperRegs; 279 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx; 280 RegUnitList RegUnits; 281 RegUnitLaneMaskList RegUnitLaneMasks; 282 }; 283 284 inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) { 285 return A.EnumValue < B.EnumValue; 286 } 287 288 inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) { 289 return A.EnumValue == B.EnumValue; 290 } 291 292 class CodeGenRegisterClass { 293 CodeGenRegister::Vec Members; 294 // Allocation orders. Order[0] always contains all registers in Members. 295 std::vector<SmallVector<Record*, 16>> Orders; 296 // Bit mask of sub-classes including this, indexed by their EnumValue. 297 BitVector SubClasses; 298 // List of super-classes, topologocally ordered to have the larger classes 299 // first. This is the same as sorting by EnumValue. 300 SmallVector<CodeGenRegisterClass*, 4> SuperClasses; 301 Record *TheDef; 302 std::string Name; 303 304 // For a synthesized class, inherit missing properties from the nearest 305 // super-class. 306 void inheritProperties(CodeGenRegBank&); 307 308 // Map SubRegIndex -> sub-class. This is the largest sub-class where all 309 // registers have a SubRegIndex sub-register. 310 DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *> 311 SubClassWithSubReg; 312 313 // Map SubRegIndex -> set of super-reg classes. This is all register 314 // classes SuperRC such that: 315 // 316 // R:SubRegIndex in this RC for all R in SuperRC. 317 // 318 DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>> 319 SuperRegClasses; 320 321 // Bit vector of TopoSigs for the registers in this class. This will be 322 // very sparse on regular architectures. 323 BitVector TopoSigs; 324 325 public: 326 unsigned EnumValue; 327 StringRef Namespace; 328 SmallVector<ValueTypeByHwMode, 4> VTs; 329 RegSizeInfoByHwMode RSI; 330 int CopyCost; 331 bool Allocatable; 332 StringRef AltOrderSelect; 333 uint8_t AllocationPriority; 334 uint8_t TSFlags; 335 /// Contains the combination of the lane masks of all subregisters. 336 LaneBitmask LaneMask; 337 /// True if there are at least 2 subregisters which do not interfere. 338 bool HasDisjunctSubRegs; 339 bool CoveredBySubRegs; 340 /// A register class is artificial if all its members are artificial. 341 bool Artificial; 342 /// Generate register pressure set for this register class and any class 343 /// synthesized from it. 344 bool GeneratePressureSet; 345 346 // Return the Record that defined this class, or NULL if the class was 347 // created by TableGen. 348 Record *getDef() const { return TheDef; } 349 350 const std::string &getName() const { return Name; } 351 std::string getQualifiedName() const; 352 ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; } 353 unsigned getNumValueTypes() const { return VTs.size(); } 354 bool hasType(const ValueTypeByHwMode &VT) const; 355 356 const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const { 357 if (VTNum < VTs.size()) 358 return VTs[VTNum]; 359 llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!"); 360 } 361 362 // Return true if this this class contains the register. 363 bool contains(const CodeGenRegister*) const; 364 365 // Returns true if RC is a subclass. 366 // RC is a sub-class of this class if it is a valid replacement for any 367 // instruction operand where a register of this classis required. It must 368 // satisfy these conditions: 369 // 370 // 1. All RC registers are also in this. 371 // 2. The RC spill size must not be smaller than our spill size. 372 // 3. RC spill alignment must be compatible with ours. 373 // 374 bool hasSubClass(const CodeGenRegisterClass *RC) const { 375 return SubClasses.test(RC->EnumValue); 376 } 377 378 // getSubClassWithSubReg - Returns the largest sub-class where all 379 // registers have a SubIdx sub-register. 380 CodeGenRegisterClass * 381 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { 382 return SubClassWithSubReg.lookup(SubIdx); 383 } 384 385 /// Find largest subclass where all registers have SubIdx subregisters in 386 /// SubRegClass and the largest subregister class that contains those 387 /// subregisters without (as far as possible) also containing additional registers. 388 /// 389 /// This can be used to find a suitable pair of classes for subregister copies. 390 /// \return std::pair<SubClass, SubRegClass> where SubClass is a SubClass is 391 /// a class where every register has SubIdx and SubRegClass is a class where 392 /// every register is covered by the SubIdx subregister of SubClass. 393 Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>> 394 getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank, 395 const CodeGenSubRegIndex *SubIdx) const; 396 397 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, 398 CodeGenRegisterClass *SubRC) { 399 SubClassWithSubReg[SubIdx] = SubRC; 400 } 401 402 // getSuperRegClasses - Returns a bit vector of all register classes 403 // containing only SubIdx super-registers of this class. 404 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, 405 BitVector &Out) const; 406 407 // addSuperRegClass - Add a class containing only SubIdx super-registers. 408 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, 409 CodeGenRegisterClass *SuperRC) { 410 SuperRegClasses[SubIdx].insert(SuperRC); 411 } 412 413 // getSubClasses - Returns a constant BitVector of subclasses indexed by 414 // EnumValue. 415 // The SubClasses vector includes an entry for this class. 416 const BitVector &getSubClasses() const { return SubClasses; } 417 418 // getSuperClasses - Returns a list of super classes ordered by EnumValue. 419 // The array does not include an entry for this class. 420 ArrayRef<CodeGenRegisterClass*> getSuperClasses() const { 421 return SuperClasses; 422 } 423 424 // Returns an ordered list of class members. 425 // The order of registers is the same as in the .td file. 426 // No = 0 is the default allocation order, No = 1 is the first alternative. 427 ArrayRef<Record*> getOrder(unsigned No = 0) const { 428 return Orders[No]; 429 } 430 431 // Return the total number of allocation orders available. 432 unsigned getNumOrders() const { return Orders.size(); } 433 434 // Get the set of registers. This set contains the same registers as 435 // getOrder(0). 436 const CodeGenRegister::Vec &getMembers() const { return Members; } 437 438 // Get a bit vector of TopoSigs present in this register class. 439 const BitVector &getTopoSigs() const { return TopoSigs; } 440 441 // Get a weight of this register class. 442 unsigned getWeight(const CodeGenRegBank&) const; 443 444 // Populate a unique sorted list of units from a register set. 445 void buildRegUnitSet(const CodeGenRegBank &RegBank, 446 std::vector<unsigned> &RegUnits) const; 447 448 CodeGenRegisterClass(CodeGenRegBank&, Record *R); 449 CodeGenRegisterClass(CodeGenRegisterClass&) = delete; 450 451 // A key representing the parts of a register class used for forming 452 // sub-classes. Note the ordering provided by this key is not the same as 453 // the topological order used for the EnumValues. 454 struct Key { 455 const CodeGenRegister::Vec *Members; 456 RegSizeInfoByHwMode RSI; 457 458 Key(const CodeGenRegister::Vec *M, const RegSizeInfoByHwMode &I) 459 : Members(M), RSI(I) {} 460 461 Key(const CodeGenRegisterClass &RC) 462 : Members(&RC.getMembers()), RSI(RC.RSI) {} 463 464 // Lexicographical order of (Members, RegSizeInfoByHwMode). 465 bool operator<(const Key&) const; 466 }; 467 468 // Create a non-user defined register class. 469 CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props); 470 471 // Called by CodeGenRegBank::CodeGenRegBank(). 472 static void computeSubClasses(CodeGenRegBank&); 473 }; 474 475 // Register categories are used when we need to deterine the category a 476 // register falls into (GPR, vector, fixed, etc.) without having to know 477 // specific information about the target architecture. 478 class CodeGenRegisterCategory { 479 Record *TheDef; 480 std::string Name; 481 std::list<CodeGenRegisterClass *> Classes; 482 483 public: 484 CodeGenRegisterCategory(CodeGenRegBank &, Record *R); 485 CodeGenRegisterCategory(CodeGenRegisterCategory &) = delete; 486 487 // Return the Record that defined this class, or NULL if the class was 488 // created by TableGen. 489 Record *getDef() const { return TheDef; } 490 491 std::string getName() const { return Name; } 492 std::list<CodeGenRegisterClass *> getClasses() const { return Classes; } 493 }; 494 495 // Register units are used to model interference and register pressure. 496 // Every register is assigned one or more register units such that two 497 // registers overlap if and only if they have a register unit in common. 498 // 499 // Normally, one register unit is created per leaf register. Non-leaf 500 // registers inherit the units of their sub-registers. 501 struct RegUnit { 502 // Weight assigned to this RegUnit for estimating register pressure. 503 // This is useful when equalizing weights in register classes with mixed 504 // register topologies. 505 unsigned Weight; 506 507 // Each native RegUnit corresponds to one or two root registers. The full 508 // set of registers containing this unit can be computed as the union of 509 // these two registers and their super-registers. 510 const CodeGenRegister *Roots[2]; 511 512 // Index into RegClassUnitSets where we can find the list of UnitSets that 513 // contain this unit. 514 unsigned RegClassUnitSetsIdx; 515 // A register unit is artificial if at least one of its roots is 516 // artificial. 517 bool Artificial; 518 519 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { 520 Roots[0] = Roots[1] = nullptr; 521 } 522 523 ArrayRef<const CodeGenRegister*> getRoots() const { 524 assert(!(Roots[1] && !Roots[0]) && "Invalid roots array"); 525 return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]); 526 } 527 }; 528 529 // Each RegUnitSet is a sorted vector with a name. 530 struct RegUnitSet { 531 typedef std::vector<unsigned>::const_iterator iterator; 532 533 std::string Name; 534 std::vector<unsigned> Units; 535 unsigned Weight = 0; // Cache the sum of all unit weights. 536 unsigned Order = 0; // Cache the sort key. 537 538 RegUnitSet() = default; 539 }; 540 541 // Base vector for identifying TopoSigs. The contents uniquely identify a 542 // TopoSig, only computeSuperRegs needs to know how. 543 typedef SmallVector<unsigned, 16> TopoSigId; 544 545 // CodeGenRegBank - Represent a target's registers and the relations between 546 // them. 547 class CodeGenRegBank { 548 SetTheory Sets; 549 550 const CodeGenHwModes &CGH; 551 552 std::deque<CodeGenSubRegIndex> SubRegIndices; 553 DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx; 554 555 CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace); 556 557 typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>, 558 CodeGenSubRegIndex*> ConcatIdxMap; 559 ConcatIdxMap ConcatIdx; 560 561 // Registers. 562 std::deque<CodeGenRegister> Registers; 563 StringMap<CodeGenRegister*> RegistersByName; 564 DenseMap<Record*, CodeGenRegister*> Def2Reg; 565 unsigned NumNativeRegUnits; 566 567 std::map<TopoSigId, unsigned> TopoSigs; 568 569 // Includes native (0..NumNativeRegUnits-1) and adopted register units. 570 SmallVector<RegUnit, 8> RegUnits; 571 572 // Register classes. 573 std::list<CodeGenRegisterClass> RegClasses; 574 DenseMap<Record*, CodeGenRegisterClass*> Def2RC; 575 typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap; 576 RCKeyMap Key2RC; 577 578 // Register categories. 579 std::list<CodeGenRegisterCategory> RegCategories; 580 DenseMap<Record *, CodeGenRegisterCategory *> Def2RCat; 581 using RCatKeyMap = 582 std::map<CodeGenRegisterClass::Key, CodeGenRegisterCategory *>; 583 RCatKeyMap Key2RCat; 584 585 // Remember each unique set of register units. Initially, this contains a 586 // unique set for each register class. Simliar sets are coalesced with 587 // pruneUnitSets and new supersets are inferred during computeRegUnitSets. 588 std::vector<RegUnitSet> RegUnitSets; 589 590 // Map RegisterClass index to the index of the RegUnitSet that contains the 591 // class's units and any inferred RegUnit supersets. 592 // 593 // NOTE: This could grow beyond the number of register classes when we map 594 // register units to lists of unit sets. If the list of unit sets does not 595 // already exist for a register class, we create a new entry in this vector. 596 std::vector<std::vector<unsigned>> RegClassUnitSets; 597 598 // Give each register unit set an order based on sorting criteria. 599 std::vector<unsigned> RegUnitSetOrder; 600 601 // Keep track of synthesized definitions generated in TupleExpander. 602 std::vector<std::unique_ptr<Record>> SynthDefs; 603 604 // Add RC to *2RC maps. 605 void addToMaps(CodeGenRegisterClass*); 606 607 // Create a synthetic sub-class if it is missing. 608 CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC, 609 const CodeGenRegister::Vec *Membs, 610 StringRef Name); 611 612 // Infer missing register classes. 613 void computeInferredRegisterClasses(); 614 void inferCommonSubClass(CodeGenRegisterClass *RC); 615 void inferSubClassWithSubReg(CodeGenRegisterClass *RC); 616 617 void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) { 618 inferMatchingSuperRegClass(RC, RegClasses.begin()); 619 } 620 621 void inferMatchingSuperRegClass( 622 CodeGenRegisterClass *RC, 623 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC); 624 625 // Iteratively prune unit sets. 626 void pruneUnitSets(); 627 628 // Compute a weight for each register unit created during getSubRegs. 629 void computeRegUnitWeights(); 630 631 // Create a RegUnitSet for each RegClass and infer superclasses. 632 void computeRegUnitSets(); 633 634 // Populate the Composite map from sub-register relationships. 635 void computeComposites(); 636 637 // Compute a lane mask for each sub-register index. 638 void computeSubRegLaneMasks(); 639 640 /// Computes a lane mask for each register unit enumerated by a physical 641 /// register. 642 void computeRegUnitLaneMasks(); 643 644 public: 645 CodeGenRegBank(RecordKeeper&, const CodeGenHwModes&); 646 CodeGenRegBank(CodeGenRegBank&) = delete; 647 648 SetTheory &getSets() { return Sets; } 649 650 const CodeGenHwModes &getHwModes() const { return CGH; } 651 652 // Sub-register indices. The first NumNamedIndices are defined by the user 653 // in the .td files. The rest are synthesized such that all sub-registers 654 // have a unique name. 655 const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const { 656 return SubRegIndices; 657 } 658 659 // Find a SubRegIndex from its Record def or add to the list if it does 660 // not exist there yet. 661 CodeGenSubRegIndex *getSubRegIdx(Record*); 662 663 // Find a SubRegIndex from its Record def. 664 const CodeGenSubRegIndex *findSubRegIdx(const Record* Def) const; 665 666 // Find or create a sub-register index representing the A+B composition. 667 CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A, 668 CodeGenSubRegIndex *B); 669 670 // Find or create a sub-register index representing the concatenation of 671 // non-overlapping sibling indices. 672 CodeGenSubRegIndex * 673 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&); 674 675 const std::deque<CodeGenRegister> &getRegisters() const { 676 return Registers; 677 } 678 679 const StringMap<CodeGenRegister *> &getRegistersByName() const { 680 return RegistersByName; 681 } 682 683 // Find a register from its Record def. 684 CodeGenRegister *getReg(Record*); 685 686 // Get a Register's index into the Registers array. 687 unsigned getRegIndex(const CodeGenRegister *Reg) const { 688 return Reg->EnumValue - 1; 689 } 690 691 // Return the number of allocated TopoSigs. The first TopoSig representing 692 // leaf registers is allocated number 0. 693 unsigned getNumTopoSigs() const { 694 return TopoSigs.size(); 695 } 696 697 // Find or create a TopoSig for the given TopoSigId. 698 // This function is only for use by CodeGenRegister::computeSuperRegs(). 699 // Others should simply use Reg->getTopoSig(). 700 unsigned getTopoSig(const TopoSigId &Id) { 701 return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second; 702 } 703 704 // Create a native register unit that is associated with one or two root 705 // registers. 706 unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) { 707 RegUnits.resize(RegUnits.size() + 1); 708 RegUnit &RU = RegUnits.back(); 709 RU.Roots[0] = R0; 710 RU.Roots[1] = R1; 711 RU.Artificial = R0->Artificial; 712 if (R1) 713 RU.Artificial |= R1->Artificial; 714 return RegUnits.size() - 1; 715 } 716 717 // Create a new non-native register unit that can be adopted by a register 718 // to increase its pressure. Note that NumNativeRegUnits is not increased. 719 unsigned newRegUnit(unsigned Weight) { 720 RegUnits.resize(RegUnits.size() + 1); 721 RegUnits.back().Weight = Weight; 722 return RegUnits.size() - 1; 723 } 724 725 // Native units are the singular unit of a leaf register. Register aliasing 726 // is completely characterized by native units. Adopted units exist to give 727 // register additional weight but don't affect aliasing. 728 bool isNativeUnit(unsigned RUID) const { 729 return RUID < NumNativeRegUnits; 730 } 731 732 unsigned getNumNativeRegUnits() const { 733 return NumNativeRegUnits; 734 } 735 736 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } 737 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } 738 739 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } 740 741 const std::list<CodeGenRegisterClass> &getRegClasses() const { 742 return RegClasses; 743 } 744 745 std::list<CodeGenRegisterCategory> &getRegCategories() { 746 return RegCategories; 747 } 748 749 const std::list<CodeGenRegisterCategory> &getRegCategories() const { 750 return RegCategories; 751 } 752 753 // Find a register class from its def. 754 CodeGenRegisterClass *getRegClass(const Record *) const; 755 756 /// getRegisterClassForRegister - Find the register class that contains the 757 /// specified physical register. If the register is not in a register 758 /// class, return null. If the register is in multiple classes, and the 759 /// classes have a superset-subset relationship and the same set of types, 760 /// return the superclass. Otherwise return null. 761 const CodeGenRegisterClass* getRegClassForRegister(Record *R); 762 763 // Analog of TargetRegisterInfo::getMinimalPhysRegClass. Unlike 764 // getRegClassForRegister, this tries to find the smallest class containing 765 // the physical register. If \p VT is specified, it will only find classes 766 // with a matching type 767 const CodeGenRegisterClass * 768 getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr); 769 770 // Get the sum of unit weights. 771 unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const { 772 unsigned Weight = 0; 773 for (unsigned Unit : Units) 774 Weight += getRegUnit(Unit).Weight; 775 return Weight; 776 } 777 778 unsigned getRegSetIDAt(unsigned Order) const { 779 return RegUnitSetOrder[Order]; 780 } 781 782 const RegUnitSet &getRegSetAt(unsigned Order) const { 783 return RegUnitSets[RegUnitSetOrder[Order]]; 784 } 785 786 // Increase a RegUnitWeight. 787 void increaseRegUnitWeight(unsigned RUID, unsigned Inc) { 788 getRegUnit(RUID).Weight += Inc; 789 } 790 791 // Get the number of register pressure dimensions. 792 unsigned getNumRegPressureSets() const { return RegUnitSets.size(); } 793 794 // Get a set of register unit IDs for a given dimension of pressure. 795 const RegUnitSet &getRegPressureSet(unsigned Idx) const { 796 return RegUnitSets[Idx]; 797 } 798 799 // The number of pressure set lists may be larget than the number of 800 // register classes if some register units appeared in a list of sets that 801 // did not correspond to an existing register class. 802 unsigned getNumRegClassPressureSetLists() const { 803 return RegClassUnitSets.size(); 804 } 805 806 // Get a list of pressure set IDs for a register class. Liveness of a 807 // register in this class impacts each pressure set in this list by the 808 // weight of the register. An exact solution requires all registers in a 809 // class to have the same class, but it is not strictly guaranteed. 810 ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const { 811 return RegClassUnitSets[RCIdx]; 812 } 813 814 // Computed derived records such as missing sub-register indices. 815 void computeDerivedInfo(); 816 817 // Compute the set of registers completely covered by the registers in Regs. 818 // The returned BitVector will have a bit set for each register in Regs, 819 // all sub-registers, and all super-registers that are covered by the 820 // registers in Regs. 821 // 822 // This is used to compute the mask of call-preserved registers from a list 823 // of callee-saves. 824 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs); 825 826 // Bit mask of lanes that cover their registers. A sub-register index whose 827 // LaneMask is contained in CoveringLanes will be completely covered by 828 // another sub-register with the same or larger lane mask. 829 LaneBitmask CoveringLanes; 830 831 // Helper function for printing debug information. Handles artificial 832 // (non-native) reg units. 833 void printRegUnitName(unsigned Unit) const; 834 }; 835 836 } // end namespace llvm 837 838 #endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H 839