1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines structures to encapsulate the machine model as described in 10 // the target description. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H 15 #define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H 16 17 #include "llvm/ADT/APInt.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/StringMap.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include "llvm/TableGen/SetTheory.h" 23 24 namespace llvm { 25 26 class CodeGenTarget; 27 class CodeGenSchedModels; 28 class CodeGenInstruction; 29 class CodeGenRegisterClass; 30 31 using RecVec = std::vector<Record*>; 32 using RecIter = std::vector<Record*>::const_iterator; 33 34 using IdxVec = std::vector<unsigned>; 35 using IdxIter = std::vector<unsigned>::const_iterator; 36 37 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred 38 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or 39 /// may not be empty. TheDef is null for inferred sequences, and Sequence must 40 /// be nonempty. 41 /// 42 /// IsVariadic controls whether the variants are expanded into multiple operands 43 /// or a sequence of writes on one operand. 44 struct CodeGenSchedRW { 45 unsigned Index; 46 std::string Name; 47 Record *TheDef; 48 bool IsRead; 49 bool IsAlias; 50 bool HasVariants; 51 bool IsVariadic; 52 bool IsSequence; 53 IdxVec Sequence; 54 RecVec Aliases; 55 56 CodeGenSchedRW() 57 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), 58 HasVariants(false), IsVariadic(false), IsSequence(false) {} 59 CodeGenSchedRW(unsigned Idx, Record *Def) 60 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { 61 Name = Def->getName(); 62 IsRead = Def->isSubClassOf("SchedRead"); 63 HasVariants = Def->isSubClassOf("SchedVariant"); 64 if (HasVariants) 65 IsVariadic = Def->getValueAsBit("Variadic"); 66 67 // Read records don't currently have sequences, but it can be easily 68 // added. Note that implicit Reads (from ReadVariant) may have a Sequence 69 // (but no record). 70 IsSequence = Def->isSubClassOf("WriteSequence"); 71 } 72 73 CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq, 74 const std::string &Name) 75 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), 76 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { 77 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs"); 78 } 79 80 bool isValid() const { 81 assert((!HasVariants || TheDef) && "Variant write needs record def"); 82 assert((!IsVariadic || HasVariants) && "Variadic write needs variants"); 83 assert((!IsSequence || !HasVariants) && "Sequence can't have variant"); 84 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty"); 85 assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases"); 86 return TheDef || !Sequence.empty(); 87 } 88 89 #ifndef NDEBUG 90 void dump() const; 91 #endif 92 }; 93 94 /// Represent a transition between SchedClasses induced by SchedVariant. 95 struct CodeGenSchedTransition { 96 unsigned ToClassIdx; 97 IdxVec ProcIndices; 98 RecVec PredTerm; 99 }; 100 101 /// Scheduling class. 102 /// 103 /// Each instruction description will be mapped to a scheduling class. There are 104 /// four types of classes: 105 /// 106 /// 1) An explicitly defined itinerary class with ItinClassDef set. 107 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor. 108 /// 109 /// 2) An implied class with a list of SchedWrites and SchedReads that are 110 /// defined in an instruction definition and which are common across all 111 /// subtargets. ProcIndices contains 0 for any processor. 112 /// 113 /// 3) An implied class with a list of InstRW records that map instructions to 114 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same 115 /// instructions to this class. ProcIndices contains all the processors that 116 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may 117 /// still be defined for processors with no InstRW entry. 118 /// 119 /// 4) An inferred class represents a variant of another class that may be 120 /// resolved at runtime. ProcIndices contains the set of processors that may 121 /// require the class. ProcIndices are propagated through SchedClasses as 122 /// variants are expanded. Multiple SchedClasses may be inferred from an 123 /// itinerary class. Each inherits the processor index from the ItinRW record 124 /// that mapped the itinerary class to the variant Writes or Reads. 125 struct CodeGenSchedClass { 126 unsigned Index; 127 std::string Name; 128 Record *ItinClassDef; 129 130 IdxVec Writes; 131 IdxVec Reads; 132 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor. 133 IdxVec ProcIndices; 134 135 std::vector<CodeGenSchedTransition> Transitions; 136 137 // InstRW records associated with this class. These records may refer to an 138 // Instruction no longer mapped to this class by InstrClassMap. These 139 // Instructions should be ignored by this class because they have been split 140 // off to join another inferred class. 141 RecVec InstRWs; 142 143 CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef) 144 : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {} 145 146 bool isKeyEqual(Record *IC, ArrayRef<unsigned> W, 147 ArrayRef<unsigned> R) const { 148 return ItinClassDef == IC && makeArrayRef(Writes) == W && 149 makeArrayRef(Reads) == R; 150 } 151 152 // Is this class generated from a variants if existing classes? Instructions 153 // are never mapped directly to inferred scheduling classes. 154 bool isInferred() const { return !ItinClassDef; } 155 156 #ifndef NDEBUG 157 void dump(const CodeGenSchedModels *SchedModels) const; 158 #endif 159 }; 160 161 /// Represent the cost of allocating a register of register class RCDef. 162 /// 163 /// The cost of allocating a register is equivalent to the number of physical 164 /// registers used by the register renamer. Register costs are defined at 165 /// register class granularity. 166 struct CodeGenRegisterCost { 167 Record *RCDef; 168 unsigned Cost; 169 bool AllowMoveElimination; 170 CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false) 171 : RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {} 172 CodeGenRegisterCost(const CodeGenRegisterCost &) = default; 173 CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete; 174 }; 175 176 /// A processor register file. 177 /// 178 /// This class describes a processor register file. Register file information is 179 /// currently consumed by external tools like llvm-mca to predict dispatch 180 /// stalls due to register pressure. 181 struct CodeGenRegisterFile { 182 std::string Name; 183 Record *RegisterFileDef; 184 unsigned MaxMovesEliminatedPerCycle; 185 bool AllowZeroMoveEliminationOnly; 186 187 unsigned NumPhysRegs; 188 std::vector<CodeGenRegisterCost> Costs; 189 190 CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0, 191 bool AllowZeroMoveElimOnly = false) 192 : Name(name), RegisterFileDef(def), 193 MaxMovesEliminatedPerCycle(MaxMoveElimPerCy), 194 AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly), 195 NumPhysRegs(0) {} 196 197 bool hasDefaultCosts() const { return Costs.empty(); } 198 }; 199 200 // Processor model. 201 // 202 // ModelName is a unique name used to name an instantiation of MCSchedModel. 203 // 204 // ModelDef is NULL for inferred Models. This happens when a processor defines 205 // an itinerary but no machine model. If the processor defines neither a machine 206 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has 207 // the special "NoModel" field set to true. 208 // 209 // ItinsDef always points to a valid record definition, but may point to the 210 // default NoItineraries. NoItineraries has an empty list of InstrItinData 211 // records. 212 // 213 // ItinDefList orders this processor's InstrItinData records by SchedClass idx. 214 struct CodeGenProcModel { 215 unsigned Index; 216 std::string ModelName; 217 Record *ModelDef; 218 Record *ItinsDef; 219 220 // Derived members... 221 222 // Array of InstrItinData records indexed by a CodeGenSchedClass index. 223 // This list is empty if the Processor has no value for Itineraries. 224 // Initialized by collectProcItins(). 225 RecVec ItinDefList; 226 227 // Map itinerary classes to per-operand resources. 228 // This list is empty if no ItinRW refers to this Processor. 229 RecVec ItinRWDefs; 230 231 // List of unsupported feature. 232 // This list is empty if the Processor has no UnsupportedFeatures. 233 RecVec UnsupportedFeaturesDefs; 234 235 // All read/write resources associated with this processor. 236 RecVec WriteResDefs; 237 RecVec ReadAdvanceDefs; 238 239 // Per-operand machine model resources associated with this processor. 240 RecVec ProcResourceDefs; 241 242 // List of Register Files. 243 std::vector<CodeGenRegisterFile> RegisterFiles; 244 245 // Optional Retire Control Unit definition. 246 Record *RetireControlUnit; 247 248 // Load/Store queue descriptors. 249 Record *LoadQueue; 250 Record *StoreQueue; 251 252 CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef, 253 Record *IDef) : 254 Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef), 255 RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {} 256 257 bool hasItineraries() const { 258 return !ItinsDef->getValueAsListOfDefs("IID").empty(); 259 } 260 261 bool hasInstrSchedModel() const { 262 return !WriteResDefs.empty() || !ItinRWDefs.empty(); 263 } 264 265 bool hasExtraProcessorInfo() const { 266 return RetireControlUnit || LoadQueue || StoreQueue || 267 !RegisterFiles.empty(); 268 } 269 270 unsigned getProcResourceIdx(Record *PRDef) const; 271 272 bool isUnsupported(const CodeGenInstruction &Inst) const; 273 274 #ifndef NDEBUG 275 void dump() const; 276 #endif 277 }; 278 279 /// Used to correlate instructions to MCInstPredicates specified by 280 /// InstructionEquivalentClass tablegen definitions. 281 /// 282 /// Example: a XOR of a register with self, is a known zero-idiom for most 283 /// X86 processors. 284 /// 285 /// Each processor can use a (potentially different) InstructionEquivalenceClass 286 /// definition to classify zero-idioms. That means, XORrr is likely to appear 287 /// in more than one equivalence class (where each class definition is 288 /// contributed by a different processor). 289 /// 290 /// There is no guarantee that the same MCInstPredicate will be used to describe 291 /// equivalence classes that identify XORrr as a zero-idiom. 292 /// 293 /// To be more specific, the requirements for being a zero-idiom XORrr may be 294 /// different for different processors. 295 /// 296 /// Class PredicateInfo identifies a subset of processors that specify the same 297 /// requirements (i.e. same MCInstPredicate and OperandMask) for an instruction 298 /// opcode. 299 /// 300 /// Back to the example. Field `ProcModelMask` will have one bit set for every 301 /// processor model that sees XORrr as a zero-idiom, and that specifies the same 302 /// set of constraints. 303 /// 304 /// By construction, there can be multiple instances of PredicateInfo associated 305 /// with a same instruction opcode. For example, different processors may define 306 /// different constraints on the same opcode. 307 /// 308 /// Field OperandMask can be used as an extra constraint. 309 /// It may be used to describe conditions that appy only to a subset of the 310 /// operands of a machine instruction, and the operands subset may not be the 311 /// same for all processor models. 312 struct PredicateInfo { 313 llvm::APInt ProcModelMask; // A set of processor model indices. 314 llvm::APInt OperandMask; // An operand mask. 315 const Record *Predicate; // MCInstrPredicate definition. 316 PredicateInfo(llvm::APInt CpuMask, llvm::APInt Operands, const Record *Pred) 317 : ProcModelMask(CpuMask), OperandMask(Operands), Predicate(Pred) {} 318 319 bool operator==(const PredicateInfo &Other) const { 320 return ProcModelMask == Other.ProcModelMask && 321 OperandMask == Other.OperandMask && Predicate == Other.Predicate; 322 } 323 }; 324 325 /// A collection of PredicateInfo objects. 326 /// 327 /// There is at least one OpcodeInfo object for every opcode specified by a 328 /// TIPredicate definition. 329 class OpcodeInfo { 330 std::vector<PredicateInfo> Predicates; 331 332 OpcodeInfo(const OpcodeInfo &Other) = delete; 333 OpcodeInfo &operator=(const OpcodeInfo &Other) = delete; 334 335 public: 336 OpcodeInfo() = default; 337 OpcodeInfo &operator=(OpcodeInfo &&Other) = default; 338 OpcodeInfo(OpcodeInfo &&Other) = default; 339 340 ArrayRef<PredicateInfo> getPredicates() const { return Predicates; } 341 342 void addPredicateForProcModel(const llvm::APInt &CpuMask, 343 const llvm::APInt &OperandMask, 344 const Record *Predicate); 345 }; 346 347 /// Used to group together tablegen instruction definitions that are subject 348 /// to a same set of constraints (identified by an instance of OpcodeInfo). 349 class OpcodeGroup { 350 OpcodeInfo Info; 351 std::vector<const Record *> Opcodes; 352 353 OpcodeGroup(const OpcodeGroup &Other) = delete; 354 OpcodeGroup &operator=(const OpcodeGroup &Other) = delete; 355 356 public: 357 OpcodeGroup(OpcodeInfo &&OpInfo) : Info(std::move(OpInfo)) {} 358 OpcodeGroup(OpcodeGroup &&Other) = default; 359 360 void addOpcode(const Record *Opcode) { 361 assert(std::find(Opcodes.begin(), Opcodes.end(), Opcode) == Opcodes.end() && 362 "Opcode already in set!"); 363 Opcodes.push_back(Opcode); 364 } 365 366 ArrayRef<const Record *> getOpcodes() const { return Opcodes; } 367 const OpcodeInfo &getOpcodeInfo() const { return Info; } 368 }; 369 370 /// An STIPredicateFunction descriptor used by tablegen backends to 371 /// auto-generate the body of a predicate function as a member of tablegen'd 372 /// class XXXGenSubtargetInfo. 373 class STIPredicateFunction { 374 const Record *FunctionDeclaration; 375 376 std::vector<const Record *> Definitions; 377 std::vector<OpcodeGroup> Groups; 378 379 STIPredicateFunction(const STIPredicateFunction &Other) = delete; 380 STIPredicateFunction &operator=(const STIPredicateFunction &Other) = delete; 381 382 public: 383 STIPredicateFunction(const Record *Rec) : FunctionDeclaration(Rec) {} 384 STIPredicateFunction(STIPredicateFunction &&Other) = default; 385 386 bool isCompatibleWith(const STIPredicateFunction &Other) const { 387 return FunctionDeclaration == Other.FunctionDeclaration; 388 } 389 390 void addDefinition(const Record *Def) { Definitions.push_back(Def); } 391 void addOpcode(const Record *OpcodeRec, OpcodeInfo &&Info) { 392 if (Groups.empty() || 393 Groups.back().getOpcodeInfo().getPredicates() != Info.getPredicates()) 394 Groups.emplace_back(std::move(Info)); 395 Groups.back().addOpcode(OpcodeRec); 396 } 397 398 StringRef getName() const { 399 return FunctionDeclaration->getValueAsString("Name"); 400 } 401 const Record *getDefaultReturnPredicate() const { 402 return FunctionDeclaration->getValueAsDef("DefaultReturnValue"); 403 } 404 405 const Record *getDeclaration() const { return FunctionDeclaration; } 406 ArrayRef<const Record *> getDefinitions() const { return Definitions; } 407 ArrayRef<OpcodeGroup> getGroups() const { return Groups; } 408 }; 409 410 /// Top level container for machine model data. 411 class CodeGenSchedModels { 412 RecordKeeper &Records; 413 const CodeGenTarget &Target; 414 415 // Map dag expressions to Instruction lists. 416 SetTheory Sets; 417 418 // List of unique processor models. 419 std::vector<CodeGenProcModel> ProcModels; 420 421 // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index. 422 using ProcModelMapTy = DenseMap<Record*, unsigned>; 423 ProcModelMapTy ProcModelMap; 424 425 // Per-operand SchedReadWrite types. 426 std::vector<CodeGenSchedRW> SchedWrites; 427 std::vector<CodeGenSchedRW> SchedReads; 428 429 // List of unique SchedClasses. 430 std::vector<CodeGenSchedClass> SchedClasses; 431 432 // Any inferred SchedClass has an index greater than NumInstrSchedClassses. 433 unsigned NumInstrSchedClasses; 434 435 RecVec ProcResourceDefs; 436 RecVec ProcResGroups; 437 438 // Map each instruction to its unique SchedClass index considering the 439 // combination of it's itinerary class, SchedRW list, and InstRW records. 440 using InstClassMapTy = DenseMap<Record*, unsigned>; 441 InstClassMapTy InstrClassMap; 442 443 std::vector<STIPredicateFunction> STIPredicates; 444 445 public: 446 CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT); 447 448 // iterator access to the scheduling classes. 449 using class_iterator = std::vector<CodeGenSchedClass>::iterator; 450 using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator; 451 class_iterator classes_begin() { return SchedClasses.begin(); } 452 const_class_iterator classes_begin() const { return SchedClasses.begin(); } 453 class_iterator classes_end() { return SchedClasses.end(); } 454 const_class_iterator classes_end() const { return SchedClasses.end(); } 455 iterator_range<class_iterator> classes() { 456 return make_range(classes_begin(), classes_end()); 457 } 458 iterator_range<const_class_iterator> classes() const { 459 return make_range(classes_begin(), classes_end()); 460 } 461 iterator_range<class_iterator> explicit_classes() { 462 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses); 463 } 464 iterator_range<const_class_iterator> explicit_classes() const { 465 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses); 466 } 467 468 Record *getModelOrItinDef(Record *ProcDef) const { 469 Record *ModelDef = ProcDef->getValueAsDef("SchedModel"); 470 Record *ItinsDef = ProcDef->getValueAsDef("ProcItin"); 471 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) { 472 assert(ModelDef->getValueAsBit("NoModel") 473 && "Itineraries must be defined within SchedMachineModel"); 474 return ItinsDef; 475 } 476 return ModelDef; 477 } 478 479 const CodeGenProcModel &getModelForProc(Record *ProcDef) const { 480 Record *ModelDef = getModelOrItinDef(ProcDef); 481 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef); 482 assert(I != ProcModelMap.end() && "missing machine model"); 483 return ProcModels[I->second]; 484 } 485 486 CodeGenProcModel &getProcModel(Record *ModelDef) { 487 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef); 488 assert(I != ProcModelMap.end() && "missing machine model"); 489 return ProcModels[I->second]; 490 } 491 const CodeGenProcModel &getProcModel(Record *ModelDef) const { 492 return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef); 493 } 494 495 // Iterate over the unique processor models. 496 using ProcIter = std::vector<CodeGenProcModel>::const_iterator; 497 ProcIter procModelBegin() const { return ProcModels.begin(); } 498 ProcIter procModelEnd() const { return ProcModels.end(); } 499 ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; } 500 501 // Return true if any processors have itineraries. 502 bool hasItineraries() const; 503 504 // Get a SchedWrite from its index. 505 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const { 506 assert(Idx < SchedWrites.size() && "bad SchedWrite index"); 507 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite"); 508 return SchedWrites[Idx]; 509 } 510 // Get a SchedWrite from its index. 511 const CodeGenSchedRW &getSchedRead(unsigned Idx) const { 512 assert(Idx < SchedReads.size() && "bad SchedRead index"); 513 assert(SchedReads[Idx].isValid() && "invalid SchedRead"); 514 return SchedReads[Idx]; 515 } 516 517 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const { 518 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx); 519 } 520 CodeGenSchedRW &getSchedRW(Record *Def) { 521 bool IsRead = Def->isSubClassOf("SchedRead"); 522 unsigned Idx = getSchedRWIdx(Def, IsRead); 523 return const_cast<CodeGenSchedRW&>( 524 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx)); 525 } 526 const CodeGenSchedRW &getSchedRW(Record *Def) const { 527 return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def); 528 } 529 530 unsigned getSchedRWIdx(const Record *Def, bool IsRead) const; 531 532 // Return true if the given write record is referenced by a ReadAdvance. 533 bool hasReadOfWrite(Record *WriteDef) const; 534 535 // Get a SchedClass from its index. 536 CodeGenSchedClass &getSchedClass(unsigned Idx) { 537 assert(Idx < SchedClasses.size() && "bad SchedClass index"); 538 return SchedClasses[Idx]; 539 } 540 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { 541 assert(Idx < SchedClasses.size() && "bad SchedClass index"); 542 return SchedClasses[Idx]; 543 } 544 545 // Get the SchedClass index for an instruction. Instructions with no 546 // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0 547 // for NoItinerary. 548 unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const; 549 550 using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator; 551 SchedClassIter schedClassBegin() const { return SchedClasses.begin(); } 552 SchedClassIter schedClassEnd() const { return SchedClasses.end(); } 553 ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; } 554 555 unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; } 556 557 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const; 558 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const; 559 void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const; 560 void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead, 561 const CodeGenProcModel &ProcModel) const; 562 563 unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites, 564 ArrayRef<unsigned> OperReads, 565 ArrayRef<unsigned> ProcIndices); 566 567 unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead); 568 569 Record *findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM, 570 ArrayRef<SMLoc> Loc) const; 571 572 ArrayRef<STIPredicateFunction> getSTIPredicates() const { 573 return STIPredicates; 574 } 575 private: 576 void collectProcModels(); 577 578 // Initialize a new processor model if it is unique. 579 void addProcModel(Record *ProcDef); 580 581 void collectSchedRW(); 582 583 std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead); 584 unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead); 585 586 void collectSchedClasses(); 587 588 void collectRetireControlUnits(); 589 590 void collectRegisterFiles(); 591 592 void collectOptionalProcessorInfo(); 593 594 std::string createSchedClassName(Record *ItinClassDef, 595 ArrayRef<unsigned> OperWrites, 596 ArrayRef<unsigned> OperReads); 597 std::string createSchedClassName(const RecVec &InstDefs); 598 void createInstRWClass(Record *InstRWDef); 599 600 void collectProcItins(); 601 602 void collectProcItinRW(); 603 604 void collectProcUnsupportedFeatures(); 605 606 void inferSchedClasses(); 607 608 void checkMCInstPredicates() const; 609 610 void checkSTIPredicates() const; 611 612 void collectSTIPredicates(); 613 614 void collectLoadStoreQueueInfo(); 615 616 void checkCompleteness(); 617 618 void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads, 619 unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices); 620 void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx); 621 void inferFromInstRWs(unsigned SCIdx); 622 623 bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM); 624 void verifyProcResourceGroups(CodeGenProcModel &PM); 625 626 void collectProcResources(); 627 628 void collectItinProcResources(Record *ItinClassDef); 629 630 void collectRWResources(unsigned RWIdx, bool IsRead, 631 ArrayRef<unsigned> ProcIndices); 632 633 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads, 634 ArrayRef<unsigned> ProcIndices); 635 636 void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM, 637 ArrayRef<SMLoc> Loc); 638 639 void addWriteRes(Record *ProcWriteResDef, unsigned PIdx); 640 641 void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx); 642 }; 643 644 } // namespace llvm 645 646 #endif 647