1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines structures to encapsulate the machine model as described in 10 // the target description. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H 15 #define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H 16 17 #include "llvm/ADT/APInt.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/TableGen/Record.h" 21 #include "llvm/TableGen/SetTheory.h" 22 23 namespace llvm { 24 25 class CodeGenTarget; 26 class CodeGenSchedModels; 27 class CodeGenInstruction; 28 29 using RecVec = std::vector<Record*>; 30 using RecIter = std::vector<Record*>::const_iterator; 31 32 using IdxVec = std::vector<unsigned>; 33 using IdxIter = std::vector<unsigned>::const_iterator; 34 35 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred 36 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or 37 /// may not be empty. TheDef is null for inferred sequences, and Sequence must 38 /// be nonempty. 39 /// 40 /// IsVariadic controls whether the variants are expanded into multiple operands 41 /// or a sequence of writes on one operand. 42 struct CodeGenSchedRW { 43 unsigned Index; 44 std::string Name; 45 Record *TheDef; 46 bool IsRead; 47 bool IsAlias; 48 bool HasVariants; 49 bool IsVariadic; 50 bool IsSequence; 51 IdxVec Sequence; 52 RecVec Aliases; 53 54 CodeGenSchedRW() 55 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), 56 HasVariants(false), IsVariadic(false), IsSequence(false) {} 57 CodeGenSchedRW(unsigned Idx, Record *Def) 58 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { 59 Name = std::string(Def->getName()); 60 IsRead = Def->isSubClassOf("SchedRead"); 61 HasVariants = Def->isSubClassOf("SchedVariant"); 62 if (HasVariants) 63 IsVariadic = Def->getValueAsBit("Variadic"); 64 65 // Read records don't currently have sequences, but it can be easily 66 // added. Note that implicit Reads (from ReadVariant) may have a Sequence 67 // (but no record). 68 IsSequence = Def->isSubClassOf("WriteSequence"); 69 } 70 71 CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq, 72 const std::string &Name) 73 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), 74 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { 75 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs"); 76 } 77 78 bool isValid() const { 79 assert((!HasVariants || TheDef) && "Variant write needs record def"); 80 assert((!IsVariadic || HasVariants) && "Variadic write needs variants"); 81 assert((!IsSequence || !HasVariants) && "Sequence can't have variant"); 82 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty"); 83 assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases"); 84 return TheDef || !Sequence.empty(); 85 } 86 87 #ifndef NDEBUG 88 void dump() const; 89 #endif 90 }; 91 92 /// Represent a transition between SchedClasses induced by SchedVariant. 93 struct CodeGenSchedTransition { 94 unsigned ToClassIdx; 95 unsigned ProcIndex; 96 RecVec PredTerm; 97 }; 98 99 /// Scheduling class. 100 /// 101 /// Each instruction description will be mapped to a scheduling class. There are 102 /// four types of classes: 103 /// 104 /// 1) An explicitly defined itinerary class with ItinClassDef set. 105 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor. 106 /// 107 /// 2) An implied class with a list of SchedWrites and SchedReads that are 108 /// defined in an instruction definition and which are common across all 109 /// subtargets. ProcIndices contains 0 for any processor. 110 /// 111 /// 3) An implied class with a list of InstRW records that map instructions to 112 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same 113 /// instructions to this class. ProcIndices contains all the processors that 114 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may 115 /// still be defined for processors with no InstRW entry. 116 /// 117 /// 4) An inferred class represents a variant of another class that may be 118 /// resolved at runtime. ProcIndices contains the set of processors that may 119 /// require the class. ProcIndices are propagated through SchedClasses as 120 /// variants are expanded. Multiple SchedClasses may be inferred from an 121 /// itinerary class. Each inherits the processor index from the ItinRW record 122 /// that mapped the itinerary class to the variant Writes or Reads. 123 struct CodeGenSchedClass { 124 unsigned Index; 125 std::string Name; 126 Record *ItinClassDef; 127 128 IdxVec Writes; 129 IdxVec Reads; 130 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor. 131 IdxVec ProcIndices; 132 133 std::vector<CodeGenSchedTransition> Transitions; 134 135 // InstRW records associated with this class. These records may refer to an 136 // Instruction no longer mapped to this class by InstrClassMap. These 137 // Instructions should be ignored by this class because they have been split 138 // off to join another inferred class. 139 RecVec InstRWs; 140 // InstRWs processor indices. Filled in inferFromInstRWs 141 DenseSet<unsigned> InstRWProcIndices; 142 143 CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef) 144 : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {} 145 146 bool isKeyEqual(Record *IC, ArrayRef<unsigned> W, 147 ArrayRef<unsigned> R) const { 148 return ItinClassDef == IC && makeArrayRef(Writes) == W && 149 makeArrayRef(Reads) == R; 150 } 151 152 // Is this class generated from a variants if existing classes? Instructions 153 // are never mapped directly to inferred scheduling classes. 154 bool isInferred() const { return !ItinClassDef; } 155 156 #ifndef NDEBUG 157 void dump(const CodeGenSchedModels *SchedModels) const; 158 #endif 159 }; 160 161 /// Represent the cost of allocating a register of register class RCDef. 162 /// 163 /// The cost of allocating a register is equivalent to the number of physical 164 /// registers used by the register renamer. Register costs are defined at 165 /// register class granularity. 166 struct CodeGenRegisterCost { 167 Record *RCDef; 168 unsigned Cost; 169 bool AllowMoveElimination; 170 CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false) 171 : RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {} 172 CodeGenRegisterCost(const CodeGenRegisterCost &) = default; 173 CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete; 174 }; 175 176 /// A processor register file. 177 /// 178 /// This class describes a processor register file. Register file information is 179 /// currently consumed by external tools like llvm-mca to predict dispatch 180 /// stalls due to register pressure. 181 struct CodeGenRegisterFile { 182 std::string Name; 183 Record *RegisterFileDef; 184 unsigned MaxMovesEliminatedPerCycle; 185 bool AllowZeroMoveEliminationOnly; 186 187 unsigned NumPhysRegs; 188 std::vector<CodeGenRegisterCost> Costs; 189 190 CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0, 191 bool AllowZeroMoveElimOnly = false) 192 : Name(name), RegisterFileDef(def), 193 MaxMovesEliminatedPerCycle(MaxMoveElimPerCy), 194 AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly), 195 NumPhysRegs(0) {} 196 197 bool hasDefaultCosts() const { return Costs.empty(); } 198 }; 199 200 // Processor model. 201 // 202 // ModelName is a unique name used to name an instantiation of MCSchedModel. 203 // 204 // ModelDef is NULL for inferred Models. This happens when a processor defines 205 // an itinerary but no machine model. If the processor defines neither a machine 206 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has 207 // the special "NoModel" field set to true. 208 // 209 // ItinsDef always points to a valid record definition, but may point to the 210 // default NoItineraries. NoItineraries has an empty list of InstrItinData 211 // records. 212 // 213 // ItinDefList orders this processor's InstrItinData records by SchedClass idx. 214 struct CodeGenProcModel { 215 unsigned Index; 216 std::string ModelName; 217 Record *ModelDef; 218 Record *ItinsDef; 219 220 // Derived members... 221 222 // Array of InstrItinData records indexed by a CodeGenSchedClass index. 223 // This list is empty if the Processor has no value for Itineraries. 224 // Initialized by collectProcItins(). 225 RecVec ItinDefList; 226 227 // Map itinerary classes to per-operand resources. 228 // This list is empty if no ItinRW refers to this Processor. 229 RecVec ItinRWDefs; 230 231 // List of unsupported feature. 232 // This list is empty if the Processor has no UnsupportedFeatures. 233 RecVec UnsupportedFeaturesDefs; 234 235 // All read/write resources associated with this processor. 236 RecVec WriteResDefs; 237 RecVec ReadAdvanceDefs; 238 239 // Per-operand machine model resources associated with this processor. 240 RecVec ProcResourceDefs; 241 242 // List of Register Files. 243 std::vector<CodeGenRegisterFile> RegisterFiles; 244 245 // Optional Retire Control Unit definition. 246 Record *RetireControlUnit; 247 248 // Load/Store queue descriptors. 249 Record *LoadQueue; 250 Record *StoreQueue; 251 252 CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef, 253 Record *IDef) : 254 Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef), 255 RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {} 256 257 bool hasItineraries() const { 258 return !ItinsDef->getValueAsListOfDefs("IID").empty(); 259 } 260 261 bool hasInstrSchedModel() const { 262 return !WriteResDefs.empty() || !ItinRWDefs.empty(); 263 } 264 265 bool hasExtraProcessorInfo() const { 266 return RetireControlUnit || LoadQueue || StoreQueue || 267 !RegisterFiles.empty(); 268 } 269 270 unsigned getProcResourceIdx(Record *PRDef) const; 271 272 bool isUnsupported(const CodeGenInstruction &Inst) const; 273 274 #ifndef NDEBUG 275 void dump() const; 276 #endif 277 }; 278 279 /// Used to correlate instructions to MCInstPredicates specified by 280 /// InstructionEquivalentClass tablegen definitions. 281 /// 282 /// Example: a XOR of a register with self, is a known zero-idiom for most 283 /// X86 processors. 284 /// 285 /// Each processor can use a (potentially different) InstructionEquivalenceClass 286 /// definition to classify zero-idioms. That means, XORrr is likely to appear 287 /// in more than one equivalence class (where each class definition is 288 /// contributed by a different processor). 289 /// 290 /// There is no guarantee that the same MCInstPredicate will be used to describe 291 /// equivalence classes that identify XORrr as a zero-idiom. 292 /// 293 /// To be more specific, the requirements for being a zero-idiom XORrr may be 294 /// different for different processors. 295 /// 296 /// Class PredicateInfo identifies a subset of processors that specify the same 297 /// requirements (i.e. same MCInstPredicate and OperandMask) for an instruction 298 /// opcode. 299 /// 300 /// Back to the example. Field `ProcModelMask` will have one bit set for every 301 /// processor model that sees XORrr as a zero-idiom, and that specifies the same 302 /// set of constraints. 303 /// 304 /// By construction, there can be multiple instances of PredicateInfo associated 305 /// with a same instruction opcode. For example, different processors may define 306 /// different constraints on the same opcode. 307 /// 308 /// Field OperandMask can be used as an extra constraint. 309 /// It may be used to describe conditions that appy only to a subset of the 310 /// operands of a machine instruction, and the operands subset may not be the 311 /// same for all processor models. 312 struct PredicateInfo { 313 llvm::APInt ProcModelMask; // A set of processor model indices. 314 llvm::APInt OperandMask; // An operand mask. 315 const Record *Predicate; // MCInstrPredicate definition. 316 PredicateInfo(llvm::APInt CpuMask, llvm::APInt Operands, const Record *Pred) 317 : ProcModelMask(CpuMask), OperandMask(Operands), Predicate(Pred) {} 318 319 bool operator==(const PredicateInfo &Other) const { 320 return ProcModelMask == Other.ProcModelMask && 321 OperandMask == Other.OperandMask && Predicate == Other.Predicate; 322 } 323 }; 324 325 /// A collection of PredicateInfo objects. 326 /// 327 /// There is at least one OpcodeInfo object for every opcode specified by a 328 /// TIPredicate definition. 329 class OpcodeInfo { 330 std::vector<PredicateInfo> Predicates; 331 332 OpcodeInfo(const OpcodeInfo &Other) = delete; 333 OpcodeInfo &operator=(const OpcodeInfo &Other) = delete; 334 335 public: 336 OpcodeInfo() = default; 337 OpcodeInfo &operator=(OpcodeInfo &&Other) = default; 338 OpcodeInfo(OpcodeInfo &&Other) = default; 339 340 ArrayRef<PredicateInfo> getPredicates() const { return Predicates; } 341 342 void addPredicateForProcModel(const llvm::APInt &CpuMask, 343 const llvm::APInt &OperandMask, 344 const Record *Predicate); 345 }; 346 347 /// Used to group together tablegen instruction definitions that are subject 348 /// to a same set of constraints (identified by an instance of OpcodeInfo). 349 class OpcodeGroup { 350 OpcodeInfo Info; 351 std::vector<const Record *> Opcodes; 352 353 OpcodeGroup(const OpcodeGroup &Other) = delete; 354 OpcodeGroup &operator=(const OpcodeGroup &Other) = delete; 355 356 public: 357 OpcodeGroup(OpcodeInfo &&OpInfo) : Info(std::move(OpInfo)) {} 358 OpcodeGroup(OpcodeGroup &&Other) = default; 359 360 void addOpcode(const Record *Opcode) { 361 assert(!llvm::is_contained(Opcodes, Opcode) && "Opcode already in set!"); 362 Opcodes.push_back(Opcode); 363 } 364 365 ArrayRef<const Record *> getOpcodes() const { return Opcodes; } 366 const OpcodeInfo &getOpcodeInfo() const { return Info; } 367 }; 368 369 /// An STIPredicateFunction descriptor used by tablegen backends to 370 /// auto-generate the body of a predicate function as a member of tablegen'd 371 /// class XXXGenSubtargetInfo. 372 class STIPredicateFunction { 373 const Record *FunctionDeclaration; 374 375 std::vector<const Record *> Definitions; 376 std::vector<OpcodeGroup> Groups; 377 378 STIPredicateFunction(const STIPredicateFunction &Other) = delete; 379 STIPredicateFunction &operator=(const STIPredicateFunction &Other) = delete; 380 381 public: 382 STIPredicateFunction(const Record *Rec) : FunctionDeclaration(Rec) {} 383 STIPredicateFunction(STIPredicateFunction &&Other) = default; 384 385 bool isCompatibleWith(const STIPredicateFunction &Other) const { 386 return FunctionDeclaration == Other.FunctionDeclaration; 387 } 388 389 void addDefinition(const Record *Def) { Definitions.push_back(Def); } 390 void addOpcode(const Record *OpcodeRec, OpcodeInfo &&Info) { 391 if (Groups.empty() || 392 Groups.back().getOpcodeInfo().getPredicates() != Info.getPredicates()) 393 Groups.emplace_back(std::move(Info)); 394 Groups.back().addOpcode(OpcodeRec); 395 } 396 397 StringRef getName() const { 398 return FunctionDeclaration->getValueAsString("Name"); 399 } 400 const Record *getDefaultReturnPredicate() const { 401 return FunctionDeclaration->getValueAsDef("DefaultReturnValue"); 402 } 403 404 const Record *getDeclaration() const { return FunctionDeclaration; } 405 ArrayRef<const Record *> getDefinitions() const { return Definitions; } 406 ArrayRef<OpcodeGroup> getGroups() const { return Groups; } 407 }; 408 409 using ProcModelMapTy = DenseMap<const Record *, unsigned>; 410 411 /// Top level container for machine model data. 412 class CodeGenSchedModels { 413 RecordKeeper &Records; 414 const CodeGenTarget &Target; 415 416 // Map dag expressions to Instruction lists. 417 SetTheory Sets; 418 419 // List of unique processor models. 420 std::vector<CodeGenProcModel> ProcModels; 421 422 // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index. 423 ProcModelMapTy ProcModelMap; 424 425 // Per-operand SchedReadWrite types. 426 std::vector<CodeGenSchedRW> SchedWrites; 427 std::vector<CodeGenSchedRW> SchedReads; 428 429 // List of unique SchedClasses. 430 std::vector<CodeGenSchedClass> SchedClasses; 431 432 // Any inferred SchedClass has an index greater than NumInstrSchedClassses. 433 unsigned NumInstrSchedClasses; 434 435 RecVec ProcResourceDefs; 436 RecVec ProcResGroups; 437 438 // Map each instruction to its unique SchedClass index considering the 439 // combination of it's itinerary class, SchedRW list, and InstRW records. 440 using InstClassMapTy = DenseMap<Record*, unsigned>; 441 InstClassMapTy InstrClassMap; 442 443 std::vector<STIPredicateFunction> STIPredicates; 444 std::vector<unsigned> getAllProcIndices() const; 445 446 public: 447 CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT); 448 449 // iterator access to the scheduling classes. 450 using class_iterator = std::vector<CodeGenSchedClass>::iterator; 451 using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator; 452 class_iterator classes_begin() { return SchedClasses.begin(); } 453 const_class_iterator classes_begin() const { return SchedClasses.begin(); } 454 class_iterator classes_end() { return SchedClasses.end(); } 455 const_class_iterator classes_end() const { return SchedClasses.end(); } 456 iterator_range<class_iterator> classes() { 457 return make_range(classes_begin(), classes_end()); 458 } 459 iterator_range<const_class_iterator> classes() const { 460 return make_range(classes_begin(), classes_end()); 461 } 462 iterator_range<class_iterator> explicit_classes() { 463 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses); 464 } 465 iterator_range<const_class_iterator> explicit_classes() const { 466 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses); 467 } 468 469 Record *getModelOrItinDef(Record *ProcDef) const { 470 Record *ModelDef = ProcDef->getValueAsDef("SchedModel"); 471 Record *ItinsDef = ProcDef->getValueAsDef("ProcItin"); 472 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) { 473 assert(ModelDef->getValueAsBit("NoModel") 474 && "Itineraries must be defined within SchedMachineModel"); 475 return ItinsDef; 476 } 477 return ModelDef; 478 } 479 480 const CodeGenProcModel &getModelForProc(Record *ProcDef) const { 481 Record *ModelDef = getModelOrItinDef(ProcDef); 482 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef); 483 assert(I != ProcModelMap.end() && "missing machine model"); 484 return ProcModels[I->second]; 485 } 486 487 CodeGenProcModel &getProcModel(Record *ModelDef) { 488 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef); 489 assert(I != ProcModelMap.end() && "missing machine model"); 490 return ProcModels[I->second]; 491 } 492 const CodeGenProcModel &getProcModel(Record *ModelDef) const { 493 return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef); 494 } 495 496 // Iterate over the unique processor models. 497 using ProcIter = std::vector<CodeGenProcModel>::const_iterator; 498 ProcIter procModelBegin() const { return ProcModels.begin(); } 499 ProcIter procModelEnd() const { return ProcModels.end(); } 500 ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; } 501 502 // Return true if any processors have itineraries. 503 bool hasItineraries() const; 504 505 // Get a SchedWrite from its index. 506 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const { 507 assert(Idx < SchedWrites.size() && "bad SchedWrite index"); 508 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite"); 509 return SchedWrites[Idx]; 510 } 511 // Get a SchedWrite from its index. 512 const CodeGenSchedRW &getSchedRead(unsigned Idx) const { 513 assert(Idx < SchedReads.size() && "bad SchedRead index"); 514 assert(SchedReads[Idx].isValid() && "invalid SchedRead"); 515 return SchedReads[Idx]; 516 } 517 518 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const { 519 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx); 520 } 521 CodeGenSchedRW &getSchedRW(Record *Def) { 522 bool IsRead = Def->isSubClassOf("SchedRead"); 523 unsigned Idx = getSchedRWIdx(Def, IsRead); 524 return const_cast<CodeGenSchedRW&>( 525 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx)); 526 } 527 const CodeGenSchedRW &getSchedRW(Record *Def) const { 528 return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def); 529 } 530 531 unsigned getSchedRWIdx(const Record *Def, bool IsRead) const; 532 533 // Return true if the given write record is referenced by a ReadAdvance. 534 bool hasReadOfWrite(Record *WriteDef) const; 535 536 // Get a SchedClass from its index. 537 CodeGenSchedClass &getSchedClass(unsigned Idx) { 538 assert(Idx < SchedClasses.size() && "bad SchedClass index"); 539 return SchedClasses[Idx]; 540 } 541 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { 542 assert(Idx < SchedClasses.size() && "bad SchedClass index"); 543 return SchedClasses[Idx]; 544 } 545 546 // Get the SchedClass index for an instruction. Instructions with no 547 // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0 548 // for NoItinerary. 549 unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const; 550 551 using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator; 552 SchedClassIter schedClassBegin() const { return SchedClasses.begin(); } 553 SchedClassIter schedClassEnd() const { return SchedClasses.end(); } 554 ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; } 555 556 unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; } 557 558 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const; 559 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const; 560 void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const; 561 void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead, 562 const CodeGenProcModel &ProcModel) const; 563 564 unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites, 565 ArrayRef<unsigned> OperReads, 566 ArrayRef<unsigned> ProcIndices); 567 568 unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead); 569 570 Record *findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM, 571 ArrayRef<SMLoc> Loc) const; 572 573 ArrayRef<STIPredicateFunction> getSTIPredicates() const { 574 return STIPredicates; 575 } 576 private: 577 void collectProcModels(); 578 579 // Initialize a new processor model if it is unique. 580 void addProcModel(Record *ProcDef); 581 582 void collectSchedRW(); 583 584 std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead); 585 unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead); 586 587 void collectSchedClasses(); 588 589 void collectRetireControlUnits(); 590 591 void collectRegisterFiles(); 592 593 void collectOptionalProcessorInfo(); 594 595 std::string createSchedClassName(Record *ItinClassDef, 596 ArrayRef<unsigned> OperWrites, 597 ArrayRef<unsigned> OperReads); 598 std::string createSchedClassName(const RecVec &InstDefs); 599 void createInstRWClass(Record *InstRWDef); 600 601 void collectProcItins(); 602 603 void collectProcItinRW(); 604 605 void collectProcUnsupportedFeatures(); 606 607 void inferSchedClasses(); 608 609 void checkMCInstPredicates() const; 610 611 void checkSTIPredicates() const; 612 613 void collectSTIPredicates(); 614 615 void collectLoadStoreQueueInfo(); 616 617 void checkCompleteness(); 618 619 void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads, 620 unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices); 621 void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx); 622 void inferFromInstRWs(unsigned SCIdx); 623 624 bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM); 625 void verifyProcResourceGroups(CodeGenProcModel &PM); 626 627 void collectProcResources(); 628 629 void collectItinProcResources(Record *ItinClassDef); 630 631 void collectRWResources(unsigned RWIdx, bool IsRead, 632 ArrayRef<unsigned> ProcIndices); 633 634 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads, 635 ArrayRef<unsigned> ProcIndices); 636 637 void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM, 638 ArrayRef<SMLoc> Loc); 639 640 void addWriteRes(Record *ProcWriteResDef, unsigned PIdx); 641 642 void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx); 643 }; 644 645 } // namespace llvm 646 647 #endif 648