1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class wraps target description classes used by the various code 10 // generation TableGen backends. This makes it easier to access the data and 11 // provides a single place that needs to check it for validity. All of these 12 // classes abort on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "CodeGenTarget.h" 17 #include "CodeGenInstruction.h" 18 #include "CodeGenIntrinsics.h" 19 #include "CodeGenSchedule.h" 20 #include "llvm/ADT/STLExtras.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/TableGen/Error.h" 23 #include "llvm/TableGen/Record.h" 24 #include <algorithm> 25 using namespace llvm; 26 27 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser"); 28 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer"); 29 30 static cl::opt<unsigned> 31 AsmParserNum("asmparsernum", cl::init(0), 32 cl::desc("Make -gen-asm-parser emit assembly parser #N"), 33 cl::cat(AsmParserCat)); 34 35 static cl::opt<unsigned> 36 AsmWriterNum("asmwriternum", cl::init(0), 37 cl::desc("Make -gen-asm-writer emit assembly writer #N"), 38 cl::cat(AsmWriterCat)); 39 40 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 41 /// record corresponds to. 42 MVT::SimpleValueType llvm::getValueType(Record *Rec) { 43 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); 44 } 45 46 StringRef llvm::getName(MVT::SimpleValueType T) { 47 switch (T) { 48 case MVT::Other: return "UNKNOWN"; 49 case MVT::iPTR: return "TLI.getPointerTy()"; 50 case MVT::iPTRAny: return "TLI.getPointerTy()"; 51 default: return getEnumName(T); 52 } 53 } 54 55 StringRef llvm::getEnumName(MVT::SimpleValueType T) { 56 // clang-format off 57 switch (T) { 58 case MVT::Other: return "MVT::Other"; 59 case MVT::i1: return "MVT::i1"; 60 case MVT::i2: return "MVT::i2"; 61 case MVT::i4: return "MVT::i4"; 62 case MVT::i8: return "MVT::i8"; 63 case MVT::i16: return "MVT::i16"; 64 case MVT::i32: return "MVT::i32"; 65 case MVT::i64: return "MVT::i64"; 66 case MVT::i128: return "MVT::i128"; 67 case MVT::Any: return "MVT::Any"; 68 case MVT::iAny: return "MVT::iAny"; 69 case MVT::fAny: return "MVT::fAny"; 70 case MVT::vAny: return "MVT::vAny"; 71 case MVT::f16: return "MVT::f16"; 72 case MVT::bf16: return "MVT::bf16"; 73 case MVT::f32: return "MVT::f32"; 74 case MVT::f64: return "MVT::f64"; 75 case MVT::f80: return "MVT::f80"; 76 case MVT::f128: return "MVT::f128"; 77 case MVT::ppcf128: return "MVT::ppcf128"; 78 case MVT::x86mmx: return "MVT::x86mmx"; 79 case MVT::x86amx: return "MVT::x86amx"; 80 case MVT::i64x8: return "MVT::i64x8"; 81 case MVT::Glue: return "MVT::Glue"; 82 case MVT::isVoid: return "MVT::isVoid"; 83 case MVT::v1i1: return "MVT::v1i1"; 84 case MVT::v2i1: return "MVT::v2i1"; 85 case MVT::v4i1: return "MVT::v4i1"; 86 case MVT::v8i1: return "MVT::v8i1"; 87 case MVT::v16i1: return "MVT::v16i1"; 88 case MVT::v32i1: return "MVT::v32i1"; 89 case MVT::v64i1: return "MVT::v64i1"; 90 case MVT::v128i1: return "MVT::v128i1"; 91 case MVT::v256i1: return "MVT::v256i1"; 92 case MVT::v512i1: return "MVT::v512i1"; 93 case MVT::v1024i1: return "MVT::v1024i1"; 94 case MVT::v128i2: return "MVT::v128i2"; 95 case MVT::v64i4: return "MVT::v64i4"; 96 case MVT::v1i8: return "MVT::v1i8"; 97 case MVT::v2i8: return "MVT::v2i8"; 98 case MVT::v4i8: return "MVT::v4i8"; 99 case MVT::v8i8: return "MVT::v8i8"; 100 case MVT::v16i8: return "MVT::v16i8"; 101 case MVT::v32i8: return "MVT::v32i8"; 102 case MVT::v64i8: return "MVT::v64i8"; 103 case MVT::v128i8: return "MVT::v128i8"; 104 case MVT::v256i8: return "MVT::v256i8"; 105 case MVT::v512i8: return "MVT::v512i8"; 106 case MVT::v1024i8: return "MVT::v1024i8"; 107 case MVT::v1i16: return "MVT::v1i16"; 108 case MVT::v2i16: return "MVT::v2i16"; 109 case MVT::v3i16: return "MVT::v3i16"; 110 case MVT::v4i16: return "MVT::v4i16"; 111 case MVT::v8i16: return "MVT::v8i16"; 112 case MVT::v16i16: return "MVT::v16i16"; 113 case MVT::v32i16: return "MVT::v32i16"; 114 case MVT::v64i16: return "MVT::v64i16"; 115 case MVT::v128i16: return "MVT::v128i16"; 116 case MVT::v256i16: return "MVT::v256i16"; 117 case MVT::v512i16: return "MVT::v512i16"; 118 case MVT::v1i32: return "MVT::v1i32"; 119 case MVT::v2i32: return "MVT::v2i32"; 120 case MVT::v3i32: return "MVT::v3i32"; 121 case MVT::v4i32: return "MVT::v4i32"; 122 case MVT::v5i32: return "MVT::v5i32"; 123 case MVT::v6i32: return "MVT::v6i32"; 124 case MVT::v7i32: return "MVT::v7i32"; 125 case MVT::v8i32: return "MVT::v8i32"; 126 case MVT::v16i32: return "MVT::v16i32"; 127 case MVT::v32i32: return "MVT::v32i32"; 128 case MVT::v64i32: return "MVT::v64i32"; 129 case MVT::v128i32: return "MVT::v128i32"; 130 case MVT::v256i32: return "MVT::v256i32"; 131 case MVT::v512i32: return "MVT::v512i32"; 132 case MVT::v1024i32: return "MVT::v1024i32"; 133 case MVT::v2048i32: return "MVT::v2048i32"; 134 case MVT::v1i64: return "MVT::v1i64"; 135 case MVT::v2i64: return "MVT::v2i64"; 136 case MVT::v3i64: return "MVT::v3i64"; 137 case MVT::v4i64: return "MVT::v4i64"; 138 case MVT::v8i64: return "MVT::v8i64"; 139 case MVT::v16i64: return "MVT::v16i64"; 140 case MVT::v32i64: return "MVT::v32i64"; 141 case MVT::v64i64: return "MVT::v64i64"; 142 case MVT::v128i64: return "MVT::v128i64"; 143 case MVT::v256i64: return "MVT::v256i64"; 144 case MVT::v1i128: return "MVT::v1i128"; 145 case MVT::v1f16: return "MVT::v1f16"; 146 case MVT::v2f16: return "MVT::v2f16"; 147 case MVT::v3f16: return "MVT::v3f16"; 148 case MVT::v4f16: return "MVT::v4f16"; 149 case MVT::v8f16: return "MVT::v8f16"; 150 case MVT::v16f16: return "MVT::v16f16"; 151 case MVT::v32f16: return "MVT::v32f16"; 152 case MVT::v64f16: return "MVT::v64f16"; 153 case MVT::v128f16: return "MVT::v128f16"; 154 case MVT::v256f16: return "MVT::v256f16"; 155 case MVT::v512f16: return "MVT::v512f16"; 156 case MVT::v2bf16: return "MVT::v2bf16"; 157 case MVT::v3bf16: return "MVT::v3bf16"; 158 case MVT::v4bf16: return "MVT::v4bf16"; 159 case MVT::v8bf16: return "MVT::v8bf16"; 160 case MVT::v16bf16: return "MVT::v16bf16"; 161 case MVT::v32bf16: return "MVT::v32bf16"; 162 case MVT::v64bf16: return "MVT::v64bf16"; 163 case MVT::v128bf16: return "MVT::v128bf16"; 164 case MVT::v1f32: return "MVT::v1f32"; 165 case MVT::v2f32: return "MVT::v2f32"; 166 case MVT::v3f32: return "MVT::v3f32"; 167 case MVT::v4f32: return "MVT::v4f32"; 168 case MVT::v5f32: return "MVT::v5f32"; 169 case MVT::v6f32: return "MVT::v6f32"; 170 case MVT::v7f32: return "MVT::v7f32"; 171 case MVT::v8f32: return "MVT::v8f32"; 172 case MVT::v16f32: return "MVT::v16f32"; 173 case MVT::v32f32: return "MVT::v32f32"; 174 case MVT::v64f32: return "MVT::v64f32"; 175 case MVT::v128f32: return "MVT::v128f32"; 176 case MVT::v256f32: return "MVT::v256f32"; 177 case MVT::v512f32: return "MVT::v512f32"; 178 case MVT::v1024f32: return "MVT::v1024f32"; 179 case MVT::v2048f32: return "MVT::v2048f32"; 180 case MVT::v1f64: return "MVT::v1f64"; 181 case MVT::v2f64: return "MVT::v2f64"; 182 case MVT::v3f64: return "MVT::v3f64"; 183 case MVT::v4f64: return "MVT::v4f64"; 184 case MVT::v8f64: return "MVT::v8f64"; 185 case MVT::v16f64: return "MVT::v16f64"; 186 case MVT::v32f64: return "MVT::v32f64"; 187 case MVT::v64f64: return "MVT::v64f64"; 188 case MVT::v128f64: return "MVT::v128f64"; 189 case MVT::v256f64: return "MVT::v256f64"; 190 case MVT::nxv1i1: return "MVT::nxv1i1"; 191 case MVT::nxv2i1: return "MVT::nxv2i1"; 192 case MVT::nxv4i1: return "MVT::nxv4i1"; 193 case MVT::nxv8i1: return "MVT::nxv8i1"; 194 case MVT::nxv16i1: return "MVT::nxv16i1"; 195 case MVT::nxv32i1: return "MVT::nxv32i1"; 196 case MVT::nxv64i1: return "MVT::nxv64i1"; 197 case MVT::nxv1i8: return "MVT::nxv1i8"; 198 case MVT::nxv2i8: return "MVT::nxv2i8"; 199 case MVT::nxv4i8: return "MVT::nxv4i8"; 200 case MVT::nxv8i8: return "MVT::nxv8i8"; 201 case MVT::nxv16i8: return "MVT::nxv16i8"; 202 case MVT::nxv32i8: return "MVT::nxv32i8"; 203 case MVT::nxv64i8: return "MVT::nxv64i8"; 204 case MVT::nxv1i16: return "MVT::nxv1i16"; 205 case MVT::nxv2i16: return "MVT::nxv2i16"; 206 case MVT::nxv4i16: return "MVT::nxv4i16"; 207 case MVT::nxv8i16: return "MVT::nxv8i16"; 208 case MVT::nxv16i16: return "MVT::nxv16i16"; 209 case MVT::nxv32i16: return "MVT::nxv32i16"; 210 case MVT::nxv1i32: return "MVT::nxv1i32"; 211 case MVT::nxv2i32: return "MVT::nxv2i32"; 212 case MVT::nxv4i32: return "MVT::nxv4i32"; 213 case MVT::nxv8i32: return "MVT::nxv8i32"; 214 case MVT::nxv16i32: return "MVT::nxv16i32"; 215 case MVT::nxv32i32: return "MVT::nxv32i32"; 216 case MVT::nxv1i64: return "MVT::nxv1i64"; 217 case MVT::nxv2i64: return "MVT::nxv2i64"; 218 case MVT::nxv4i64: return "MVT::nxv4i64"; 219 case MVT::nxv8i64: return "MVT::nxv8i64"; 220 case MVT::nxv16i64: return "MVT::nxv16i64"; 221 case MVT::nxv32i64: return "MVT::nxv32i64"; 222 case MVT::nxv1f16: return "MVT::nxv1f16"; 223 case MVT::nxv2f16: return "MVT::nxv2f16"; 224 case MVT::nxv4f16: return "MVT::nxv4f16"; 225 case MVT::nxv8f16: return "MVT::nxv8f16"; 226 case MVT::nxv16f16: return "MVT::nxv16f16"; 227 case MVT::nxv32f16: return "MVT::nxv32f16"; 228 case MVT::nxv1bf16: return "MVT::nxv1bf16"; 229 case MVT::nxv2bf16: return "MVT::nxv2bf16"; 230 case MVT::nxv4bf16: return "MVT::nxv4bf16"; 231 case MVT::nxv8bf16: return "MVT::nxv8bf16"; 232 case MVT::nxv16bf16: return "MVT::nxv16bf16"; 233 case MVT::nxv32bf16: return "MVT::nxv32bf16"; 234 case MVT::nxv1f32: return "MVT::nxv1f32"; 235 case MVT::nxv2f32: return "MVT::nxv2f32"; 236 case MVT::nxv4f32: return "MVT::nxv4f32"; 237 case MVT::nxv8f32: return "MVT::nxv8f32"; 238 case MVT::nxv16f32: return "MVT::nxv16f32"; 239 case MVT::nxv1f64: return "MVT::nxv1f64"; 240 case MVT::nxv2f64: return "MVT::nxv2f64"; 241 case MVT::nxv4f64: return "MVT::nxv4f64"; 242 case MVT::nxv8f64: return "MVT::nxv8f64"; 243 case MVT::token: return "MVT::token"; 244 case MVT::Metadata: return "MVT::Metadata"; 245 case MVT::iPTR: return "MVT::iPTR"; 246 case MVT::iPTRAny: return "MVT::iPTRAny"; 247 case MVT::Untyped: return "MVT::Untyped"; 248 case MVT::funcref: return "MVT::funcref"; 249 case MVT::externref: return "MVT::externref"; 250 default: llvm_unreachable("ILLEGAL VALUE TYPE!"); 251 } 252 // clang-format on 253 } 254 255 /// getQualifiedName - Return the name of the specified record, with a 256 /// namespace qualifier if the record contains one. 257 /// 258 std::string llvm::getQualifiedName(const Record *R) { 259 std::string Namespace; 260 if (R->getValue("Namespace")) 261 Namespace = std::string(R->getValueAsString("Namespace")); 262 if (Namespace.empty()) 263 return std::string(R->getName()); 264 return Namespace + "::" + R->getName().str(); 265 } 266 267 268 /// getTarget - Return the current instance of the Target class. 269 /// 270 CodeGenTarget::CodeGenTarget(RecordKeeper &records) 271 : Records(records), CGH(records) { 272 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target"); 273 if (Targets.size() == 0) 274 PrintFatalError("No 'Target' subclasses defined!"); 275 if (Targets.size() != 1) 276 PrintFatalError("Multiple subclasses of Target defined!"); 277 TargetRec = Targets[0]; 278 } 279 280 CodeGenTarget::~CodeGenTarget() { 281 } 282 283 StringRef CodeGenTarget::getName() const { return TargetRec->getName(); } 284 285 /// getInstNamespace - Find and return the target machine's instruction 286 /// namespace. The namespace is cached because it is requested multiple times. 287 StringRef CodeGenTarget::getInstNamespace() const { 288 if (InstNamespace.empty()) { 289 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) { 290 // We are not interested in the "TargetOpcode" namespace. 291 if (Inst->Namespace != "TargetOpcode") { 292 InstNamespace = Inst->Namespace; 293 break; 294 } 295 } 296 } 297 298 return InstNamespace; 299 } 300 301 StringRef CodeGenTarget::getRegNamespace() const { 302 auto &RegClasses = RegBank->getRegClasses(); 303 return RegClasses.size() > 0 ? RegClasses.front().Namespace : ""; 304 } 305 306 Record *CodeGenTarget::getInstructionSet() const { 307 return TargetRec->getValueAsDef("InstructionSet"); 308 } 309 310 bool CodeGenTarget::getAllowRegisterRenaming() const { 311 return TargetRec->getValueAsInt("AllowRegisterRenaming"); 312 } 313 314 /// getAsmParser - Return the AssemblyParser definition for this target. 315 /// 316 Record *CodeGenTarget::getAsmParser() const { 317 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers"); 318 if (AsmParserNum >= LI.size()) 319 PrintFatalError("Target does not have an AsmParser #" + 320 Twine(AsmParserNum) + "!"); 321 return LI[AsmParserNum]; 322 } 323 324 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 325 /// this target. 326 /// 327 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const { 328 std::vector<Record*> LI = 329 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 330 if (i >= LI.size()) 331 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) + 332 "!"); 333 return LI[i]; 334 } 335 336 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 337 /// available for this target. 338 /// 339 unsigned CodeGenTarget::getAsmParserVariantCount() const { 340 std::vector<Record*> LI = 341 TargetRec->getValueAsListOfDefs("AssemblyParserVariants"); 342 return LI.size(); 343 } 344 345 /// getAsmWriter - Return the AssemblyWriter definition for this target. 346 /// 347 Record *CodeGenTarget::getAsmWriter() const { 348 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters"); 349 if (AsmWriterNum >= LI.size()) 350 PrintFatalError("Target does not have an AsmWriter #" + 351 Twine(AsmWriterNum) + "!"); 352 return LI[AsmWriterNum]; 353 } 354 355 CodeGenRegBank &CodeGenTarget::getRegBank() const { 356 if (!RegBank) 357 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes()); 358 return *RegBank; 359 } 360 361 Optional<CodeGenRegisterClass *> 362 CodeGenTarget::getSuperRegForSubReg(const ValueTypeByHwMode &ValueTy, 363 CodeGenRegBank &RegBank, 364 const CodeGenSubRegIndex *SubIdx, 365 bool MustBeAllocatable) const { 366 std::vector<CodeGenRegisterClass *> Candidates; 367 auto &RegClasses = RegBank.getRegClasses(); 368 369 // Try to find a register class which supports ValueTy, and also contains 370 // SubIdx. 371 for (CodeGenRegisterClass &RC : RegClasses) { 372 // Is there a subclass of this class which contains this subregister index? 373 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx); 374 if (!SubClassWithSubReg) 375 continue; 376 377 // We have a class. Check if it supports this value type. 378 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy)) 379 continue; 380 381 // If necessary, check that it is allocatable. 382 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable) 383 continue; 384 385 // We have a register class which supports both the value type and 386 // subregister index. Remember it. 387 Candidates.push_back(SubClassWithSubReg); 388 } 389 390 // If we didn't find anything, we're done. 391 if (Candidates.empty()) 392 return None; 393 394 // Find and return the largest of our candidate classes. 395 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A, 396 const CodeGenRegisterClass *B) { 397 if (A->getMembers().size() > B->getMembers().size()) 398 return true; 399 400 if (A->getMembers().size() < B->getMembers().size()) 401 return false; 402 403 // Order by name as a tie-breaker. 404 return StringRef(A->getName()) < B->getName(); 405 }); 406 407 return Candidates[0]; 408 } 409 410 void CodeGenTarget::ReadRegAltNameIndices() const { 411 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); 412 llvm::sort(RegAltNameIndices, LessRecord()); 413 } 414 415 /// getRegisterByName - If there is a register with the specific AsmName, 416 /// return it. 417 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { 418 return getRegBank().getRegistersByName().lookup(Name); 419 } 420 421 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) 422 const { 423 const CodeGenRegister *Reg = getRegBank().getReg(R); 424 std::vector<ValueTypeByHwMode> Result; 425 for (const auto &RC : getRegBank().getRegClasses()) { 426 if (RC.contains(Reg)) { 427 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes(); 428 llvm::append_range(Result, InVTs); 429 } 430 } 431 432 // Remove duplicates. 433 llvm::sort(Result); 434 Result.erase(std::unique(Result.begin(), Result.end()), Result.end()); 435 return Result; 436 } 437 438 439 void CodeGenTarget::ReadLegalValueTypes() const { 440 for (const auto &RC : getRegBank().getRegClasses()) 441 llvm::append_range(LegalValueTypes, RC.VTs); 442 443 // Remove duplicates. 444 llvm::sort(LegalValueTypes); 445 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(), 446 LegalValueTypes.end()), 447 LegalValueTypes.end()); 448 } 449 450 CodeGenSchedModels &CodeGenTarget::getSchedModels() const { 451 if (!SchedModels) 452 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this); 453 return *SchedModels; 454 } 455 456 void CodeGenTarget::ReadInstructions() const { 457 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction"); 458 if (Insts.size() <= 2) 459 PrintFatalError("No 'Instruction' subclasses defined!"); 460 461 // Parse the instructions defined in the .td file. 462 for (unsigned i = 0, e = Insts.size(); i != e; ++i) 463 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]); 464 } 465 466 static const CodeGenInstruction * 467 GetInstByName(const char *Name, 468 const DenseMap<const Record*, 469 std::unique_ptr<CodeGenInstruction>> &Insts, 470 RecordKeeper &Records) { 471 const Record *Rec = Records.getDef(Name); 472 473 const auto I = Insts.find(Rec); 474 if (!Rec || I == Insts.end()) 475 PrintFatalError(Twine("Could not find '") + Name + "' instruction!"); 476 return I->second.get(); 477 } 478 479 static const char *FixedInstrs[] = { 480 #define HANDLE_TARGET_OPCODE(OPC) #OPC, 481 #include "llvm/Support/TargetOpcodes.def" 482 nullptr}; 483 484 unsigned CodeGenTarget::getNumFixedInstructions() { 485 return array_lengthof(FixedInstrs) - 1; 486 } 487 488 /// Return all of the instructions defined by the target, ordered by 489 /// their enum value. 490 void CodeGenTarget::ComputeInstrsByEnum() const { 491 const auto &Insts = getInstructions(); 492 for (const char *const *p = FixedInstrs; *p; ++p) { 493 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records); 494 assert(Instr && "Missing target independent instruction"); 495 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace"); 496 InstrsByEnum.push_back(Instr); 497 } 498 unsigned EndOfPredefines = InstrsByEnum.size(); 499 assert(EndOfPredefines == getNumFixedInstructions() && 500 "Missing generic opcode"); 501 502 for (const auto &I : Insts) { 503 const CodeGenInstruction *CGI = I.second.get(); 504 if (CGI->Namespace != "TargetOpcode") { 505 InstrsByEnum.push_back(CGI); 506 if (CGI->TheDef->getValueAsBit("isPseudo")) 507 ++NumPseudoInstructions; 508 } 509 } 510 511 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr"); 512 513 // All of the instructions are now in random order based on the map iteration. 514 llvm::sort( 515 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(), 516 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) { 517 const auto &D1 = *Rec1->TheDef; 518 const auto &D2 = *Rec2->TheDef; 519 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) < 520 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName()); 521 }); 522 } 523 524 525 /// isLittleEndianEncoding - Return whether this target encodes its instruction 526 /// in little-endian format, i.e. bits laid out in the order [0..n] 527 /// 528 bool CodeGenTarget::isLittleEndianEncoding() const { 529 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding"); 530 } 531 532 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 533 /// encodings, reverse the bit order of all instructions. 534 void CodeGenTarget::reverseBitsForLittleEndianEncoding() { 535 if (!isLittleEndianEncoding()) 536 return; 537 538 std::vector<Record *> Insts = 539 Records.getAllDerivedDefinitions("InstructionEncoding"); 540 for (Record *R : Insts) { 541 if (R->getValueAsString("Namespace") == "TargetOpcode" || 542 R->getValueAsBit("isPseudo")) 543 continue; 544 545 BitsInit *BI = R->getValueAsBitsInit("Inst"); 546 547 unsigned numBits = BI->getNumBits(); 548 549 SmallVector<Init *, 16> NewBits(numBits); 550 551 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { 552 unsigned bitSwapIdx = numBits - bit - 1; 553 Init *OrigBit = BI->getBit(bit); 554 Init *BitSwap = BI->getBit(bitSwapIdx); 555 NewBits[bit] = BitSwap; 556 NewBits[bitSwapIdx] = OrigBit; 557 } 558 if (numBits % 2) { 559 unsigned middle = (numBits + 1) / 2; 560 NewBits[middle] = BI->getBit(middle); 561 } 562 563 BitsInit *NewBI = BitsInit::get(Records, NewBits); 564 565 // Update the bits in reversed order so that emitInstrOpBits will get the 566 // correct endianness. 567 R->getValue("Inst")->setValue(NewBI); 568 } 569 } 570 571 /// guessInstructionProperties - Return true if it's OK to guess instruction 572 /// properties instead of raising an error. 573 /// 574 /// This is configurable as a temporary migration aid. It will eventually be 575 /// permanently false. 576 bool CodeGenTarget::guessInstructionProperties() const { 577 return getInstructionSet()->getValueAsBit("guessInstructionProperties"); 578 } 579 580 //===----------------------------------------------------------------------===// 581 // ComplexPattern implementation 582 // 583 ComplexPattern::ComplexPattern(Record *R) { 584 Ty = R->getValueAsDef("Ty"); 585 NumOperands = R->getValueAsInt("NumOperands"); 586 SelectFunc = std::string(R->getValueAsString("SelectFunc")); 587 RootNodes = R->getValueAsListOfDefs("RootNodes"); 588 589 // FIXME: This is a hack to statically increase the priority of patterns which 590 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best 591 // possible pattern match we'll need to dynamically calculate the complexity 592 // of all patterns a dag can potentially map to. 593 int64_t RawComplexity = R->getValueAsInt("Complexity"); 594 if (RawComplexity == -1) 595 Complexity = NumOperands * 3; 596 else 597 Complexity = RawComplexity; 598 599 // FIXME: Why is this different from parseSDPatternOperatorProperties? 600 // Parse the properties. 601 Properties = 0; 602 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties"); 603 for (unsigned i = 0, e = PropList.size(); i != e; ++i) 604 if (PropList[i]->getName() == "SDNPHasChain") { 605 Properties |= 1 << SDNPHasChain; 606 } else if (PropList[i]->getName() == "SDNPOptInGlue") { 607 Properties |= 1 << SDNPOptInGlue; 608 } else if (PropList[i]->getName() == "SDNPMayStore") { 609 Properties |= 1 << SDNPMayStore; 610 } else if (PropList[i]->getName() == "SDNPMayLoad") { 611 Properties |= 1 << SDNPMayLoad; 612 } else if (PropList[i]->getName() == "SDNPSideEffect") { 613 Properties |= 1 << SDNPSideEffect; 614 } else if (PropList[i]->getName() == "SDNPMemOperand") { 615 Properties |= 1 << SDNPMemOperand; 616 } else if (PropList[i]->getName() == "SDNPVariadic") { 617 Properties |= 1 << SDNPVariadic; 618 } else if (PropList[i]->getName() == "SDNPWantRoot") { 619 Properties |= 1 << SDNPWantRoot; 620 } else if (PropList[i]->getName() == "SDNPWantParent") { 621 Properties |= 1 << SDNPWantParent; 622 } else { 623 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" + 624 PropList[i]->getName() + 625 "' on ComplexPattern '" + R->getName() + 626 "'!"); 627 } 628 } 629 630 //===----------------------------------------------------------------------===// 631 // CodeGenIntrinsic Implementation 632 //===----------------------------------------------------------------------===// 633 634 CodeGenIntrinsicTable::CodeGenIntrinsicTable(const RecordKeeper &RC) { 635 std::vector<Record *> IntrProperties = 636 RC.getAllDerivedDefinitions("IntrinsicProperty"); 637 638 std::vector<Record *> DefaultProperties; 639 for (Record *Rec : IntrProperties) 640 if (Rec->getValueAsBit("IsDefault")) 641 DefaultProperties.push_back(Rec); 642 643 std::vector<Record *> Defs = RC.getAllDerivedDefinitions("Intrinsic"); 644 Intrinsics.reserve(Defs.size()); 645 646 for (unsigned I = 0, e = Defs.size(); I != e; ++I) 647 Intrinsics.push_back(CodeGenIntrinsic(Defs[I], DefaultProperties)); 648 649 llvm::sort(Intrinsics, 650 [](const CodeGenIntrinsic &LHS, const CodeGenIntrinsic &RHS) { 651 return std::tie(LHS.TargetPrefix, LHS.Name) < 652 std::tie(RHS.TargetPrefix, RHS.Name); 653 }); 654 Targets.push_back({"", 0, 0}); 655 for (size_t I = 0, E = Intrinsics.size(); I < E; ++I) 656 if (Intrinsics[I].TargetPrefix != Targets.back().Name) { 657 Targets.back().Count = I - Targets.back().Offset; 658 Targets.push_back({Intrinsics[I].TargetPrefix, I, 0}); 659 } 660 Targets.back().Count = Intrinsics.size() - Targets.back().Offset; 661 } 662 663 CodeGenIntrinsic::CodeGenIntrinsic(Record *R, 664 std::vector<Record *> DefaultProperties) { 665 TheDef = R; 666 std::string DefName = std::string(R->getName()); 667 ArrayRef<SMLoc> DefLoc = R->getLoc(); 668 ModRef = ReadWriteMem; 669 Properties = 0; 670 isOverloaded = false; 671 isCommutative = false; 672 canThrow = false; 673 isNoReturn = false; 674 isNoCallback = false; 675 isNoSync = false; 676 isNoFree = false; 677 isWillReturn = false; 678 isCold = false; 679 isNoDuplicate = false; 680 isNoMerge = false; 681 isConvergent = false; 682 isSpeculatable = false; 683 hasSideEffects = false; 684 685 if (DefName.size() <= 4 || DefName.substr(0, 4) != "int_") 686 PrintFatalError(DefLoc, 687 "Intrinsic '" + DefName + "' does not start with 'int_'!"); 688 689 EnumName = DefName.substr(4); 690 691 if (R->getValue("ClangBuiltinName")) // Ignore a missing ClangBuiltinName field. 692 ClangBuiltinName = std::string(R->getValueAsString("ClangBuiltinName")); 693 if (R->getValue("MSBuiltinName")) // Ignore a missing MSBuiltinName field. 694 MSBuiltinName = std::string(R->getValueAsString("MSBuiltinName")); 695 696 TargetPrefix = std::string(R->getValueAsString("TargetPrefix")); 697 Name = std::string(R->getValueAsString("LLVMName")); 698 699 if (Name == "") { 700 // If an explicit name isn't specified, derive one from the DefName. 701 Name = "llvm."; 702 703 for (unsigned i = 0, e = EnumName.size(); i != e; ++i) 704 Name += (EnumName[i] == '_') ? '.' : EnumName[i]; 705 } else { 706 // Verify it starts with "llvm.". 707 if (Name.size() <= 5 || Name.substr(0, 5) != "llvm.") 708 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 709 "'s name does not start with 'llvm.'!"); 710 } 711 712 // If TargetPrefix is specified, make sure that Name starts with 713 // "llvm.<targetprefix>.". 714 if (!TargetPrefix.empty()) { 715 if (Name.size() < 6+TargetPrefix.size() || 716 Name.substr(5, 1 + TargetPrefix.size()) != (TargetPrefix + ".")) 717 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 718 "' does not start with 'llvm." + 719 TargetPrefix + ".'!"); 720 } 721 722 ListInit *RetTypes = R->getValueAsListInit("RetTypes"); 723 ListInit *ParamTypes = R->getValueAsListInit("ParamTypes"); 724 725 // First collate a list of overloaded types. 726 std::vector<MVT::SimpleValueType> OverloadedVTs; 727 for (ListInit *TypeList : {RetTypes, ParamTypes}) { 728 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 729 Record *TyEl = TypeList->getElementAsRecord(i); 730 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 731 732 if (TyEl->isSubClassOf("LLVMMatchType")) 733 continue; 734 735 MVT::SimpleValueType VT = getValueType(TyEl->getValueAsDef("VT")); 736 if (MVT(VT).isOverloaded()) { 737 OverloadedVTs.push_back(VT); 738 isOverloaded = true; 739 } 740 } 741 } 742 743 // Parse the list of return types. 744 ListInit *TypeList = RetTypes; 745 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 746 Record *TyEl = TypeList->getElementAsRecord(i); 747 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 748 MVT::SimpleValueType VT; 749 if (TyEl->isSubClassOf("LLVMMatchType")) { 750 unsigned MatchTy = TyEl->getValueAsInt("Number"); 751 assert(MatchTy < OverloadedVTs.size() && 752 "Invalid matching number!"); 753 VT = OverloadedVTs[MatchTy]; 754 // It only makes sense to use the extended and truncated vector element 755 // variants with iAny types; otherwise, if the intrinsic is not 756 // overloaded, all the types can be specified directly. 757 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 758 !TyEl->isSubClassOf("LLVMTruncatedType")) || 759 VT == MVT::iAny || VT == MVT::vAny) && 760 "Expected iAny or vAny type"); 761 } else { 762 VT = getValueType(TyEl->getValueAsDef("VT")); 763 } 764 765 // Reject invalid types. 766 if (VT == MVT::isVoid) 767 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 768 " has void in result type list!"); 769 770 IS.RetVTs.push_back(VT); 771 IS.RetTypeDefs.push_back(TyEl); 772 } 773 774 // Parse the list of parameter types. 775 TypeList = ParamTypes; 776 for (unsigned i = 0, e = TypeList->size(); i != e; ++i) { 777 Record *TyEl = TypeList->getElementAsRecord(i); 778 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); 779 MVT::SimpleValueType VT; 780 if (TyEl->isSubClassOf("LLVMMatchType")) { 781 unsigned MatchTy = TyEl->getValueAsInt("Number"); 782 if (MatchTy >= OverloadedVTs.size()) { 783 PrintError(R->getLoc(), 784 "Parameter #" + Twine(i) + " has out of bounds matching " 785 "number " + Twine(MatchTy)); 786 PrintFatalError(DefLoc, 787 Twine("ParamTypes is ") + TypeList->getAsString()); 788 } 789 VT = OverloadedVTs[MatchTy]; 790 // It only makes sense to use the extended and truncated vector element 791 // variants with iAny types; otherwise, if the intrinsic is not 792 // overloaded, all the types can be specified directly. 793 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && 794 !TyEl->isSubClassOf("LLVMTruncatedType")) || 795 VT == MVT::iAny || VT == MVT::vAny) && 796 "Expected iAny or vAny type"); 797 } else 798 VT = getValueType(TyEl->getValueAsDef("VT")); 799 800 // Reject invalid types. 801 if (VT == MVT::isVoid && i != e-1 /*void at end means varargs*/) 802 PrintFatalError(DefLoc, "Intrinsic '" + DefName + 803 " has void in result type list!"); 804 805 IS.ParamVTs.push_back(VT); 806 IS.ParamTypeDefs.push_back(TyEl); 807 } 808 809 // Parse the intrinsic properties. 810 ListInit *PropList = R->getValueAsListInit("IntrProperties"); 811 for (unsigned i = 0, e = PropList->size(); i != e; ++i) { 812 Record *Property = PropList->getElementAsRecord(i); 813 assert(Property->isSubClassOf("IntrinsicProperty") && 814 "Expected a property!"); 815 816 setProperty(Property); 817 } 818 819 // Set default properties to true. 820 setDefaultProperties(R, DefaultProperties); 821 822 // Also record the SDPatternOperator Properties. 823 Properties = parseSDPatternOperatorProperties(R); 824 825 // Sort the argument attributes for later benefit. 826 llvm::sort(ArgumentAttributes); 827 } 828 829 void CodeGenIntrinsic::setDefaultProperties( 830 Record *R, std::vector<Record *> DefaultProperties) { 831 // opt-out of using default attributes. 832 if (R->getValueAsBit("DisableDefaultAttributes")) 833 return; 834 835 for (Record *Rec : DefaultProperties) 836 setProperty(Rec); 837 } 838 839 void CodeGenIntrinsic::setProperty(Record *R) { 840 if (R->getName() == "IntrNoMem") 841 ModRef = NoMem; 842 else if (R->getName() == "IntrReadMem") { 843 if (!(ModRef & MR_Ref)) 844 PrintFatalError(TheDef->getLoc(), 845 Twine("IntrReadMem cannot be used after IntrNoMem or " 846 "IntrWriteMem. Default is ReadWrite")); 847 ModRef = ModRefBehavior(ModRef & ~MR_Mod); 848 } else if (R->getName() == "IntrWriteMem") { 849 if (!(ModRef & MR_Mod)) 850 PrintFatalError(TheDef->getLoc(), 851 Twine("IntrWriteMem cannot be used after IntrNoMem or " 852 "IntrReadMem. Default is ReadWrite")); 853 ModRef = ModRefBehavior(ModRef & ~MR_Ref); 854 } else if (R->getName() == "IntrArgMemOnly") 855 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem); 856 else if (R->getName() == "IntrInaccessibleMemOnly") 857 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_InaccessibleMem); 858 else if (R->getName() == "IntrInaccessibleMemOrArgMemOnly") 859 ModRef = ModRefBehavior((ModRef & ~MR_Anywhere) | MR_ArgMem | 860 MR_InaccessibleMem); 861 else if (R->getName() == "Commutative") 862 isCommutative = true; 863 else if (R->getName() == "Throws") 864 canThrow = true; 865 else if (R->getName() == "IntrNoDuplicate") 866 isNoDuplicate = true; 867 else if (R->getName() == "IntrNoMerge") 868 isNoMerge = true; 869 else if (R->getName() == "IntrConvergent") 870 isConvergent = true; 871 else if (R->getName() == "IntrNoReturn") 872 isNoReturn = true; 873 else if (R->getName() == "IntrNoCallback") 874 isNoCallback = true; 875 else if (R->getName() == "IntrNoSync") 876 isNoSync = true; 877 else if (R->getName() == "IntrNoFree") 878 isNoFree = true; 879 else if (R->getName() == "IntrWillReturn") 880 isWillReturn = !isNoReturn; 881 else if (R->getName() == "IntrCold") 882 isCold = true; 883 else if (R->getName() == "IntrSpeculatable") 884 isSpeculatable = true; 885 else if (R->getName() == "IntrHasSideEffects") 886 hasSideEffects = true; 887 else if (R->isSubClassOf("NoCapture")) { 888 unsigned ArgNo = R->getValueAsInt("ArgNo"); 889 ArgumentAttributes.emplace_back(ArgNo, NoCapture, 0); 890 } else if (R->isSubClassOf("NoAlias")) { 891 unsigned ArgNo = R->getValueAsInt("ArgNo"); 892 ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0); 893 } else if (R->isSubClassOf("NoUndef")) { 894 unsigned ArgNo = R->getValueAsInt("ArgNo"); 895 ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0); 896 } else if (R->isSubClassOf("Returned")) { 897 unsigned ArgNo = R->getValueAsInt("ArgNo"); 898 ArgumentAttributes.emplace_back(ArgNo, Returned, 0); 899 } else if (R->isSubClassOf("ReadOnly")) { 900 unsigned ArgNo = R->getValueAsInt("ArgNo"); 901 ArgumentAttributes.emplace_back(ArgNo, ReadOnly, 0); 902 } else if (R->isSubClassOf("WriteOnly")) { 903 unsigned ArgNo = R->getValueAsInt("ArgNo"); 904 ArgumentAttributes.emplace_back(ArgNo, WriteOnly, 0); 905 } else if (R->isSubClassOf("ReadNone")) { 906 unsigned ArgNo = R->getValueAsInt("ArgNo"); 907 ArgumentAttributes.emplace_back(ArgNo, ReadNone, 0); 908 } else if (R->isSubClassOf("ImmArg")) { 909 unsigned ArgNo = R->getValueAsInt("ArgNo"); 910 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); 911 } else if (R->isSubClassOf("Align")) { 912 unsigned ArgNo = R->getValueAsInt("ArgNo"); 913 uint64_t Align = R->getValueAsInt("Align"); 914 ArgumentAttributes.emplace_back(ArgNo, Alignment, Align); 915 } else 916 llvm_unreachable("Unknown property!"); 917 } 918 919 bool CodeGenIntrinsic::isParamAPointer(unsigned ParamIdx) const { 920 if (ParamIdx >= IS.ParamVTs.size()) 921 return false; 922 MVT ParamType = MVT(IS.ParamVTs[ParamIdx]); 923 return ParamType == MVT::iPTR || ParamType == MVT::iPTRAny; 924 } 925 926 bool CodeGenIntrinsic::isParamImmArg(unsigned ParamIdx) const { 927 // Convert argument index to attribute index starting from `FirstArgIndex`. 928 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; 929 return std::binary_search(ArgumentAttributes.begin(), 930 ArgumentAttributes.end(), Val); 931 } 932