1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines wrappers for the Target class and related global 10 // functionality. This makes it easier to access the data and provides a single 11 // place that needs to check it for validity. All of these classes abort 12 // on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 17 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 18 19 #include "CodeGenHwModes.h" 20 #include "CodeGenRegisters.h" 21 #include "InfoByHwMode.h" 22 #include "SDNodeProperties.h" 23 24 namespace llvm { 25 26 class RecordKeeper; 27 class Record; 28 class CodeGenInstruction; 29 struct CodeGenRegister; 30 class CodeGenSchedModels; 31 class CodeGenTarget; 32 33 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 34 /// record corresponds to. 35 MVT::SimpleValueType getValueType(Record *Rec); 36 37 StringRef getName(MVT::SimpleValueType T); 38 StringRef getEnumName(MVT::SimpleValueType T); 39 40 /// getQualifiedName - Return the name of the specified record, with a 41 /// namespace qualifier if the record contains one. 42 std::string getQualifiedName(const Record *R); 43 44 /// CodeGenTarget - This class corresponds to the Target class in the .td files. 45 /// 46 class CodeGenTarget { 47 RecordKeeper &Records; 48 Record *TargetRec; 49 50 mutable DenseMap<const Record*, 51 std::unique_ptr<CodeGenInstruction>> Instructions; 52 mutable std::unique_ptr<CodeGenRegBank> RegBank; 53 mutable std::vector<Record*> RegAltNameIndices; 54 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes; 55 CodeGenHwModes CGH; 56 void ReadRegAltNameIndices() const; 57 void ReadInstructions() const; 58 void ReadLegalValueTypes() const; 59 60 mutable std::unique_ptr<CodeGenSchedModels> SchedModels; 61 62 mutable StringRef InstNamespace; 63 mutable std::vector<const CodeGenInstruction*> InstrsByEnum; 64 mutable unsigned NumPseudoInstructions = 0; 65 public: 66 CodeGenTarget(RecordKeeper &Records); 67 ~CodeGenTarget(); 68 69 Record *getTargetRecord() const { return TargetRec; } 70 StringRef getName() const; 71 72 /// getInstNamespace - Return the target-specific instruction namespace. 73 /// 74 StringRef getInstNamespace() const; 75 76 /// getRegNamespace - Return the target-specific register namespace. 77 StringRef getRegNamespace() const; 78 79 /// getInstructionSet - Return the InstructionSet object. 80 /// 81 Record *getInstructionSet() const; 82 83 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for 84 /// this target. 85 /// 86 bool getAllowRegisterRenaming() const; 87 88 /// getAsmParser - Return the AssemblyParser definition for this target. 89 /// 90 Record *getAsmParser() const; 91 92 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 93 /// this target. 94 /// 95 Record *getAsmParserVariant(unsigned i) const; 96 97 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 98 /// available for this target. 99 /// 100 unsigned getAsmParserVariantCount() const; 101 102 /// getAsmWriter - Return the AssemblyWriter definition for this target. 103 /// 104 Record *getAsmWriter() const; 105 106 /// getRegBank - Return the register bank description. 107 CodeGenRegBank &getRegBank() const; 108 109 /// Return the largest register class on \p RegBank which supports \p Ty and 110 /// covers \p SubIdx if it exists. 111 Optional<CodeGenRegisterClass *> 112 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank, 113 const CodeGenSubRegIndex *SubIdx, 114 bool MustBeAllocatable = false) const; 115 116 /// getRegisterByName - If there is a register with the specific AsmName, 117 /// return it. 118 const CodeGenRegister *getRegisterByName(StringRef Name) const; 119 120 const std::vector<Record*> &getRegAltNameIndices() const { 121 if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); 122 return RegAltNameIndices; 123 } 124 125 const CodeGenRegisterClass &getRegisterClass(Record *R) const { 126 return *getRegBank().getRegClass(R); 127 } 128 129 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the 130 /// specified physical register. 131 std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const; 132 133 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const { 134 if (LegalValueTypes.empty()) 135 ReadLegalValueTypes(); 136 return LegalValueTypes; 137 } 138 139 CodeGenSchedModels &getSchedModels() const; 140 141 const CodeGenHwModes &getHwModes() const { return CGH; } 142 143 private: 144 DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> & 145 getInstructions() const { 146 if (Instructions.empty()) ReadInstructions(); 147 return Instructions; 148 } 149 public: 150 151 CodeGenInstruction &getInstruction(const Record *InstRec) const { 152 if (Instructions.empty()) ReadInstructions(); 153 auto I = Instructions.find(InstRec); 154 assert(I != Instructions.end() && "Not an instruction"); 155 return *I->second; 156 } 157 158 /// Returns the number of predefined instructions. 159 static unsigned getNumFixedInstructions(); 160 161 /// Returns the number of pseudo instructions. 162 unsigned getNumPseudoInstructions() const { 163 if (InstrsByEnum.empty()) 164 ComputeInstrsByEnum(); 165 return NumPseudoInstructions; 166 } 167 168 /// Return all of the instructions defined by the target, ordered by their 169 /// enum value. 170 /// The following order of instructions is also guaranteed: 171 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order; 172 /// - pseudo instructions in lexicographical order sorted by name; 173 /// - other instructions in lexicographical order sorted by name. 174 ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const { 175 if (InstrsByEnum.empty()) 176 ComputeInstrsByEnum(); 177 return InstrsByEnum; 178 } 179 180 typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator; 181 inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();} 182 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } 183 184 185 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? 186 /// 187 bool isLittleEndianEncoding() const; 188 189 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 190 /// encodings, reverse the bit order of all instructions. 191 void reverseBitsForLittleEndianEncoding(); 192 193 /// guessInstructionProperties - should we just guess unset instruction 194 /// properties? 195 bool guessInstructionProperties() const; 196 197 private: 198 void ComputeInstrsByEnum() const; 199 }; 200 201 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern 202 /// tablegen class in TargetSelectionDAG.td 203 class ComplexPattern { 204 Record *Ty; 205 unsigned NumOperands; 206 std::string SelectFunc; 207 std::vector<Record*> RootNodes; 208 unsigned Properties; // Node properties 209 unsigned Complexity; 210 public: 211 ComplexPattern(Record *R); 212 213 Record *getValueType() const { return Ty; } 214 unsigned getNumOperands() const { return NumOperands; } 215 const std::string &getSelectFunc() const { return SelectFunc; } 216 const std::vector<Record*> &getRootNodes() const { 217 return RootNodes; 218 } 219 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); } 220 unsigned getComplexity() const { return Complexity; } 221 }; 222 223 } // End llvm namespace 224 225 #endif 226