1 //===--- InfoByHwMode.cpp -------------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // Classes that implement data parameterized by HW modes for instruction 9 // selection. Currently it is ValueTypeByHwMode (parameterized ValueType), 10 // and RegSizeInfoByHwMode (parameterized register/spill size and alignment 11 // data). 12 //===----------------------------------------------------------------------===// 13 14 #include "CodeGenTarget.h" 15 #include "InfoByHwMode.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/Support/Debug.h" 19 #include "llvm/Support/raw_ostream.h" 20 21 #include <string> 22 23 using namespace llvm; 24 25 std::string llvm::getModeName(unsigned Mode) { 26 if (Mode == DefaultMode) 27 return "*"; 28 return (Twine('m') + Twine(Mode)).str(); 29 } 30 31 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH) { 32 const HwModeSelect &MS = CGH.getHwModeSelect(R); 33 for (const HwModeSelect::PairType &P : MS.Items) { 34 auto I = Map.insert({P.first, MVT(llvm::getValueType(P.second))}); 35 assert(I.second && "Duplicate entry?"); 36 (void)I; 37 } 38 } 39 40 ValueTypeByHwMode::ValueTypeByHwMode(Record *R, MVT T) : ValueTypeByHwMode(T) { 41 if (R->isSubClassOf("PtrValueType")) 42 PtrAddrSpace = R->getValueAsInt("AddrSpace"); 43 } 44 45 bool ValueTypeByHwMode::operator== (const ValueTypeByHwMode &T) const { 46 assert(isValid() && T.isValid() && "Invalid type in assignment"); 47 bool Simple = isSimple(); 48 if (Simple != T.isSimple()) 49 return false; 50 if (Simple) 51 return getSimple() == T.getSimple(); 52 53 return Map == T.Map; 54 } 55 56 bool ValueTypeByHwMode::operator< (const ValueTypeByHwMode &T) const { 57 assert(isValid() && T.isValid() && "Invalid type in comparison"); 58 // Default order for maps. 59 return Map < T.Map; 60 } 61 62 MVT &ValueTypeByHwMode::getOrCreateTypeForMode(unsigned Mode, MVT Type) { 63 auto F = Map.find(Mode); 64 if (F != Map.end()) 65 return F->second; 66 // If Mode is not in the map, look up the default mode. If it exists, 67 // make a copy of it for Mode and return it. 68 auto D = Map.find(DefaultMode); 69 if (D != Map.end()) 70 return Map.insert(std::make_pair(Mode, D->second)).first->second; 71 // If default mode is not present either, use provided Type. 72 return Map.insert(std::make_pair(Mode, Type)).first->second; 73 } 74 75 StringRef ValueTypeByHwMode::getMVTName(MVT T) { 76 StringRef N = llvm::getEnumName(T.SimpleTy); 77 N.consume_front("MVT::"); 78 return N; 79 } 80 81 void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const { 82 if (isSimple()) { 83 OS << getMVTName(getSimple()); 84 return; 85 } 86 87 std::vector<const PairType*> Pairs; 88 for (const auto &P : Map) 89 Pairs.push_back(&P); 90 llvm::sort(Pairs, deref<std::less<PairType>>()); 91 92 OS << '{'; 93 ListSeparator LS(","); 94 for (const PairType *P : Pairs) 95 OS << LS << '(' << getModeName(P->first) << ':' 96 << getMVTName(P->second).str() << ')'; 97 OS << '}'; 98 } 99 100 LLVM_DUMP_METHOD 101 void ValueTypeByHwMode::dump() const { 102 dbgs() << *this << '\n'; 103 } 104 105 ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec, 106 const CodeGenHwModes &CGH) { 107 #ifndef NDEBUG 108 if (!Rec->isSubClassOf("ValueType")) 109 Rec->dump(); 110 #endif 111 assert(Rec->isSubClassOf("ValueType") && 112 "Record must be derived from ValueType"); 113 if (Rec->isSubClassOf("HwModeSelect")) 114 return ValueTypeByHwMode(Rec, CGH); 115 return ValueTypeByHwMode(Rec, llvm::getValueType(Rec)); 116 } 117 118 RegSizeInfo::RegSizeInfo(Record *R, const CodeGenHwModes &CGH) { 119 RegSize = R->getValueAsInt("RegSize"); 120 SpillSize = R->getValueAsInt("SpillSize"); 121 SpillAlignment = R->getValueAsInt("SpillAlignment"); 122 } 123 124 bool RegSizeInfo::operator< (const RegSizeInfo &I) const { 125 return std::tie(RegSize, SpillSize, SpillAlignment) < 126 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment); 127 } 128 129 bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const { 130 return RegSize <= I.RegSize && 131 SpillAlignment && I.SpillAlignment % SpillAlignment == 0 && 132 SpillSize <= I.SpillSize; 133 } 134 135 void RegSizeInfo::writeToStream(raw_ostream &OS) const { 136 OS << "[R=" << RegSize << ",S=" << SpillSize 137 << ",A=" << SpillAlignment << ']'; 138 } 139 140 RegSizeInfoByHwMode::RegSizeInfoByHwMode(Record *R, 141 const CodeGenHwModes &CGH) { 142 const HwModeSelect &MS = CGH.getHwModeSelect(R); 143 for (const HwModeSelect::PairType &P : MS.Items) { 144 auto I = Map.insert({P.first, RegSizeInfo(P.second, CGH)}); 145 assert(I.second && "Duplicate entry?"); 146 (void)I; 147 } 148 } 149 150 bool RegSizeInfoByHwMode::operator< (const RegSizeInfoByHwMode &I) const { 151 unsigned M0 = Map.begin()->first; 152 return get(M0) < I.get(M0); 153 } 154 155 bool RegSizeInfoByHwMode::operator== (const RegSizeInfoByHwMode &I) const { 156 unsigned M0 = Map.begin()->first; 157 return get(M0) == I.get(M0); 158 } 159 160 bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const { 161 unsigned M0 = Map.begin()->first; 162 return get(M0).isSubClassOf(I.get(M0)); 163 } 164 165 bool RegSizeInfoByHwMode::hasStricterSpillThan(const RegSizeInfoByHwMode &I) 166 const { 167 unsigned M0 = Map.begin()->first; 168 const RegSizeInfo &A0 = get(M0); 169 const RegSizeInfo &B0 = I.get(M0); 170 return std::tie(A0.SpillSize, A0.SpillAlignment) > 171 std::tie(B0.SpillSize, B0.SpillAlignment); 172 } 173 174 void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const { 175 typedef typename decltype(Map)::value_type PairType; 176 std::vector<const PairType*> Pairs; 177 for (const auto &P : Map) 178 Pairs.push_back(&P); 179 llvm::sort(Pairs, deref<std::less<PairType>>()); 180 181 OS << '{'; 182 ListSeparator LS(","); 183 for (const PairType *P : Pairs) 184 OS << LS << '(' << getModeName(P->first) << ':' << P->second << ')'; 185 OS << '}'; 186 } 187 188 EncodingInfoByHwMode::EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH) { 189 const HwModeSelect &MS = CGH.getHwModeSelect(R); 190 for (const HwModeSelect::PairType &P : MS.Items) { 191 assert(P.second && P.second->isSubClassOf("InstructionEncoding") && 192 "Encoding must subclass InstructionEncoding"); 193 auto I = Map.insert({P.first, P.second}); 194 assert(I.second && "Duplicate entry?"); 195 (void)I; 196 } 197 } 198 199 namespace llvm { 200 raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) { 201 T.writeToStream(OS); 202 return OS; 203 } 204 205 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) { 206 T.writeToStream(OS); 207 return OS; 208 } 209 210 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) { 211 T.writeToStream(OS); 212 return OS; 213 } 214 } 215