1 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "CodeGenInstruction.h"
10 #include "CodeGenTarget.h"
11 #include "llvm/ADT/IndexedMap.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/StringMap.h"
14 #include "llvm/Support/Debug.h"
15 #include "llvm/Support/ErrorHandling.h"
16 #include "llvm/TableGen/Error.h"
17 #include "llvm/TableGen/Record.h"
18 #include "llvm/TableGen/TableGenBackend.h"
19 #include <vector>
20 using namespace llvm;
21 
22 #define DEBUG_TYPE "pseudo-lowering"
23 
24 namespace {
25 class PseudoLoweringEmitter {
26   struct OpData {
27     enum MapKind { Operand, Imm, Reg };
28     MapKind Kind;
29     union {
30       unsigned Operand;   // Operand number mapped to.
31       uint64_t Imm;       // Integer immedate value.
32       Record *Reg;        // Physical register.
33     } Data;
34   };
35   struct PseudoExpansion {
36     CodeGenInstruction Source;  // The source pseudo instruction definition.
37     CodeGenInstruction Dest;    // The destination instruction to lower to.
38     IndexedMap<OpData> OperandMap;
39 
40     PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
41                     IndexedMap<OpData> &m) :
42       Source(s), Dest(d), OperandMap(m) {}
43   };
44 
45   RecordKeeper &Records;
46 
47   // It's overkill to have an instance of the full CodeGenTarget object,
48   // but it loads everything on demand, not in the constructor, so it's
49   // lightweight in performance, so it works out OK.
50   CodeGenTarget Target;
51 
52   SmallVector<PseudoExpansion, 64> Expansions;
53 
54   unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
55                                 CodeGenInstruction &Insn,
56                                 IndexedMap<OpData> &OperandMap,
57                                 unsigned BaseIdx);
58   void evaluateExpansion(Record *Pseudo);
59   void emitLoweringEmitter(raw_ostream &o);
60 public:
61   PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
62 
63   /// run - Output the pseudo-lowerings.
64   void run(raw_ostream &o);
65 };
66 } // End anonymous namespace
67 
68 // FIXME: This pass currently can only expand a pseudo to a single instruction.
69 //        The pseudo expansion really should take a list of dags, not just
70 //        a single dag, so we can do fancier things.
71 
72 unsigned PseudoLoweringEmitter::
73 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
74                      IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
75   unsigned OpsAdded = 0;
76   for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
77     if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
78       // Physical register reference. Explicit check for the special case
79       // "zero_reg" definition.
80       if (DI->getDef()->isSubClassOf("Register") ||
81           DI->getDef()->getName() == "zero_reg") {
82         OperandMap[BaseIdx + i].Kind = OpData::Reg;
83         OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
84         ++OpsAdded;
85         continue;
86       }
87 
88       // Normal operands should always have the same type, or we have a
89       // problem.
90       // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
91       assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
92       // FIXME: Are the message operand types backward?
93       if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
94         PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
95                         "', operand type '" + DI->getDef()->getName() +
96                         "' does not match expansion operand type '" +
97                         Insn.Operands[BaseIdx + i].Rec->getName() + "'");
98         PrintFatalNote(DI->getDef(),
99                        "Value was assigned at the following location:");
100       }
101       // Source operand maps to destination operand. The Data element
102       // will be filled in later, just set the Kind for now. Do it
103       // for each corresponding MachineInstr operand, not just the first.
104       for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
105         OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
106       OpsAdded += Insn.Operands[i].MINumOperands;
107     } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
108       OperandMap[BaseIdx + i].Kind = OpData::Imm;
109       OperandMap[BaseIdx + i].Data.Imm = II->getValue();
110       ++OpsAdded;
111     } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
112       // Just add the operands recursively. This is almost certainly
113       // a constant value for a complex operand (> 1 MI operand).
114       unsigned NewOps =
115         addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
116       OpsAdded += NewOps;
117       // Since we added more than one, we also need to adjust the base.
118       BaseIdx += NewOps - 1;
119     } else
120       llvm_unreachable("Unhandled pseudo-expansion argument type!");
121   }
122   return OpsAdded;
123 }
124 
125 void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
126   LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
127 
128   // Validate that the result pattern has the corrent number and types
129   // of arguments for the instruction it references.
130   DagInit *Dag = Rec->getValueAsDag("ResultInst");
131   assert(Dag && "Missing result instruction in pseudo expansion!");
132   LLVM_DEBUG(dbgs() << "  Result: " << *Dag << "\n");
133 
134   DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
135   if (!OpDef) {
136     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
137                     "', result operator is not a record");
138     PrintFatalNote(Rec->getValue("ResultInst"),
139                    "Result was assigned at the following location:");
140   }
141   Record *Operator = OpDef->getDef();
142   if (!Operator->isSubClassOf("Instruction")) {
143     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
144                     "', result operator '" + Operator->getName() +
145                     "' is not an instruction");
146     PrintFatalNote(Rec->getValue("ResultInst"),
147                    "Result was assigned at the following location:");
148   }
149 
150   CodeGenInstruction Insn(Operator);
151 
152   if (Insn.isCodeGenOnly || Insn.isPseudo) {
153     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
154                     "', result operator '" + Operator->getName() +
155                     "' cannot be a pseudo instruction");
156     PrintFatalNote(Rec->getValue("ResultInst"),
157                    "Result was assigned at the following location:");
158   }
159 
160   if (Insn.Operands.size() != Dag->getNumArgs()) {
161     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
162                     "', result operator '" + Operator->getName() +
163                     "' has the wrong number of operands");
164     PrintFatalNote(Rec->getValue("ResultInst"),
165                    "Result was assigned at the following location:");
166   }
167 
168   unsigned NumMIOperands = 0;
169   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
170     NumMIOperands += Insn.Operands[i].MINumOperands;
171   IndexedMap<OpData> OperandMap;
172   OperandMap.grow(NumMIOperands);
173 
174   addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
175 
176   // If there are more operands that weren't in the DAG, they have to
177   // be operands that have default values, or we have an error. Currently,
178   // Operands that are a subclass of OperandWithDefaultOp have default values.
179 
180   // Validate that each result pattern argument has a matching (by name)
181   // argument in the source instruction, in either the (outs) or (ins) list.
182   // Also check that the type of the arguments match.
183   //
184   // Record the mapping of the source to result arguments for use by
185   // the lowering emitter.
186   CodeGenInstruction SourceInsn(Rec);
187   StringMap<unsigned> SourceOperands;
188   for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
189     SourceOperands[SourceInsn.Operands[i].Name] = i;
190 
191   LLVM_DEBUG(dbgs() << "  Operand mapping:\n");
192   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
193     // We've already handled constant values. Just map instruction operands
194     // here.
195     if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
196       continue;
197     StringMap<unsigned>::iterator SourceOp =
198       SourceOperands.find(Dag->getArgNameStr(i));
199     if (SourceOp == SourceOperands.end()) {
200       PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
201                       "', output operand '" + Dag->getArgNameStr(i) +
202                       "' has no matching source operand");
203       PrintFatalNote(Rec->getValue("ResultInst"),
204                      "Value was assigned at the following location:");
205     }
206     // Map the source operand to the destination operand index for each
207     // MachineInstr operand.
208     for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
209       OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
210         SourceOp->getValue();
211 
212     LLVM_DEBUG(dbgs() << "    " << SourceOp->getValue() << " ==> " << i
213                       << "\n");
214   }
215 
216   Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
217 }
218 
219 void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
220   // Emit file header.
221   emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
222 
223   o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
224     << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
225     << "                            const MachineInstr *MI) {\n";
226 
227   if (!Expansions.empty()) {
228     o << "  switch (MI->getOpcode()) {\n"
229       << "  default: return false;\n";
230     for (auto &Expansion : Expansions) {
231       CodeGenInstruction &Source = Expansion.Source;
232       CodeGenInstruction &Dest = Expansion.Dest;
233       o << "  case " << Source.Namespace << "::"
234         << Source.TheDef->getName() << ": {\n"
235         << "    MCInst TmpInst;\n"
236         << "    MCOperand MCOp;\n"
237         << "    TmpInst.setOpcode(" << Dest.Namespace << "::"
238         << Dest.TheDef->getName() << ");\n";
239 
240       // Copy the operands from the source instruction.
241       // FIXME: Instruction operands with defaults values (predicates and cc_out
242       //        in ARM, for example shouldn't need explicit values in the
243       //        expansion DAG.
244       unsigned MIOpNo = 0;
245       for (const auto &DestOperand : Dest.Operands) {
246         o << "    // Operand: " << DestOperand.Name << "\n";
247         for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
248           switch (Expansion.OperandMap[MIOpNo + i].Kind) {
249             case OpData::Operand:
250             o << "    lowerOperand(MI->getOperand("
251               << Source.Operands[Expansion.OperandMap[MIOpNo].Data
252               .Operand].MIOperandNo + i
253               << "), MCOp);\n"
254               << "    TmpInst.addOperand(MCOp);\n";
255             break;
256             case OpData::Imm:
257             o << "    TmpInst.addOperand(MCOperand::createImm("
258               << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
259             break;
260             case OpData::Reg: {
261               Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
262               o << "    TmpInst.addOperand(MCOperand::createReg(";
263               // "zero_reg" is special.
264               if (Reg->getName() == "zero_reg")
265                 o << "0";
266               else
267                 o << Reg->getValueAsString("Namespace") << "::"
268                   << Reg->getName();
269               o << "));\n";
270               break;
271             }
272           }
273         }
274         MIOpNo += DestOperand.MINumOperands;
275       }
276       if (Dest.Operands.isVariadic) {
277         MIOpNo = Source.Operands.size() + 1;
278         o << "    // variable_ops\n";
279         o << "    for (unsigned i = " << MIOpNo
280           << ", e = MI->getNumOperands(); i != e; ++i)\n"
281           << "      if (lowerOperand(MI->getOperand(i), MCOp))\n"
282           << "        TmpInst.addOperand(MCOp);\n";
283       }
284       o << "    EmitToStreamer(OutStreamer, TmpInst);\n"
285         << "    break;\n"
286         << "  }\n";
287     }
288     o << "  }\n  return true;";
289   } else
290     o << "  return false;";
291 
292   o << "\n}\n\n";
293 }
294 
295 void PseudoLoweringEmitter::run(raw_ostream &o) {
296   StringRef Classes[] = {"PseudoInstExpansion", "Instruction"};
297   std::vector<Record *> Insts =
298       Records.getAllDerivedDefinitions(makeArrayRef(Classes));
299 
300   // Process the pseudo expansion definitions, validating them as we do so.
301   Records.startTimer("Process definitions");
302   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
303     evaluateExpansion(Insts[i]);
304 
305   // Generate expansion code to lower the pseudo to an MCInst of the real
306   // instruction.
307   Records.startTimer("Emit expansion code");
308   emitLoweringEmitter(o);
309 }
310 
311 namespace llvm {
312 
313 void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
314   PseudoLoweringEmitter(RK).run(OS);
315 }
316 
317 } // End llvm namespace
318