1 //===- RegisterBankEmitter.cpp - Generate a Register Bank Desc. -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This tablegen backend is responsible for emitting a description of a target
10 // register bank for a code generator.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "CodeGenRegisters.h"
15 #include "CodeGenTarget.h"
16 #include "InfoByHwMode.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/TableGen/Error.h"
20 #include "llvm/TableGen/Record.h"
21 #include "llvm/TableGen/TableGenBackend.h"
22 
23 #define DEBUG_TYPE "register-bank-emitter"
24 
25 using namespace llvm;
26 
27 namespace {
28 class RegisterBank {
29 
30   /// A vector of register classes that are included in the register bank.
31   typedef std::vector<const CodeGenRegisterClass *> RegisterClassesTy;
32 
33 private:
34   const Record &TheDef;
35 
36   /// The register classes that are covered by the register bank.
37   RegisterClassesTy RCs;
38 
39   /// The register class with the largest register size.
40   std::vector<const CodeGenRegisterClass *> RCsWithLargestRegSize;
41 
42 public:
43   RegisterBank(const Record &TheDef, unsigned NumModeIds)
44       : TheDef(TheDef), RCsWithLargestRegSize(NumModeIds) {}
45 
46   /// Get the human-readable name for the bank.
47   StringRef getName() const { return TheDef.getValueAsString("Name"); }
48   /// Get the name of the enumerator in the ID enumeration.
49   std::string getEnumeratorName() const { return (TheDef.getName() + "ID").str(); }
50 
51   /// Get the name of the array holding the register class coverage data;
52   std::string getCoverageArrayName() const {
53     return (TheDef.getName() + "CoverageData").str();
54   }
55 
56   /// Get the name of the global instance variable.
57   StringRef getInstanceVarName() const { return TheDef.getName(); }
58 
59   const Record &getDef() const { return TheDef; }
60 
61   /// Get the register classes listed in the RegisterBank.RegisterClasses field.
62   std::vector<const CodeGenRegisterClass *>
63   getExplicitlySpecifiedRegisterClasses(
64       const CodeGenRegBank &RegisterClassHierarchy) const {
65     std::vector<const CodeGenRegisterClass *> RCs;
66     for (const auto *RCDef : getDef().getValueAsListOfDefs("RegisterClasses"))
67       RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
68     return RCs;
69   }
70 
71   /// Add a register class to the bank without duplicates.
72   void addRegisterClass(const CodeGenRegisterClass *RC) {
73     if (llvm::is_contained(RCs, RC))
74       return;
75 
76     // FIXME? We really want the register size rather than the spill size
77     //        since the spill size may be bigger on some targets with
78     //        limited load/store instructions. However, we don't store the
79     //        register size anywhere (we could sum the sizes of the subregisters
80     //        but there may be additional bits too) and we can't derive it from
81     //        the VT's reliably due to Untyped.
82     unsigned NumModeIds = RCsWithLargestRegSize.size();
83     for (unsigned M = 0; M < NumModeIds; ++M) {
84       if (RCsWithLargestRegSize[M] == nullptr)
85         RCsWithLargestRegSize[M] = RC;
86       else if (RCsWithLargestRegSize[M]->RSI.get(M).SpillSize <
87                RC->RSI.get(M).SpillSize)
88         RCsWithLargestRegSize[M] = RC;
89       assert(RCsWithLargestRegSize[M] && "RC was nullptr?");
90     }
91 
92     RCs.emplace_back(RC);
93   }
94 
95   const CodeGenRegisterClass *getRCWithLargestRegSize(unsigned HwMode) const {
96     return RCsWithLargestRegSize[HwMode];
97   }
98 
99   iterator_range<typename RegisterClassesTy::const_iterator>
100   register_classes() const {
101     return llvm::make_range(RCs.begin(), RCs.end());
102   }
103 };
104 
105 class RegisterBankEmitter {
106 private:
107   CodeGenTarget Target;
108   RecordKeeper &Records;
109 
110   void emitHeader(raw_ostream &OS, const StringRef TargetName,
111                   const std::vector<RegisterBank> &Banks);
112   void emitBaseClassDefinition(raw_ostream &OS, const StringRef TargetName,
113                                const std::vector<RegisterBank> &Banks);
114   void emitBaseClassImplementation(raw_ostream &OS, const StringRef TargetName,
115                                    std::vector<RegisterBank> &Banks);
116 
117 public:
118   RegisterBankEmitter(RecordKeeper &R) : Target(R), Records(R) {}
119 
120   void run(raw_ostream &OS);
121 };
122 
123 } // end anonymous namespace
124 
125 /// Emit code to declare the ID enumeration and external global instance
126 /// variables.
127 void RegisterBankEmitter::emitHeader(raw_ostream &OS,
128                                      const StringRef TargetName,
129                                      const std::vector<RegisterBank> &Banks) {
130   // <Target>RegisterBankInfo.h
131   OS << "namespace llvm {\n"
132      << "namespace " << TargetName << " {\n"
133      << "enum : unsigned {\n";
134 
135   OS << "  InvalidRegBankID = ~0u,\n";
136   unsigned ID = 0;
137   for (const auto &Bank : Banks)
138     OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";
139   OS << "  NumRegisterBanks,\n"
140      << "};\n"
141      << "} // end namespace " << TargetName << "\n"
142      << "} // end namespace llvm\n";
143 }
144 
145 /// Emit declarations of the <Target>GenRegisterBankInfo class.
146 void RegisterBankEmitter::emitBaseClassDefinition(
147     raw_ostream &OS, const StringRef TargetName,
148     const std::vector<RegisterBank> &Banks) {
149   OS << "private:\n"
150      << "  static const RegisterBank *RegBanks[];\n"
151      << "  static const unsigned Sizes[];\n\n"
152      << "protected:\n"
153      << "  " << TargetName << "GenRegisterBankInfo(unsigned HwMode = 0);\n"
154      << "\n";
155 }
156 
157 /// Visit each register class belonging to the given register bank.
158 ///
159 /// A class belongs to the bank iff any of these apply:
160 /// * It is explicitly specified
161 /// * It is a subclass of a class that is a member.
162 /// * It is a class containing subregisters of the registers of a class that
163 ///   is a member. This is known as a subreg-class.
164 ///
165 /// This function must be called for each explicitly specified register class.
166 ///
167 /// \param RC The register class to search.
168 /// \param Kind A debug string containing the path the visitor took to reach RC.
169 /// \param VisitFn The action to take for each class visited. It may be called
170 ///                multiple times for a given class if there are multiple paths
171 ///                to the class.
172 static void visitRegisterBankClasses(
173     const CodeGenRegBank &RegisterClassHierarchy,
174     const CodeGenRegisterClass *RC, const Twine &Kind,
175     std::function<void(const CodeGenRegisterClass *, StringRef)> VisitFn,
176     SmallPtrSetImpl<const CodeGenRegisterClass *> &VisitedRCs) {
177 
178   // Make sure we only visit each class once to avoid infinite loops.
179   if (!VisitedRCs.insert(RC).second)
180     return;
181 
182   // Visit each explicitly named class.
183   VisitFn(RC, Kind.str());
184 
185   for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) {
186     std::string TmpKind =
187         (Kind + " (" + PossibleSubclass.getName() + ")").str();
188 
189     // Visit each subclass of an explicitly named class.
190     if (RC != &PossibleSubclass && RC->hasSubClass(&PossibleSubclass))
191       visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass,
192                                TmpKind + " " + RC->getName() + " subclass",
193                                VisitFn, VisitedRCs);
194 
195     // Visit each class that contains only subregisters of RC with a common
196     // subregister-index.
197     //
198     // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in
199     // PossibleSubclass for all registers Reg from RC using any
200     // subregister-index SubReg
201     for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
202       BitVector BV(RegisterClassHierarchy.getRegClasses().size());
203       PossibleSubclass.getSuperRegClasses(&SubIdx, BV);
204       if (BV.test(RC->EnumValue)) {
205         std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +
206                                 " class-with-subregs: " + RC->getName())
207                                    .str();
208         VisitFn(&PossibleSubclass, TmpKind2);
209       }
210     }
211   }
212 }
213 
214 void RegisterBankEmitter::emitBaseClassImplementation(
215     raw_ostream &OS, StringRef TargetName,
216     std::vector<RegisterBank> &Banks) {
217   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
218   const CodeGenHwModes &CGH = Target.getHwModes();
219 
220   OS << "namespace llvm {\n"
221      << "namespace " << TargetName << " {\n";
222   for (const auto &Bank : Banks) {
223     std::vector<std::vector<const CodeGenRegisterClass *>> RCsGroupedByWord(
224         (RegisterClassHierarchy.getRegClasses().size() + 31) / 32);
225 
226     for (const auto &RC : Bank.register_classes())
227       RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);
228 
229     OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
230     unsigned LowestIdxInWord = 0;
231     for (const auto &RCs : RCsGroupedByWord) {
232       OS << "    // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
233       for (const auto &RC : RCs) {
234         std::string QualifiedRegClassID =
235             (Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
236         OS << "    (1u << (" << QualifiedRegClassID << " - "
237            << LowestIdxInWord << ")) |\n";
238       }
239       OS << "    0,\n";
240       LowestIdxInWord += 32;
241     }
242     OS << "};\n";
243   }
244   OS << "\n";
245 
246   for (const auto &Bank : Banks) {
247     std::string QualifiedBankID =
248         (TargetName + "::" + Bank.getEnumeratorName()).str();
249     OS << "const RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ "
250        << QualifiedBankID << ", /* Name */ \"" << Bank.getName() << "\", "
251        << "/* CoveredRegClasses */ " << Bank.getCoverageArrayName()
252        << ", /* NumRegClasses */ "
253        << RegisterClassHierarchy.getRegClasses().size() << ");\n";
254   }
255   OS << "} // end namespace " << TargetName << "\n"
256      << "\n";
257 
258   OS << "const RegisterBank *" << TargetName
259      << "GenRegisterBankInfo::RegBanks[] = {\n";
260   for (const auto &Bank : Banks)
261     OS << "    &" << TargetName << "::" << Bank.getInstanceVarName() << ",\n";
262   OS << "};\n\n";
263 
264   unsigned NumModeIds = CGH.getNumModeIds();
265   OS << "const unsigned " << TargetName << "GenRegisterBankInfo::Sizes[] = {\n";
266   for (unsigned M = 0; M < NumModeIds; ++M) {
267     OS << "    // Mode = " << M << " (";
268     if (M == DefaultMode)
269       OS << "Default";
270     else
271       OS << CGH.getMode(M).Name;
272     OS << ")\n";
273     for (const auto &Bank : Banks) {
274       const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegSize(M);
275       unsigned Size = RC.RSI.get(M).SpillSize;
276       OS << "    " << Size << ",\n";
277     }
278   }
279   OS << "};\n\n";
280 
281   OS << TargetName << "GenRegisterBankInfo::" << TargetName
282      << "GenRegisterBankInfo(unsigned HwMode)\n"
283      << "    : RegisterBankInfo(RegBanks, " << TargetName
284      << "::NumRegisterBanks, Sizes, HwMode) {\n"
285      << "  // Assert that RegBank indices match their ID's\n"
286      << "#ifndef NDEBUG\n"
287      << "  for (auto RB : enumerate(RegBanks))\n"
288      << "    assert(RB.index() == RB.value()->getID() && \"Index != ID\");\n"
289      << "#endif // NDEBUG\n"
290      << "}\n"
291      << "} // end namespace llvm\n";
292 }
293 
294 void RegisterBankEmitter::run(raw_ostream &OS) {
295   StringRef TargetName = Target.getName();
296   const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank();
297   const CodeGenHwModes &CGH = Target.getHwModes();
298 
299   Records.startTimer("Analyze records");
300   std::vector<RegisterBank> Banks;
301   for (const auto &V : Records.getAllDerivedDefinitions("RegisterBank")) {
302     SmallPtrSet<const CodeGenRegisterClass *, 8> VisitedRCs;
303     RegisterBank Bank(*V, CGH.getNumModeIds());
304 
305     for (const CodeGenRegisterClass *RC :
306          Bank.getExplicitlySpecifiedRegisterClasses(RegisterClassHierarchy)) {
307       visitRegisterBankClasses(
308           RegisterClassHierarchy, RC, "explicit",
309           [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) {
310             LLVM_DEBUG(dbgs()
311                        << "Added " << RC->getName() << "(" << Kind << ")\n");
312             Bank.addRegisterClass(RC);
313           },
314           VisitedRCs);
315     }
316 
317     Banks.push_back(Bank);
318   }
319 
320   // Warn about ambiguous MIR caused by register bank/class name clashes.
321   Records.startTimer("Warn ambiguous");
322   for (const auto &Class : RegisterClassHierarchy.getRegClasses()) {
323     for (const auto &Bank : Banks) {
324       if (Bank.getName().lower() == StringRef(Class.getName()).lower()) {
325         PrintWarning(Bank.getDef().getLoc(), "Register bank names should be "
326                                              "distinct from register classes "
327                                              "to avoid ambiguous MIR");
328         PrintNote(Bank.getDef().getLoc(), "RegisterBank was declared here");
329         PrintNote(Class.getDef()->getLoc(), "RegisterClass was declared here");
330       }
331     }
332   }
333 
334   Records.startTimer("Emit output");
335   emitSourceFileHeader("Register Bank Source Fragments", OS);
336   OS << "#ifdef GET_REGBANK_DECLARATIONS\n"
337      << "#undef GET_REGBANK_DECLARATIONS\n";
338   emitHeader(OS, TargetName, Banks);
339   OS << "#endif // GET_REGBANK_DECLARATIONS\n\n"
340      << "#ifdef GET_TARGET_REGBANK_CLASS\n"
341      << "#undef GET_TARGET_REGBANK_CLASS\n";
342   emitBaseClassDefinition(OS, TargetName, Banks);
343   OS << "#endif // GET_TARGET_REGBANK_CLASS\n\n"
344      << "#ifdef GET_TARGET_REGBANK_IMPL\n"
345      << "#undef GET_TARGET_REGBANK_IMPL\n";
346   emitBaseClassImplementation(OS, TargetName, Banks);
347   OS << "#endif // GET_TARGET_REGBANK_IMPL\n";
348 }
349 
350 static TableGen::Emitter::OptClass<RegisterBankEmitter>
351     X("gen-register-bank", "Generate registers bank descriptions");
352