1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend is responsible for emitting a description of a target 10 // register file for a code generator. It uses instances of the Register, 11 // RegisterAliases, and RegisterClass classes to gather this information. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "CodeGenRegisters.h" 16 #include "CodeGenTarget.h" 17 #include "SequenceToOffsetTable.h" 18 #include "Types.h" 19 #include "llvm/ADT/ArrayRef.h" 20 #include "llvm/ADT/BitVector.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/SetVector.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/ADT/SparseBitVector.h" 25 #include "llvm/ADT/Twine.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/Format.h" 29 #include "llvm/Support/MachineValueType.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/TableGen/Error.h" 32 #include "llvm/TableGen/Record.h" 33 #include "llvm/TableGen/SetTheory.h" 34 #include "llvm/TableGen/TableGenBackend.h" 35 #include <algorithm> 36 #include <cassert> 37 #include <cstddef> 38 #include <cstdint> 39 #include <deque> 40 #include <iterator> 41 #include <set> 42 #include <string> 43 #include <vector> 44 45 using namespace llvm; 46 47 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 48 49 static cl::opt<bool> 50 RegisterInfoDebug("register-info-debug", cl::init(false), 51 cl::desc("Dump register information to help debugging"), 52 cl::cat(RegisterInfoCat)); 53 54 namespace { 55 56 class RegisterInfoEmitter { 57 CodeGenTarget Target; 58 RecordKeeper &Records; 59 60 public: 61 RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 62 CodeGenRegBank &RegBank = Target.getRegBank(); 63 RegBank.computeDerivedInfo(); 64 } 65 66 // runEnums - Print out enum values for all of the registers. 67 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 68 69 // runMCDesc - Print out MC register descriptions. 70 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 71 72 // runTargetHeader - Emit a header fragment for the register info emitter. 73 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 74 CodeGenRegBank &Bank); 75 76 // runTargetDesc - Output the target register and register file descriptions. 77 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 78 CodeGenRegBank &Bank); 79 80 // run - Output the register file description. 81 void run(raw_ostream &o); 82 83 void debugDump(raw_ostream &OS); 84 85 private: 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 87 bool isCtor); 88 void EmitRegMappingTables(raw_ostream &o, 89 const std::deque<CodeGenRegister> &Regs, 90 bool isCtor); 91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 92 const std::string &ClassName); 93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 94 const std::string &ClassName); 95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 96 const std::string &ClassName); 97 }; 98 99 } // end anonymous namespace 100 101 // runEnums - Print out enum values for all of the registers. 102 void RegisterInfoEmitter::runEnums(raw_ostream &OS, 103 CodeGenTarget &Target, CodeGenRegBank &Bank) { 104 const auto &Registers = Bank.getRegisters(); 105 106 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 108 109 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 110 111 emitSourceFileHeader("Target Register Enum Values", OS); 112 113 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 114 OS << "#undef GET_REGINFO_ENUM\n\n"; 115 116 OS << "namespace llvm {\n\n"; 117 118 OS << "class MCRegisterClass;\n" 119 << "extern const MCRegisterClass " << Target.getName() 120 << "MCRegisterClasses[];\n\n"; 121 122 if (!Namespace.empty()) 123 OS << "namespace " << Namespace << " {\n"; 124 OS << "enum {\n NoRegister,\n"; 125 126 for (const auto &Reg : Registers) 127 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 128 assert(Registers.size() == Registers.back().EnumValue && 129 "Register enum value mismatch!"); 130 OS << " NUM_TARGET_REGS // " << Registers.size()+1 << "\n"; 131 OS << "};\n"; 132 if (!Namespace.empty()) 133 OS << "} // end namespace " << Namespace << "\n"; 134 135 const auto &RegisterClasses = Bank.getRegClasses(); 136 if (!RegisterClasses.empty()) { 137 138 // RegisterClass enums are stored as uint16_t in the tables. 139 assert(RegisterClasses.size() <= 0xffff && 140 "Too many register classes to fit in tables"); 141 142 OS << "\n// Register classes\n\n"; 143 if (!Namespace.empty()) 144 OS << "namespace " << Namespace << " {\n"; 145 OS << "enum {\n"; 146 for (const auto &RC : RegisterClasses) 147 OS << " " << RC.getName() << "RegClassID" 148 << " = " << RC.EnumValue << ",\n"; 149 OS << "\n};\n"; 150 if (!Namespace.empty()) 151 OS << "} // end namespace " << Namespace << "\n\n"; 152 } 153 154 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 155 // If the only definition is the default NoRegAltName, we don't need to 156 // emit anything. 157 if (RegAltNameIndices.size() > 1) { 158 OS << "\n// Register alternate name indices\n\n"; 159 if (!Namespace.empty()) 160 OS << "namespace " << Namespace << " {\n"; 161 OS << "enum {\n"; 162 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 163 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 164 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 165 OS << "};\n"; 166 if (!Namespace.empty()) 167 OS << "} // end namespace " << Namespace << "\n\n"; 168 } 169 170 auto &SubRegIndices = Bank.getSubRegIndices(); 171 if (!SubRegIndices.empty()) { 172 OS << "\n// Subregister indices\n\n"; 173 std::string Namespace = SubRegIndices.front().getNamespace(); 174 if (!Namespace.empty()) 175 OS << "namespace " << Namespace << " {\n"; 176 OS << "enum : uint16_t {\n NoSubRegister,\n"; 177 unsigned i = 0; 178 for (const auto &Idx : SubRegIndices) 179 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 180 OS << " NUM_TARGET_SUBREGS\n};\n"; 181 if (!Namespace.empty()) 182 OS << "} // end namespace " << Namespace << "\n\n"; 183 } 184 185 OS << "// Register pressure sets enum.\n"; 186 if (!Namespace.empty()) 187 OS << "namespace " << Namespace << " {\n"; 188 OS << "enum RegisterPressureSets {\n"; 189 unsigned NumSets = Bank.getNumRegPressureSets(); 190 for (unsigned i = 0; i < NumSets; ++i ) { 191 const RegUnitSet &RegUnits = Bank.getRegSetAt(i); 192 OS << " " << RegUnits.Name << " = " << i << ",\n"; 193 } 194 OS << "};\n"; 195 if (!Namespace.empty()) 196 OS << "} // end namespace " << Namespace << '\n'; 197 OS << '\n'; 198 199 OS << "} // end namespace llvm\n\n"; 200 OS << "#endif // GET_REGINFO_ENUM\n\n"; 201 } 202 203 static void printInt(raw_ostream &OS, int Val) { 204 OS << Val; 205 } 206 207 void RegisterInfoEmitter:: 208 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 209 const std::string &ClassName) { 210 unsigned NumRCs = RegBank.getRegClasses().size(); 211 unsigned NumSets = RegBank.getNumRegPressureSets(); 212 213 OS << "/// Get the weight in units of pressure for this register class.\n" 214 << "const RegClassWeight &" << ClassName << "::\n" 215 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 216 << " static const RegClassWeight RCWeightTable[] = {\n"; 217 for (const auto &RC : RegBank.getRegClasses()) { 218 const CodeGenRegister::Vec &Regs = RC.getMembers(); 219 OS << " {" << RC.getWeight(RegBank) << ", "; 220 if (Regs.empty() || RC.Artificial) 221 OS << '0'; 222 else { 223 std::vector<unsigned> RegUnits; 224 RC.buildRegUnitSet(RegBank, RegUnits); 225 OS << RegBank.getRegUnitSetWeight(RegUnits); 226 } 227 OS << "}, \t// " << RC.getName() << "\n"; 228 } 229 OS << " };\n" 230 << " return RCWeightTable[RC->getID()];\n" 231 << "}\n\n"; 232 233 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 234 // bother generating a table. 235 bool RegUnitsHaveUnitWeight = true; 236 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 237 UnitIdx < UnitEnd; ++UnitIdx) { 238 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 239 RegUnitsHaveUnitWeight = false; 240 } 241 OS << "/// Get the weight in units of pressure for this register unit.\n" 242 << "unsigned " << ClassName << "::\n" 243 << "getRegUnitWeight(unsigned RegUnit) const {\n" 244 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 245 << " && \"invalid register unit\");\n"; 246 if (!RegUnitsHaveUnitWeight) { 247 OS << " static const uint8_t RUWeightTable[] = {\n "; 248 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 249 UnitIdx < UnitEnd; ++UnitIdx) { 250 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 251 assert(RU.Weight < 256 && "RegUnit too heavy"); 252 OS << RU.Weight << ", "; 253 } 254 OS << "};\n" 255 << " return RUWeightTable[RegUnit];\n"; 256 } 257 else { 258 OS << " // All register units have unit weight.\n" 259 << " return 1;\n"; 260 } 261 OS << "}\n\n"; 262 263 OS << "\n" 264 << "// Get the number of dimensions of register pressure.\n" 265 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 266 << " return " << NumSets << ";\n}\n\n"; 267 268 OS << "// Get the name of this register unit pressure set.\n" 269 << "const char *" << ClassName << "::\n" 270 << "getRegPressureSetName(unsigned Idx) const {\n" 271 << " static const char *PressureNameTable[] = {\n"; 272 unsigned MaxRegUnitWeight = 0; 273 for (unsigned i = 0; i < NumSets; ++i ) { 274 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 275 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 276 OS << " \"" << RegUnits.Name << "\",\n"; 277 } 278 OS << " };\n" 279 << " return PressureNameTable[Idx];\n" 280 << "}\n\n"; 281 282 OS << "// Get the register unit pressure limit for this dimension.\n" 283 << "// This limit must be adjusted dynamically for reserved registers.\n" 284 << "unsigned " << ClassName << "::\n" 285 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 286 "{\n" 287 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 288 << " PressureLimitTable[] = {\n"; 289 for (unsigned i = 0; i < NumSets; ++i ) { 290 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 291 OS << " " << RegUnits.Weight << ", \t// " << i << ": " 292 << RegUnits.Name << "\n"; 293 } 294 OS << " };\n" 295 << " return PressureLimitTable[Idx];\n" 296 << "}\n\n"; 297 298 SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 299 300 // This table may be larger than NumRCs if some register units needed a list 301 // of unit sets that did not correspond to a register class. 302 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 303 std::vector<std::vector<int>> PSets(NumRCUnitSets); 304 305 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 306 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 307 PSets[i].reserve(PSetIDs.size()); 308 for (unsigned PSetID : PSetIDs) { 309 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order); 310 } 311 llvm::sort(PSets[i]); 312 PSetsSeqs.add(PSets[i]); 313 } 314 315 PSetsSeqs.layout(); 316 317 OS << "/// Table of pressure sets per register class or unit.\n" 318 << "static const int RCSetsTable[] = {\n"; 319 PSetsSeqs.emit(OS, printInt, "-1"); 320 OS << "};\n\n"; 321 322 OS << "/// Get the dimensions of register pressure impacted by this " 323 << "register class.\n" 324 << "/// Returns a -1 terminated array of pressure set IDs\n" 325 << "const int *" << ClassName << "::\n" 326 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 327 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 328 << " RCSetStartTable[] = {\n "; 329 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 330 OS << PSetsSeqs.get(PSets[i]) << ","; 331 } 332 OS << "};\n" 333 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 334 << "}\n\n"; 335 336 OS << "/// Get the dimensions of register pressure impacted by this " 337 << "register unit.\n" 338 << "/// Returns a -1 terminated array of pressure set IDs\n" 339 << "const int *" << ClassName << "::\n" 340 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 341 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 342 << " && \"invalid register unit\");\n"; 343 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 344 << " RUSetStartTable[] = {\n "; 345 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 346 UnitIdx < UnitEnd; ++UnitIdx) { 347 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 348 << ","; 349 } 350 OS << "};\n" 351 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 352 << "}\n\n"; 353 } 354 355 using DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>; 356 using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 357 358 static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 359 // Sort and unique to get a map-like vector. We want the last assignment to 360 // match previous behaviour. 361 llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>()); 362 // Warn about duplicate assignments. 363 const Record *LastSeenReg = nullptr; 364 for (const auto &X : DwarfRegNums) { 365 const auto &Reg = X.first; 366 // The only way LessRecordRegister can return equal is if they're the same 367 // string. Use simple equality instead. 368 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 369 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 370 getQualifiedName(Reg) + 371 "specified multiple times"); 372 LastSeenReg = Reg; 373 } 374 auto Last = std::unique( 375 DwarfRegNums.begin(), DwarfRegNums.end(), 376 [](const DwarfRegNumsMapPair &A, const DwarfRegNumsMapPair &B) { 377 return A.first->getName() == B.first->getName(); 378 }); 379 DwarfRegNums.erase(Last, DwarfRegNums.end()); 380 } 381 382 void RegisterInfoEmitter::EmitRegMappingTables( 383 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 384 // Collect all information about dwarf register numbers 385 DwarfRegNumsVecTy DwarfRegNums; 386 387 // First, just pull all provided information to the map 388 unsigned maxLength = 0; 389 for (auto &RE : Regs) { 390 Record *Reg = RE.TheDef; 391 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 392 maxLength = std::max((size_t)maxLength, RegNums.size()); 393 DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 394 } 395 finalizeDwarfRegNumsKeys(DwarfRegNums); 396 397 if (!maxLength) 398 return; 399 400 // Now we know maximal length of number list. Append -1's, where needed 401 for (auto &DwarfRegNum : DwarfRegNums) 402 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) 403 DwarfRegNum.second.push_back(-1); 404 405 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 406 407 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 408 409 // Emit reverse information about the dwarf register numbers. 410 for (unsigned j = 0; j < 2; ++j) { 411 for (unsigned I = 0, E = maxLength; I != E; ++I) { 412 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 413 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 414 OS << I << "Dwarf2L[]"; 415 416 if (!isCtor) { 417 OS << " = {\n"; 418 419 // Store the mapping sorted by the LLVM reg num so lookup can be done 420 // with a binary search. 421 std::map<uint64_t, Record*> Dwarf2LMap; 422 for (auto &DwarfRegNum : DwarfRegNums) { 423 int DwarfRegNo = DwarfRegNum.second[I]; 424 if (DwarfRegNo < 0) 425 continue; 426 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; 427 } 428 429 for (auto &I : Dwarf2LMap) 430 OS << " { " << I.first << "U, " << getQualifiedName(I.second) 431 << " },\n"; 432 433 OS << "};\n"; 434 } else { 435 OS << ";\n"; 436 } 437 438 // We have to store the size in a const global, it's used in multiple 439 // places. 440 OS << "extern const unsigned " << Namespace 441 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize"; 442 if (!isCtor) 443 OS << " = array_lengthof(" << Namespace 444 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n"; 445 else 446 OS << ";\n\n"; 447 } 448 } 449 450 for (auto &RE : Regs) { 451 Record *Reg = RE.TheDef; 452 const RecordVal *V = Reg->getValue("DwarfAlias"); 453 if (!V || !V->getValue()) 454 continue; 455 456 DefInit *DI = cast<DefInit>(V->getValue()); 457 Record *Alias = DI->getDef(); 458 const auto &AliasIter = llvm::lower_bound( 459 DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) { 460 return LessRecordRegister()(A.first, B); 461 }); 462 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 463 "Expected Alias to be present in map"); 464 const auto &RegIter = llvm::lower_bound( 465 DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) { 466 return LessRecordRegister()(A.first, B); 467 }); 468 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 469 "Expected Reg to be present in map"); 470 RegIter->second = AliasIter->second; 471 } 472 473 // Emit information about the dwarf register numbers. 474 for (unsigned j = 0; j < 2; ++j) { 475 for (unsigned i = 0, e = maxLength; i != e; ++i) { 476 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 477 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 478 OS << i << "L2Dwarf[]"; 479 if (!isCtor) { 480 OS << " = {\n"; 481 // Store the mapping sorted by the Dwarf reg num so lookup can be done 482 // with a binary search. 483 for (auto &DwarfRegNum : DwarfRegNums) { 484 int RegNo = DwarfRegNum.second[i]; 485 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 486 continue; 487 488 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo 489 << "U },\n"; 490 } 491 OS << "};\n"; 492 } else { 493 OS << ";\n"; 494 } 495 496 // We have to store the size in a const global, it's used in multiple 497 // places. 498 OS << "extern const unsigned " << Namespace 499 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 500 if (!isCtor) 501 OS << " = array_lengthof(" << Namespace 502 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 503 else 504 OS << ";\n\n"; 505 } 506 } 507 } 508 509 void RegisterInfoEmitter::EmitRegMapping( 510 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 511 // Emit the initializer so the tables from EmitRegMappingTables get wired up 512 // to the MCRegisterInfo object. 513 unsigned maxLength = 0; 514 for (auto &RE : Regs) { 515 Record *Reg = RE.TheDef; 516 maxLength = std::max((size_t)maxLength, 517 Reg->getValueAsListOfInts("DwarfNumbers").size()); 518 } 519 520 if (!maxLength) 521 return; 522 523 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 524 525 // Emit reverse information about the dwarf register numbers. 526 for (unsigned j = 0; j < 2; ++j) { 527 OS << " switch ("; 528 if (j == 0) 529 OS << "DwarfFlavour"; 530 else 531 OS << "EHFlavour"; 532 OS << ") {\n" 533 << " default:\n" 534 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 535 536 for (unsigned i = 0, e = maxLength; i != e; ++i) { 537 OS << " case " << i << ":\n"; 538 OS << " "; 539 if (!isCtor) 540 OS << "RI->"; 541 std::string Tmp; 542 raw_string_ostream(Tmp) << Namespace 543 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 544 << "Dwarf2L"; 545 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 546 if (j == 0) 547 OS << "false"; 548 else 549 OS << "true"; 550 OS << ");\n"; 551 OS << " break;\n"; 552 } 553 OS << " }\n"; 554 } 555 556 // Emit information about the dwarf register numbers. 557 for (unsigned j = 0; j < 2; ++j) { 558 OS << " switch ("; 559 if (j == 0) 560 OS << "DwarfFlavour"; 561 else 562 OS << "EHFlavour"; 563 OS << ") {\n" 564 << " default:\n" 565 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 566 567 for (unsigned i = 0, e = maxLength; i != e; ++i) { 568 OS << " case " << i << ":\n"; 569 OS << " "; 570 if (!isCtor) 571 OS << "RI->"; 572 std::string Tmp; 573 raw_string_ostream(Tmp) << Namespace 574 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 575 << "L2Dwarf"; 576 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 577 if (j == 0) 578 OS << "false"; 579 else 580 OS << "true"; 581 OS << ");\n"; 582 OS << " break;\n"; 583 } 584 OS << " }\n"; 585 } 586 } 587 588 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 589 // Width is the number of bits per hex number. 590 static void printBitVectorAsHex(raw_ostream &OS, 591 const BitVector &Bits, 592 unsigned Width) { 593 assert(Width <= 32 && "Width too large"); 594 unsigned Digits = (Width + 3) / 4; 595 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 596 unsigned Value = 0; 597 for (unsigned j = 0; j != Width && i + j != e; ++j) 598 Value |= Bits.test(i + j) << j; 599 OS << format("0x%0*x, ", Digits, Value); 600 } 601 } 602 603 // Helper to emit a set of bits into a constant byte array. 604 class BitVectorEmitter { 605 BitVector Values; 606 public: 607 void add(unsigned v) { 608 if (v >= Values.size()) 609 Values.resize(((v/8)+1)*8); // Round up to the next byte. 610 Values[v] = true; 611 } 612 613 void print(raw_ostream &OS) { 614 printBitVectorAsHex(OS, Values, 8); 615 } 616 }; 617 618 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 619 OS << getEnumName(VT); 620 } 621 622 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 623 OS << Idx->EnumValue; 624 } 625 626 // Differentially encoded register and regunit lists allow for better 627 // compression on regular register banks. The sequence is computed from the 628 // differential list as: 629 // 630 // out[0] = InitVal; 631 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 632 // 633 // The initial value depends on the specific list. The list is terminated by a 634 // 0 differential which means we can't encode repeated elements. 635 636 typedef SmallVector<uint16_t, 4> DiffVec; 637 typedef SmallVector<LaneBitmask, 4> MaskVec; 638 639 // Differentially encode a sequence of numbers into V. The starting value and 640 // terminating 0 are not added to V, so it will have the same size as List. 641 static 642 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 643 assert(V.empty() && "Clear DiffVec before diffEncode."); 644 uint16_t Val = uint16_t(InitVal); 645 646 for (uint16_t Cur : List) { 647 V.push_back(Cur - Val); 648 Val = Cur; 649 } 650 return V; 651 } 652 653 template<typename Iter> 654 static 655 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 656 assert(V.empty() && "Clear DiffVec before diffEncode."); 657 uint16_t Val = uint16_t(InitVal); 658 for (Iter I = Begin; I != End; ++I) { 659 uint16_t Cur = (*I)->EnumValue; 660 V.push_back(Cur - Val); 661 Val = Cur; 662 } 663 return V; 664 } 665 666 static void printDiff16(raw_ostream &OS, uint16_t Val) { 667 OS << Val; 668 } 669 670 static void printMask(raw_ostream &OS, LaneBitmask Val) { 671 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 672 } 673 674 // Try to combine Idx's compose map into Vec if it is compatible. 675 // Return false if it's not possible. 676 static bool combine(const CodeGenSubRegIndex *Idx, 677 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 678 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 679 for (const auto &I : Map) { 680 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 681 if (Entry && Entry != I.second) 682 return false; 683 } 684 685 // All entries are compatible. Make it so. 686 for (const auto &I : Map) { 687 auto *&Entry = Vec[I.first->EnumValue - 1]; 688 assert((!Entry || Entry == I.second) && 689 "Expected EnumValue to be unique"); 690 Entry = I.second; 691 } 692 return true; 693 } 694 695 void 696 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 697 CodeGenRegBank &RegBank, 698 const std::string &ClName) { 699 const auto &SubRegIndices = RegBank.getSubRegIndices(); 700 OS << "unsigned " << ClName 701 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 702 703 // Many sub-register indexes are composition-compatible, meaning that 704 // 705 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 706 // 707 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 708 // The illegal entries can be use as wildcards to compress the table further. 709 710 // Map each Sub-register index to a compatible table row. 711 SmallVector<unsigned, 4> RowMap; 712 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 713 714 auto SubRegIndicesSize = 715 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 716 for (const auto &Idx : SubRegIndices) { 717 unsigned Found = ~0u; 718 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 719 if (combine(&Idx, Rows[r])) { 720 Found = r; 721 break; 722 } 723 } 724 if (Found == ~0u) { 725 Found = Rows.size(); 726 Rows.resize(Found + 1); 727 Rows.back().resize(SubRegIndicesSize); 728 combine(&Idx, Rows.back()); 729 } 730 RowMap.push_back(Found); 731 } 732 733 // Output the row map if there is multiple rows. 734 if (Rows.size() > 1) { 735 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 736 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 737 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 738 OS << RowMap[i] << ", "; 739 OS << "\n };\n"; 740 } 741 742 // Output the rows. 743 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 744 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 745 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 746 OS << " { "; 747 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 748 if (Rows[r][i]) 749 OS << Rows[r][i]->getQualifiedName() << ", "; 750 else 751 OS << "0, "; 752 OS << "},\n"; 753 } 754 OS << " };\n\n"; 755 756 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" 757 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 758 if (Rows.size() > 1) 759 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 760 else 761 OS << " return Rows[0][IdxB];\n"; 762 OS << "}\n\n"; 763 } 764 765 void 766 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 767 CodeGenRegBank &RegBank, 768 const std::string &ClName) { 769 // See the comments in computeSubRegLaneMasks() for our goal here. 770 const auto &SubRegIndices = RegBank.getSubRegIndices(); 771 772 // Create a list of Mask+Rotate operations, with equivalent entries merged. 773 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 774 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 775 for (const auto &Idx : SubRegIndices) { 776 const SmallVector<MaskRolPair, 1> &IdxSequence 777 = Idx.CompositionLaneMaskTransform; 778 779 unsigned Found = ~0u; 780 unsigned SIdx = 0; 781 unsigned NextSIdx; 782 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 783 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 784 NextSIdx = SIdx + Sequence.size() + 1; 785 if (Sequence == IdxSequence) { 786 Found = SIdx; 787 break; 788 } 789 } 790 if (Found == ~0u) { 791 Sequences.push_back(IdxSequence); 792 Found = SIdx; 793 } 794 SubReg2SequenceIndexMap.push_back(Found); 795 } 796 797 OS << " struct MaskRolOp {\n" 798 " LaneBitmask Mask;\n" 799 " uint8_t RotateLeft;\n" 800 " };\n" 801 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 802 unsigned Idx = 0; 803 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 804 OS << " "; 805 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 806 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 807 const MaskRolPair &P = Sequence[p]; 808 printMask(OS << "{ ", P.Mask); 809 OS << format(", %2u }, ", P.RotateLeft); 810 } 811 OS << "{ LaneBitmask::getNone(), 0 }"; 812 if (s+1 != se) 813 OS << ", "; 814 OS << " // Sequence " << Idx << "\n"; 815 Idx += Sequence.size() + 1; 816 } 817 auto *IntType = getMinimalTypeForRange(*std::max_element( 818 SubReg2SequenceIndexMap.begin(), SubReg2SequenceIndexMap.end())); 819 OS << " };\n" 820 " static const " 821 << IntType << " CompositeSequences[] = {\n"; 822 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 823 OS << " "; 824 OS << SubReg2SequenceIndexMap[i]; 825 if (i+1 != e) 826 OS << ","; 827 OS << " // to " << SubRegIndices[i].getName() << "\n"; 828 } 829 OS << " };\n\n"; 830 831 OS << "LaneBitmask " << ClName 832 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 833 " const {\n" 834 " --IdxA; assert(IdxA < " << SubRegIndices.size() 835 << " && \"Subregister index out of bounds\");\n" 836 " LaneBitmask Result;\n" 837 " for (const MaskRolOp *Ops =\n" 838 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 839 " Ops->Mask.any(); ++Ops) {\n" 840 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 841 " if (unsigned S = Ops->RotateLeft)\n" 842 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 843 " else\n" 844 " Result |= LaneBitmask(M);\n" 845 " }\n" 846 " return Result;\n" 847 "}\n\n"; 848 849 OS << "LaneBitmask " << ClName 850 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 851 " LaneBitmask LaneMask) const {\n" 852 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 853 " --IdxA; assert(IdxA < " << SubRegIndices.size() 854 << " && \"Subregister index out of bounds\");\n" 855 " LaneBitmask Result;\n" 856 " for (const MaskRolOp *Ops =\n" 857 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 858 " Ops->Mask.any(); ++Ops) {\n" 859 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 860 " if (unsigned S = Ops->RotateLeft)\n" 861 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 862 " else\n" 863 " Result |= LaneBitmask(M);\n" 864 " }\n" 865 " return Result;\n" 866 "}\n\n"; 867 } 868 869 // 870 // runMCDesc - Print out MC register descriptions. 871 // 872 void 873 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 874 CodeGenRegBank &RegBank) { 875 emitSourceFileHeader("MC Register Information", OS); 876 877 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 878 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 879 880 const auto &Regs = RegBank.getRegisters(); 881 882 auto &SubRegIndices = RegBank.getSubRegIndices(); 883 // The lists of sub-registers and super-registers go in the same array. That 884 // allows us to share suffixes. 885 typedef std::vector<const CodeGenRegister*> RegVec; 886 887 // Differentially encoded lists. 888 SequenceToOffsetTable<DiffVec> DiffSeqs; 889 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 890 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 891 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 892 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 893 894 // List of lane masks accompanying register unit sequences. 895 SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 896 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 897 898 // Keep track of sub-register names as well. These are not differentially 899 // encoded. 900 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 901 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs; 902 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 903 904 SequenceToOffsetTable<std::string> RegStrings; 905 906 // Precompute register lists for the SequenceToOffsetTable. 907 unsigned i = 0; 908 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 909 const auto &Reg = *I; 910 RegStrings.add(std::string(Reg.getName())); 911 912 // Compute the ordered sub-register list. 913 SetVector<const CodeGenRegister*> SR; 914 Reg.addSubRegsPreOrder(SR, RegBank); 915 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 916 DiffSeqs.add(SubRegLists[i]); 917 918 // Compute the corresponding sub-register indexes. 919 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 920 for (const CodeGenRegister *S : SR) 921 SRIs.push_back(Reg.getSubRegIndex(S)); 922 SubRegIdxSeqs.add(SRIs); 923 924 // Super-registers are already computed. 925 const RegVec &SuperRegList = Reg.getSuperRegs(); 926 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 927 SuperRegList.end()); 928 DiffSeqs.add(SuperRegLists[i]); 929 930 // Differentially encode the register unit list, seeded by register number. 931 // First compute a scale factor that allows more diff-lists to be reused: 932 // 933 // D0 -> (S0, S1) 934 // D1 -> (S2, S3) 935 // 936 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 937 // value for the differential decoder is the register number multiplied by 938 // the scale. 939 // 940 // Check the neighboring registers for arithmetic progressions. 941 unsigned ScaleA = ~0u, ScaleB = ~0u; 942 SparseBitVector<> RUs = Reg.getNativeRegUnits(); 943 if (I != Regs.begin() && 944 std::prev(I)->getNativeRegUnits().count() == RUs.count()) 945 ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 946 if (std::next(I) != Regs.end() && 947 std::next(I)->getNativeRegUnits().count() == RUs.count()) 948 ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 949 unsigned Scale = std::min(ScaleB, ScaleA); 950 // Default the scale to 0 if it can't be encoded in 4 bits. 951 if (Scale >= 16) 952 Scale = 0; 953 RegUnitInitScale[i] = Scale; 954 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 955 956 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 957 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 958 assert(LaneMaskVec.empty()); 959 llvm::append_range(LaneMaskVec, RUMasks); 960 // Terminator mask should not be used inside of the list. 961 #ifndef NDEBUG 962 for (LaneBitmask M : LaneMaskVec) { 963 assert(!M.all() && "terminator mask should not be part of the list"); 964 } 965 #endif 966 LaneMaskSeqs.add(LaneMaskVec); 967 } 968 969 // Compute the final layout of the sequence table. 970 DiffSeqs.layout(); 971 LaneMaskSeqs.layout(); 972 SubRegIdxSeqs.layout(); 973 974 OS << "namespace llvm {\n\n"; 975 976 const std::string &TargetName = std::string(Target.getName()); 977 978 // Emit the shared table of differential lists. 979 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 980 DiffSeqs.emit(OS, printDiff16); 981 OS << "};\n\n"; 982 983 // Emit the shared table of regunit lane mask sequences. 984 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 985 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 986 OS << "};\n\n"; 987 988 // Emit the table of sub-register indexes. 989 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 990 SubRegIdxSeqs.emit(OS, printSubRegIndex); 991 OS << "};\n\n"; 992 993 // Emit the table of sub-register index sizes. 994 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 995 << TargetName << "SubRegIdxRanges[] = {\n"; 996 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 997 for (const auto &Idx : SubRegIndices) { 998 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 999 << Idx.getName() << "\n"; 1000 } 1001 OS << "};\n\n"; 1002 1003 // Emit the string table. 1004 RegStrings.layout(); 1005 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + 1006 "RegStrings[]"); 1007 1008 OS << "extern const MCRegisterDesc " << TargetName 1009 << "RegDesc[] = { // Descriptors\n"; 1010 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 1011 1012 // Emit the register descriptors now. 1013 i = 0; 1014 for (const auto &Reg : Regs) { 1015 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " 1016 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1017 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1018 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 1019 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1020 ++i; 1021 } 1022 OS << "};\n\n"; // End of register descriptors... 1023 1024 // Emit the table of register unit roots. Each regunit has one or two root 1025 // registers. 1026 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1027 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1028 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 1029 assert(!Roots.empty() && "All regunits must have a root register."); 1030 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1031 OS << " { "; 1032 ListSeparator LS; 1033 for (const CodeGenRegister *R : Roots) 1034 OS << LS << getQualifiedName(R->TheDef); 1035 OS << " },\n"; 1036 } 1037 OS << "};\n\n"; 1038 1039 const auto &RegisterClasses = RegBank.getRegClasses(); 1040 1041 // Loop over all of the register classes... emitting each one. 1042 OS << "namespace { // Register classes...\n"; 1043 1044 SequenceToOffsetTable<std::string> RegClassStrings; 1045 1046 // Emit the register enum value arrays for each RegisterClass 1047 for (const auto &RC : RegisterClasses) { 1048 ArrayRef<Record*> Order = RC.getOrder(); 1049 1050 // Give the register class a legal C name if it's anonymous. 1051 const std::string &Name = RC.getName(); 1052 1053 RegClassStrings.add(Name); 1054 1055 // Emit the register list now (unless it would be a zero-length array). 1056 if (!Order.empty()) { 1057 OS << " // " << Name << " Register Class...\n" 1058 << " const MCPhysReg " << Name << "[] = {\n "; 1059 for (Record *Reg : Order) { 1060 OS << getQualifiedName(Reg) << ", "; 1061 } 1062 OS << "\n };\n\n"; 1063 1064 OS << " // " << Name << " Bit set.\n" 1065 << " const uint8_t " << Name << "Bits[] = {\n "; 1066 BitVectorEmitter BVE; 1067 for (Record *Reg : Order) { 1068 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1069 } 1070 BVE.print(OS); 1071 OS << "\n };\n\n"; 1072 } 1073 } 1074 OS << "} // end anonymous namespace\n\n"; 1075 1076 RegClassStrings.layout(); 1077 RegClassStrings.emitStringLiteralDef( 1078 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); 1079 1080 OS << "extern const MCRegisterClass " << TargetName 1081 << "MCRegisterClasses[] = {\n"; 1082 1083 for (const auto &RC : RegisterClasses) { 1084 ArrayRef<Record *> Order = RC.getOrder(); 1085 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); 1086 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; 1087 std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")"; 1088 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1089 uint32_t RegSize = 0; 1090 if (RC.RSI.isSimple()) 1091 RegSize = RC.RSI.getSimple().RegSize; 1092 OS << " { " << RCName << ", " << RCBitsName << ", " 1093 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() 1094 << ", " << RCBitsSize << ", " << RC.getQualifiedName() + "RegClassID" 1095 << ", " << RegSize << ", " << RC.CopyCost << ", " 1096 << (RC.Allocatable ? "true" : "false") << " },\n"; 1097 } 1098 1099 OS << "};\n\n"; 1100 1101 EmitRegMappingTables(OS, Regs, false); 1102 1103 // Emit Reg encoding table 1104 OS << "extern const uint16_t " << TargetName; 1105 OS << "RegEncodingTable[] = {\n"; 1106 // Add entry for NoRegister 1107 OS << " 0,\n"; 1108 for (const auto &RE : Regs) { 1109 Record *Reg = RE.TheDef; 1110 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1111 uint64_t Value = 0; 1112 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1113 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1114 Value |= (uint64_t)B->getValue() << b; 1115 } 1116 OS << " " << Value << ",\n"; 1117 } 1118 OS << "};\n"; // End of HW encoding table 1119 1120 // MCRegisterInfo initialization routine. 1121 OS << "static inline void Init" << TargetName 1122 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1123 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1124 "{\n" 1125 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1126 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1127 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1128 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1129 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1130 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1131 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1132 << TargetName << "SubRegIdxRanges, " << TargetName 1133 << "RegEncodingTable);\n\n"; 1134 1135 EmitRegMapping(OS, Regs, false); 1136 1137 OS << "}\n\n"; 1138 1139 OS << "} // end namespace llvm\n\n"; 1140 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1141 } 1142 1143 void 1144 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1145 CodeGenRegBank &RegBank) { 1146 emitSourceFileHeader("Register Information Header Fragment", OS); 1147 1148 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1149 OS << "#undef GET_REGINFO_HEADER\n\n"; 1150 1151 const std::string &TargetName = std::string(Target.getName()); 1152 std::string ClassName = TargetName + "GenRegisterInfo"; 1153 1154 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1155 1156 OS << "namespace llvm {\n\n"; 1157 1158 OS << "class " << TargetName << "FrameLowering;\n\n"; 1159 1160 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1161 << " explicit " << ClassName 1162 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1163 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1164 if (!RegBank.getSubRegIndices().empty()) { 1165 OS << " unsigned composeSubRegIndicesImpl" 1166 << "(unsigned, unsigned) const override;\n" 1167 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1168 << "(unsigned, LaneBitmask) const override;\n" 1169 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1170 << "(unsigned, LaneBitmask) const override;\n" 1171 << " const TargetRegisterClass *getSubClassWithSubReg" 1172 << "(const TargetRegisterClass *, unsigned) const override;\n"; 1173 } 1174 OS << " const RegClassWeight &getRegClassWeight(" 1175 << "const TargetRegisterClass *RC) const override;\n" 1176 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1177 << " unsigned getNumRegPressureSets() const override;\n" 1178 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1179 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1180 "Idx) const override;\n" 1181 << " const int *getRegClassPressureSets(" 1182 << "const TargetRegisterClass *RC) const override;\n" 1183 << " const int *getRegUnitPressureSets(" 1184 << "unsigned RegUnit) const override;\n" 1185 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1186 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1187 << " bool isGeneralPurposeRegister(const MachineFunction &, " 1188 << "MCRegister) const override;\n" 1189 << " bool isFixedRegister(const MachineFunction &, " 1190 << "MCRegister) const override;\n" 1191 << " bool isArgumentRegister(const MachineFunction &, " 1192 << "MCRegister) const override;\n" 1193 << " /// Devirtualized TargetFrameLowering.\n" 1194 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1195 << " const MachineFunction &MF);\n" 1196 << "};\n\n"; 1197 1198 const auto &RegisterClasses = RegBank.getRegClasses(); 1199 1200 if (!RegisterClasses.empty()) { 1201 OS << "namespace " << RegisterClasses.front().Namespace 1202 << " { // Register classes\n"; 1203 1204 for (const auto &RC : RegisterClasses) { 1205 const std::string &Name = RC.getName(); 1206 1207 // Output the extern for the instance. 1208 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1209 } 1210 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1211 } 1212 OS << "} // end namespace llvm\n\n"; 1213 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1214 } 1215 1216 // 1217 // runTargetDesc - Output the target register and register file descriptions. 1218 // 1219 void 1220 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1221 CodeGenRegBank &RegBank){ 1222 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1223 1224 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1225 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1226 1227 OS << "namespace llvm {\n\n"; 1228 1229 // Get access to MCRegisterClass data. 1230 OS << "extern const MCRegisterClass " << Target.getName() 1231 << "MCRegisterClasses[];\n"; 1232 1233 // Start out by emitting each of the register classes. 1234 const auto &RegisterClasses = RegBank.getRegClasses(); 1235 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1236 1237 // Collect all registers belonging to any allocatable class. 1238 std::set<Record*> AllocatableRegs; 1239 1240 // Collect allocatable registers. 1241 for (const auto &RC : RegisterClasses) { 1242 ArrayRef<Record*> Order = RC.getOrder(); 1243 1244 if (RC.Allocatable) 1245 AllocatableRegs.insert(Order.begin(), Order.end()); 1246 } 1247 1248 const CodeGenHwModes &CGH = Target.getHwModes(); 1249 unsigned NumModes = CGH.getNumModeIds(); 1250 1251 // Build a shared array of value types. 1252 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1253 for (unsigned M = 0; M < NumModes; ++M) { 1254 for (const auto &RC : RegisterClasses) { 1255 std::vector<MVT::SimpleValueType> S; 1256 for (const ValueTypeByHwMode &VVT : RC.VTs) 1257 S.push_back(VVT.get(M).SimpleTy); 1258 VTSeqs.add(S); 1259 } 1260 } 1261 VTSeqs.layout(); 1262 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1263 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1264 OS << "};\n"; 1265 1266 // Emit SubRegIndex names, skipping 0. 1267 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; 1268 1269 for (const auto &Idx : SubRegIndices) { 1270 OS << Idx.getName(); 1271 OS << "\", \""; 1272 } 1273 OS << "\" };\n\n"; 1274 1275 // Emit SubRegIndex lane masks, including 0. 1276 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1277 "LaneBitmask::getAll(),\n"; 1278 for (const auto &Idx : SubRegIndices) { 1279 printMask(OS << " ", Idx.LaneMask); 1280 OS << ", // " << Idx.getName() << '\n'; 1281 } 1282 OS << " };\n\n"; 1283 1284 OS << "\n"; 1285 1286 // Now that all of the structs have been emitted, emit the instances. 1287 if (!RegisterClasses.empty()) { 1288 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1289 << " = {\n"; 1290 for (unsigned M = 0; M < NumModes; ++M) { 1291 unsigned EV = 0; 1292 OS << " // Mode = " << M << " ("; 1293 if (M == 0) 1294 OS << "Default"; 1295 else 1296 OS << CGH.getMode(M).Name; 1297 OS << ")\n"; 1298 for (const auto &RC : RegisterClasses) { 1299 assert(RC.EnumValue == EV && "Unexpected order of register classes"); 1300 ++EV; 1301 (void)EV; 1302 const RegSizeInfo &RI = RC.RSI.get(M); 1303 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1304 << RI.SpillAlignment; 1305 std::vector<MVT::SimpleValueType> VTs; 1306 for (const ValueTypeByHwMode &VVT : RC.VTs) 1307 VTs.push_back(VVT.get(M).SimpleTy); 1308 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1309 << RC.getName() << '\n'; 1310 } 1311 } 1312 OS << "};\n"; 1313 1314 1315 OS << "\nstatic const TargetRegisterClass *const " 1316 << "NullRegClasses[] = { nullptr };\n\n"; 1317 1318 // Emit register class bit mask tables. The first bit mask emitted for a 1319 // register class, RC, is the set of sub-classes, including RC itself. 1320 // 1321 // If RC has super-registers, also create a list of subreg indices and bit 1322 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1323 // SuperRC, that satisfies: 1324 // 1325 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1326 // 1327 // The 0-terminated list of subreg indices starts at: 1328 // 1329 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1330 // 1331 // The corresponding bitmasks follow the sub-class mask in memory. Each 1332 // mask has RCMaskWords uint32_t entries. 1333 // 1334 // Every bit mask present in the list has at least one bit set. 1335 1336 // Compress the sub-reg index lists. 1337 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1338 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1339 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1340 BitVector MaskBV(RegisterClasses.size()); 1341 1342 for (const auto &RC : RegisterClasses) { 1343 OS << "static const uint32_t " << RC.getName() 1344 << "SubClassMask[] = {\n "; 1345 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1346 1347 // Emit super-reg class masks for any relevant SubRegIndices that can 1348 // project into RC. 1349 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1350 for (auto &Idx : SubRegIndices) { 1351 MaskBV.reset(); 1352 RC.getSuperRegClasses(&Idx, MaskBV); 1353 if (MaskBV.none()) 1354 continue; 1355 SRIList.push_back(&Idx); 1356 OS << "\n "; 1357 printBitVectorAsHex(OS, MaskBV, 32); 1358 OS << "// " << Idx.getName(); 1359 } 1360 SuperRegIdxSeqs.add(SRIList); 1361 OS << "\n};\n\n"; 1362 } 1363 1364 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1365 SuperRegIdxSeqs.layout(); 1366 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1367 OS << "};\n\n"; 1368 1369 // Emit NULL terminated super-class lists. 1370 for (const auto &RC : RegisterClasses) { 1371 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1372 1373 // Skip classes without supers. We can reuse NullRegClasses. 1374 if (Supers.empty()) 1375 continue; 1376 1377 OS << "static const TargetRegisterClass *const " 1378 << RC.getName() << "Superclasses[] = {\n"; 1379 for (const auto *Super : Supers) 1380 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1381 OS << " nullptr\n};\n\n"; 1382 } 1383 1384 // Emit methods. 1385 for (const auto &RC : RegisterClasses) { 1386 if (!RC.AltOrderSelect.empty()) { 1387 OS << "\nstatic inline unsigned " << RC.getName() 1388 << "AltOrderSelect(const MachineFunction &MF) {" 1389 << RC.AltOrderSelect << "}\n\n" 1390 << "static ArrayRef<MCPhysReg> " << RC.getName() 1391 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1392 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1393 ArrayRef<Record*> Elems = RC.getOrder(oi); 1394 if (!Elems.empty()) { 1395 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1396 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1397 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1398 OS << " };\n"; 1399 } 1400 } 1401 OS << " const MCRegisterClass &MCR = " << Target.getName() 1402 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1403 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1404 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1405 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1406 if (RC.getOrder(oi).empty()) 1407 OS << "),\n ArrayRef<MCPhysReg>("; 1408 else 1409 OS << "),\n makeArrayRef(AltOrder" << oi; 1410 OS << ")\n };\n const unsigned Select = " << RC.getName() 1411 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1412 << ");\n return Order[Select];\n}\n"; 1413 } 1414 } 1415 1416 // Now emit the actual value-initialized register class instances. 1417 OS << "\nnamespace " << RegisterClasses.front().Namespace 1418 << " { // Register class instances\n"; 1419 1420 for (const auto &RC : RegisterClasses) { 1421 OS << " extern const TargetRegisterClass " << RC.getName() 1422 << "RegClass = {\n " << '&' << Target.getName() 1423 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1424 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1425 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1426 printMask(OS, RC.LaneMask); 1427 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1428 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n " 1429 << (RC.HasDisjunctSubRegs?"true":"false") 1430 << ", /* HasDisjunctSubRegs */\n " 1431 << (RC.CoveredBySubRegs?"true":"false") 1432 << ", /* CoveredBySubRegs */\n "; 1433 if (RC.getSuperClasses().empty()) 1434 OS << "NullRegClasses,\n "; 1435 else 1436 OS << RC.getName() << "Superclasses,\n "; 1437 if (RC.AltOrderSelect.empty()) 1438 OS << "nullptr\n"; 1439 else 1440 OS << RC.getName() << "GetRawAllocationOrder\n"; 1441 OS << " };\n\n"; 1442 } 1443 1444 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1445 } 1446 1447 OS << "\nnamespace {\n"; 1448 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; 1449 for (const auto &RC : RegisterClasses) 1450 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1451 OS << " };\n"; 1452 OS << "} // end anonymous namespace\n"; 1453 1454 // Emit extra information about registers. 1455 const std::string &TargetName = std::string(Target.getName()); 1456 const auto &Regs = RegBank.getRegisters(); 1457 unsigned NumRegCosts = 1; 1458 for (const auto &Reg : Regs) 1459 NumRegCosts = std::max((size_t)NumRegCosts, Reg.CostPerUse.size()); 1460 1461 std::vector<unsigned> AllRegCostPerUse; 1462 llvm::BitVector InAllocClass(Regs.size() + 1, false); 1463 AllRegCostPerUse.insert(AllRegCostPerUse.end(), NumRegCosts, 0); 1464 1465 // Populate the vector RegCosts with the CostPerUse list of the registers 1466 // in the order they are read. Have at most NumRegCosts entries for 1467 // each register. Fill with zero for values which are not explicitly given. 1468 for (const auto &Reg : Regs) { 1469 auto Costs = Reg.CostPerUse; 1470 AllRegCostPerUse.insert(AllRegCostPerUse.end(), Costs.begin(), Costs.end()); 1471 if (NumRegCosts > Costs.size()) 1472 AllRegCostPerUse.insert(AllRegCostPerUse.end(), 1473 NumRegCosts - Costs.size(), 0); 1474 1475 if (AllocatableRegs.count(Reg.TheDef)) 1476 InAllocClass.set(Reg.EnumValue); 1477 } 1478 1479 // Emit the cost values as a 1D-array after grouping them by their indices, 1480 // i.e. the costs for all registers corresponds to index 0, 1, 2, etc. 1481 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1). 1482 OS << "\nstatic const uint8_t " 1483 << "CostPerUseTable[] = { \n"; 1484 for (unsigned int I = 0; I < NumRegCosts; ++I) { 1485 for (unsigned J = I, E = AllRegCostPerUse.size(); J < E; J += NumRegCosts) 1486 OS << AllRegCostPerUse[J] << ", "; 1487 } 1488 OS << "};\n\n"; 1489 1490 OS << "\nstatic const bool " 1491 << "InAllocatableClassTable[] = { \n"; 1492 for (unsigned I = 0, E = InAllocClass.size(); I < E; ++I) { 1493 OS << (InAllocClass[I] ? "true" : "false") << ", "; 1494 } 1495 OS << "};\n\n"; 1496 1497 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName 1498 << "RegInfoDesc = { // Extra Descriptors\n"; 1499 OS << "CostPerUseTable, " << NumRegCosts << ", " 1500 << "InAllocatableClassTable"; 1501 OS << "};\n\n"; // End of register descriptors... 1502 1503 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1504 1505 auto SubRegIndicesSize = 1506 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1507 1508 if (!SubRegIndices.empty()) { 1509 emitComposeSubRegIndices(OS, RegBank, ClassName); 1510 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1511 } 1512 1513 // Emit getSubClassWithSubReg. 1514 if (!SubRegIndices.empty()) { 1515 OS << "const TargetRegisterClass *" << ClassName 1516 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1517 << " const {\n"; 1518 // Use the smallest type that can hold a regclass ID with room for a 1519 // sentinel. 1520 if (RegisterClasses.size() < UINT8_MAX) 1521 OS << " static const uint8_t Table["; 1522 else if (RegisterClasses.size() < UINT16_MAX) 1523 OS << " static const uint16_t Table["; 1524 else 1525 PrintFatalError("Too many register classes."); 1526 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1527 for (const auto &RC : RegisterClasses) { 1528 OS << " {\t// " << RC.getName() << "\n"; 1529 for (auto &Idx : SubRegIndices) { 1530 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1531 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1532 << " -> " << SRC->getName() << "\n"; 1533 else 1534 OS << " 0,\t// " << Idx.getName() << "\n"; 1535 } 1536 OS << " },\n"; 1537 } 1538 OS << " };\n assert(RC && \"Missing regclass\");\n" 1539 << " if (!Idx) return RC;\n --Idx;\n" 1540 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1541 << " unsigned TV = Table[RC->getID()][Idx];\n" 1542 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1543 } 1544 1545 EmitRegUnitPressure(OS, RegBank, ClassName); 1546 1547 // Emit the constructor of the class... 1548 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1549 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1550 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1551 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1552 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1553 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1554 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1555 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1556 << TargetName << "SubRegIdxRanges[];\n"; 1557 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1558 1559 EmitRegMappingTables(OS, Regs, true); 1560 1561 OS << ClassName << "::\n" 1562 << ClassName 1563 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1564 " unsigned PC, unsigned HwMode)\n" 1565 << " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc" 1566 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1567 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1568 << " "; 1569 printMask(OS, RegBank.CoveringLanes); 1570 OS << ", RegClassInfos, HwMode) {\n" 1571 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1572 << ", RA, PC,\n " << TargetName 1573 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1574 << " " << TargetName << "RegUnitRoots,\n" 1575 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1576 << " " << TargetName << "RegDiffLists,\n" 1577 << " " << TargetName << "LaneMaskLists,\n" 1578 << " " << TargetName << "RegStrings,\n" 1579 << " " << TargetName << "RegClassStrings,\n" 1580 << " " << TargetName << "SubRegIdxLists,\n" 1581 << " " << SubRegIndicesSize + 1 << ",\n" 1582 << " " << TargetName << "SubRegIdxRanges,\n" 1583 << " " << TargetName << "RegEncodingTable);\n\n"; 1584 1585 EmitRegMapping(OS, Regs, true); 1586 1587 OS << "}\n\n"; 1588 1589 // Emit CalleeSavedRegs information. 1590 std::vector<Record*> CSRSets = 1591 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1592 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1593 Record *CSRSet = CSRSets[i]; 1594 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1595 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1596 1597 // Emit the *_SaveList list of callee-saved registers. 1598 OS << "static const MCPhysReg " << CSRSet->getName() 1599 << "_SaveList[] = { "; 1600 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1601 OS << getQualifiedName((*Regs)[r]) << ", "; 1602 OS << "0 };\n"; 1603 1604 // Emit the *_RegMask bit mask of call-preserved registers. 1605 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1606 1607 // Check for an optional OtherPreserved set. 1608 // Add those registers to RegMask, but not to SaveList. 1609 if (DagInit *OPDag = 1610 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1611 SetTheory::RecSet OPSet; 1612 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1613 Covered |= RegBank.computeCoveredRegisters( 1614 ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1615 } 1616 1617 OS << "static const uint32_t " << CSRSet->getName() 1618 << "_RegMask[] = { "; 1619 printBitVectorAsHex(OS, Covered, 32); 1620 OS << "};\n"; 1621 } 1622 OS << "\n\n"; 1623 1624 OS << "ArrayRef<const uint32_t *> " << ClassName 1625 << "::getRegMasks() const {\n"; 1626 if (!CSRSets.empty()) { 1627 OS << " static const uint32_t *const Masks[] = {\n"; 1628 for (Record *CSRSet : CSRSets) 1629 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1630 OS << " };\n"; 1631 OS << " return makeArrayRef(Masks);\n"; 1632 } else { 1633 OS << " return None;\n"; 1634 } 1635 OS << "}\n\n"; 1636 1637 const std::list<CodeGenRegisterCategory> &RegCategories = 1638 RegBank.getRegCategories(); 1639 OS << "bool " << ClassName << "::\n" 1640 << "isGeneralPurposeRegister(const MachineFunction &MF, " 1641 << "MCRegister PhysReg) const {\n" 1642 << " return\n"; 1643 for (const CodeGenRegisterCategory &Category : RegCategories) 1644 if (Category.getName() == "GeneralPurposeRegisters") { 1645 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1646 OS << " " << RC->getQualifiedName() 1647 << "RegClass.contains(PhysReg) ||\n"; 1648 break; 1649 } 1650 OS << " false;\n"; 1651 OS << "}\n\n"; 1652 1653 OS << "bool " << ClassName << "::\n" 1654 << "isFixedRegister(const MachineFunction &MF, " 1655 << "MCRegister PhysReg) const {\n" 1656 << " return\n"; 1657 for (const CodeGenRegisterCategory &Category : RegCategories) 1658 if (Category.getName() == "FixedRegisters") { 1659 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1660 OS << " " << RC->getQualifiedName() 1661 << "RegClass.contains(PhysReg) ||\n"; 1662 break; 1663 } 1664 OS << " false;\n"; 1665 OS << "}\n\n"; 1666 1667 OS << "bool " << ClassName << "::\n" 1668 << "isArgumentRegister(const MachineFunction &MF, " 1669 << "MCRegister PhysReg) const {\n" 1670 << " return\n"; 1671 for (const CodeGenRegisterCategory &Category : RegCategories) 1672 if (Category.getName() == "ArgumentRegisters") { 1673 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1674 OS << " " << RC->getQualifiedName() 1675 << "RegClass.contains(PhysReg) ||\n"; 1676 break; 1677 } 1678 OS << " false;\n"; 1679 OS << "}\n\n"; 1680 1681 OS << "ArrayRef<const char *> " << ClassName 1682 << "::getRegMaskNames() const {\n"; 1683 if (!CSRSets.empty()) { 1684 OS << " static const char *Names[] = {\n"; 1685 for (Record *CSRSet : CSRSets) 1686 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1687 OS << " };\n"; 1688 OS << " return makeArrayRef(Names);\n"; 1689 } else { 1690 OS << " return None;\n"; 1691 } 1692 OS << "}\n\n"; 1693 1694 OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1695 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1696 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1697 << " MF.getSubtarget().getFrameLowering());\n" 1698 << "}\n\n"; 1699 1700 OS << "} // end namespace llvm\n\n"; 1701 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1702 } 1703 1704 void RegisterInfoEmitter::run(raw_ostream &OS) { 1705 CodeGenRegBank &RegBank = Target.getRegBank(); 1706 Records.startTimer("Print enums"); 1707 runEnums(OS, Target, RegBank); 1708 1709 Records.startTimer("Print MC registers"); 1710 runMCDesc(OS, Target, RegBank); 1711 1712 Records.startTimer("Print header fragment"); 1713 runTargetHeader(OS, Target, RegBank); 1714 1715 Records.startTimer("Print target registers"); 1716 runTargetDesc(OS, Target, RegBank); 1717 1718 if (RegisterInfoDebug) 1719 debugDump(errs()); 1720 } 1721 1722 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1723 CodeGenRegBank &RegBank = Target.getRegBank(); 1724 const CodeGenHwModes &CGH = Target.getHwModes(); 1725 unsigned NumModes = CGH.getNumModeIds(); 1726 auto getModeName = [CGH] (unsigned M) -> StringRef { 1727 if (M == 0) 1728 return "Default"; 1729 return CGH.getMode(M).Name; 1730 }; 1731 1732 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1733 OS << "RegisterClass " << RC.getName() << ":\n"; 1734 OS << "\tSpillSize: {"; 1735 for (unsigned M = 0; M != NumModes; ++M) 1736 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1737 OS << " }\n\tSpillAlignment: {"; 1738 for (unsigned M = 0; M != NumModes; ++M) 1739 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1740 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1741 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1742 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1743 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1744 OS << "\tAllocatable: " << RC.Allocatable << '\n'; 1745 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; 1746 OS << "\tRegs:"; 1747 for (const CodeGenRegister *R : RC.getMembers()) { 1748 OS << " " << R->getName(); 1749 } 1750 OS << '\n'; 1751 OS << "\tSubClasses:"; 1752 const BitVector &SubClasses = RC.getSubClasses(); 1753 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1754 if (!SubClasses.test(SRC.EnumValue)) 1755 continue; 1756 OS << " " << SRC.getName(); 1757 } 1758 OS << '\n'; 1759 OS << "\tSuperClasses:"; 1760 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1761 OS << " " << SRC->getName(); 1762 } 1763 OS << '\n'; 1764 } 1765 1766 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1767 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1768 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1769 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1770 } 1771 1772 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1773 OS << "Register " << R.getName() << ":\n"; 1774 OS << "\tCostPerUse: "; 1775 for (const auto &Cost : R.CostPerUse) 1776 OS << Cost << " "; 1777 OS << '\n'; 1778 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1779 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1780 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1781 OS << "\tSubReg " << P.first->getName() 1782 << " = " << P.second->getName() << '\n'; 1783 } 1784 } 1785 } 1786 1787 namespace llvm { 1788 1789 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1790 RegisterInfoEmitter(RK).run(OS); 1791 } 1792 1793 } // end namespace llvm 1794