1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend is responsible for emitting a description of a target 10 // register file for a code generator. It uses instances of the Register, 11 // RegisterAliases, and RegisterClass classes to gather this information. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "CodeGenHwModes.h" 16 #include "CodeGenRegisters.h" 17 #include "CodeGenTarget.h" 18 #include "InfoByHwMode.h" 19 #include "SequenceToOffsetTable.h" 20 #include "Types.h" 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/SetVector.h" 25 #include "llvm/ADT/SmallVector.h" 26 #include "llvm/ADT/SparseBitVector.h" 27 #include "llvm/ADT/Twine.h" 28 #include "llvm/CodeGen/MachineValueType.h" 29 #include "llvm/Support/Casting.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Support/Format.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/TableGen/Error.h" 34 #include "llvm/TableGen/Record.h" 35 #include "llvm/TableGen/SetTheory.h" 36 #include "llvm/TableGen/TableGenBackend.h" 37 #include <algorithm> 38 #include <cassert> 39 #include <cstddef> 40 #include <cstdint> 41 #include <deque> 42 #include <iterator> 43 #include <set> 44 #include <string> 45 #include <vector> 46 47 using namespace llvm; 48 49 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 50 51 static cl::opt<bool> 52 RegisterInfoDebug("register-info-debug", cl::init(false), 53 cl::desc("Dump register information to help debugging"), 54 cl::cat(RegisterInfoCat)); 55 56 namespace { 57 58 class RegisterInfoEmitter { 59 CodeGenTarget Target; 60 RecordKeeper &Records; 61 62 public: 63 RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 64 CodeGenRegBank &RegBank = Target.getRegBank(); 65 RegBank.computeDerivedInfo(); 66 } 67 68 // runEnums - Print out enum values for all of the registers. 69 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 70 71 // runMCDesc - Print out MC register descriptions. 72 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 73 74 // runTargetHeader - Emit a header fragment for the register info emitter. 75 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 76 CodeGenRegBank &Bank); 77 78 // runTargetDesc - Output the target register and register file descriptions. 79 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 80 CodeGenRegBank &Bank); 81 82 // run - Output the register file description. 83 void run(raw_ostream &o); 84 85 void debugDump(raw_ostream &OS); 86 87 private: 88 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 89 bool isCtor); 90 void EmitRegMappingTables(raw_ostream &o, 91 const std::deque<CodeGenRegister> &Regs, 92 bool isCtor); 93 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 94 const std::string &ClassName); 95 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 96 const std::string &ClassName); 97 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 98 const std::string &ClassName); 99 }; 100 101 } // end anonymous namespace 102 103 // runEnums - Print out enum values for all of the registers. 104 void RegisterInfoEmitter::runEnums(raw_ostream &OS, 105 CodeGenTarget &Target, CodeGenRegBank &Bank) { 106 const auto &Registers = Bank.getRegisters(); 107 108 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 109 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 110 111 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 112 113 emitSourceFileHeader("Target Register Enum Values", OS); 114 115 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 116 OS << "#undef GET_REGINFO_ENUM\n\n"; 117 118 OS << "namespace llvm {\n\n"; 119 120 OS << "class MCRegisterClass;\n" 121 << "extern const MCRegisterClass " << Target.getName() 122 << "MCRegisterClasses[];\n\n"; 123 124 if (!Namespace.empty()) 125 OS << "namespace " << Namespace << " {\n"; 126 OS << "enum {\n NoRegister,\n"; 127 128 for (const auto &Reg : Registers) 129 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 130 assert(Registers.size() == Registers.back().EnumValue && 131 "Register enum value mismatch!"); 132 OS << " NUM_TARGET_REGS // " << Registers.size()+1 << "\n"; 133 OS << "};\n"; 134 if (!Namespace.empty()) 135 OS << "} // end namespace " << Namespace << "\n"; 136 137 const auto &RegisterClasses = Bank.getRegClasses(); 138 if (!RegisterClasses.empty()) { 139 140 // RegisterClass enums are stored as uint16_t in the tables. 141 assert(RegisterClasses.size() <= 0xffff && 142 "Too many register classes to fit in tables"); 143 144 OS << "\n// Register classes\n\n"; 145 if (!Namespace.empty()) 146 OS << "namespace " << Namespace << " {\n"; 147 OS << "enum {\n"; 148 for (const auto &RC : RegisterClasses) 149 OS << " " << RC.getName() << "RegClassID" 150 << " = " << RC.EnumValue << ",\n"; 151 OS << "\n};\n"; 152 if (!Namespace.empty()) 153 OS << "} // end namespace " << Namespace << "\n\n"; 154 } 155 156 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 157 // If the only definition is the default NoRegAltName, we don't need to 158 // emit anything. 159 if (RegAltNameIndices.size() > 1) { 160 OS << "\n// Register alternate name indices\n\n"; 161 if (!Namespace.empty()) 162 OS << "namespace " << Namespace << " {\n"; 163 OS << "enum {\n"; 164 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 165 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 166 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 167 OS << "};\n"; 168 if (!Namespace.empty()) 169 OS << "} // end namespace " << Namespace << "\n\n"; 170 } 171 172 auto &SubRegIndices = Bank.getSubRegIndices(); 173 if (!SubRegIndices.empty()) { 174 OS << "\n// Subregister indices\n\n"; 175 std::string Namespace = SubRegIndices.front().getNamespace(); 176 if (!Namespace.empty()) 177 OS << "namespace " << Namespace << " {\n"; 178 OS << "enum : uint16_t {\n NoSubRegister,\n"; 179 unsigned i = 0; 180 for (const auto &Idx : SubRegIndices) 181 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 182 OS << " NUM_TARGET_SUBREGS\n};\n"; 183 if (!Namespace.empty()) 184 OS << "} // end namespace " << Namespace << "\n\n"; 185 } 186 187 OS << "// Register pressure sets enum.\n"; 188 if (!Namespace.empty()) 189 OS << "namespace " << Namespace << " {\n"; 190 OS << "enum RegisterPressureSets {\n"; 191 unsigned NumSets = Bank.getNumRegPressureSets(); 192 for (unsigned i = 0; i < NumSets; ++i ) { 193 const RegUnitSet &RegUnits = Bank.getRegSetAt(i); 194 OS << " " << RegUnits.Name << " = " << i << ",\n"; 195 } 196 OS << "};\n"; 197 if (!Namespace.empty()) 198 OS << "} // end namespace " << Namespace << '\n'; 199 OS << '\n'; 200 201 OS << "} // end namespace llvm\n\n"; 202 OS << "#endif // GET_REGINFO_ENUM\n\n"; 203 } 204 205 static void printInt(raw_ostream &OS, int Val) { 206 OS << Val; 207 } 208 209 void RegisterInfoEmitter:: 210 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 211 const std::string &ClassName) { 212 unsigned NumRCs = RegBank.getRegClasses().size(); 213 unsigned NumSets = RegBank.getNumRegPressureSets(); 214 215 OS << "/// Get the weight in units of pressure for this register class.\n" 216 << "const RegClassWeight &" << ClassName << "::\n" 217 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 218 << " static const RegClassWeight RCWeightTable[] = {\n"; 219 for (const auto &RC : RegBank.getRegClasses()) { 220 const CodeGenRegister::Vec &Regs = RC.getMembers(); 221 OS << " {" << RC.getWeight(RegBank) << ", "; 222 if (Regs.empty() || RC.Artificial) 223 OS << '0'; 224 else { 225 std::vector<unsigned> RegUnits; 226 RC.buildRegUnitSet(RegBank, RegUnits); 227 OS << RegBank.getRegUnitSetWeight(RegUnits); 228 } 229 OS << "}, \t// " << RC.getName() << "\n"; 230 } 231 OS << " };\n" 232 << " return RCWeightTable[RC->getID()];\n" 233 << "}\n\n"; 234 235 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 236 // bother generating a table. 237 bool RegUnitsHaveUnitWeight = true; 238 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 239 UnitIdx < UnitEnd; ++UnitIdx) { 240 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 241 RegUnitsHaveUnitWeight = false; 242 } 243 OS << "/// Get the weight in units of pressure for this register unit.\n" 244 << "unsigned " << ClassName << "::\n" 245 << "getRegUnitWeight(unsigned RegUnit) const {\n" 246 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 247 << " && \"invalid register unit\");\n"; 248 if (!RegUnitsHaveUnitWeight) { 249 OS << " static const uint8_t RUWeightTable[] = {\n "; 250 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 251 UnitIdx < UnitEnd; ++UnitIdx) { 252 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 253 assert(RU.Weight < 256 && "RegUnit too heavy"); 254 OS << RU.Weight << ", "; 255 } 256 OS << "};\n" 257 << " return RUWeightTable[RegUnit];\n"; 258 } 259 else { 260 OS << " // All register units have unit weight.\n" 261 << " return 1;\n"; 262 } 263 OS << "}\n\n"; 264 265 OS << "\n" 266 << "// Get the number of dimensions of register pressure.\n" 267 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 268 << " return " << NumSets << ";\n}\n\n"; 269 270 OS << "// Get the name of this register unit pressure set.\n" 271 << "const char *" << ClassName << "::\n" 272 << "getRegPressureSetName(unsigned Idx) const {\n" 273 << " static const char *PressureNameTable[] = {\n"; 274 unsigned MaxRegUnitWeight = 0; 275 for (unsigned i = 0; i < NumSets; ++i ) { 276 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 277 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 278 OS << " \"" << RegUnits.Name << "\",\n"; 279 } 280 OS << " };\n" 281 << " return PressureNameTable[Idx];\n" 282 << "}\n\n"; 283 284 OS << "// Get the register unit pressure limit for this dimension.\n" 285 << "// This limit must be adjusted dynamically for reserved registers.\n" 286 << "unsigned " << ClassName << "::\n" 287 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 288 "{\n" 289 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 290 << " PressureLimitTable[] = {\n"; 291 for (unsigned i = 0; i < NumSets; ++i ) { 292 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 293 OS << " " << RegUnits.Weight << ", \t// " << i << ": " 294 << RegUnits.Name << "\n"; 295 } 296 OS << " };\n" 297 << " return PressureLimitTable[Idx];\n" 298 << "}\n\n"; 299 300 SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 301 302 // This table may be larger than NumRCs if some register units needed a list 303 // of unit sets that did not correspond to a register class. 304 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 305 std::vector<std::vector<int>> PSets(NumRCUnitSets); 306 307 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 308 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 309 PSets[i].reserve(PSetIDs.size()); 310 for (unsigned PSetID : PSetIDs) { 311 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order); 312 } 313 llvm::sort(PSets[i]); 314 PSetsSeqs.add(PSets[i]); 315 } 316 317 PSetsSeqs.layout(); 318 319 OS << "/// Table of pressure sets per register class or unit.\n" 320 << "static const int RCSetsTable[] = {\n"; 321 PSetsSeqs.emit(OS, printInt, "-1"); 322 OS << "};\n\n"; 323 324 OS << "/// Get the dimensions of register pressure impacted by this " 325 << "register class.\n" 326 << "/// Returns a -1 terminated array of pressure set IDs\n" 327 << "const int *" << ClassName << "::\n" 328 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 329 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 330 << " RCSetStartTable[] = {\n "; 331 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 332 OS << PSetsSeqs.get(PSets[i]) << ","; 333 } 334 OS << "};\n" 335 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 336 << "}\n\n"; 337 338 OS << "/// Get the dimensions of register pressure impacted by this " 339 << "register unit.\n" 340 << "/// Returns a -1 terminated array of pressure set IDs\n" 341 << "const int *" << ClassName << "::\n" 342 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 343 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 344 << " && \"invalid register unit\");\n"; 345 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 346 << " RUSetStartTable[] = {\n "; 347 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 348 UnitIdx < UnitEnd; ++UnitIdx) { 349 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 350 << ","; 351 } 352 OS << "};\n" 353 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 354 << "}\n\n"; 355 } 356 357 using DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>; 358 using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 359 360 static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 361 // Sort and unique to get a map-like vector. We want the last assignment to 362 // match previous behaviour. 363 llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>()); 364 // Warn about duplicate assignments. 365 const Record *LastSeenReg = nullptr; 366 for (const auto &X : DwarfRegNums) { 367 const auto &Reg = X.first; 368 // The only way LessRecordRegister can return equal is if they're the same 369 // string. Use simple equality instead. 370 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 371 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 372 getQualifiedName(Reg) + 373 "specified multiple times"); 374 LastSeenReg = Reg; 375 } 376 auto Last = std::unique( 377 DwarfRegNums.begin(), DwarfRegNums.end(), 378 [](const DwarfRegNumsMapPair &A, const DwarfRegNumsMapPair &B) { 379 return A.first->getName() == B.first->getName(); 380 }); 381 DwarfRegNums.erase(Last, DwarfRegNums.end()); 382 } 383 384 void RegisterInfoEmitter::EmitRegMappingTables( 385 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 386 // Collect all information about dwarf register numbers 387 DwarfRegNumsVecTy DwarfRegNums; 388 389 // First, just pull all provided information to the map 390 unsigned maxLength = 0; 391 for (auto &RE : Regs) { 392 Record *Reg = RE.TheDef; 393 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 394 maxLength = std::max((size_t)maxLength, RegNums.size()); 395 DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 396 } 397 finalizeDwarfRegNumsKeys(DwarfRegNums); 398 399 if (!maxLength) 400 return; 401 402 // Now we know maximal length of number list. Append -1's, where needed 403 for (auto &DwarfRegNum : DwarfRegNums) 404 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) 405 DwarfRegNum.second.push_back(-1); 406 407 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 408 409 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 410 411 // Emit reverse information about the dwarf register numbers. 412 for (unsigned j = 0; j < 2; ++j) { 413 for (unsigned I = 0, E = maxLength; I != E; ++I) { 414 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 415 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 416 OS << I << "Dwarf2L[]"; 417 418 if (!isCtor) { 419 OS << " = {\n"; 420 421 // Store the mapping sorted by the LLVM reg num so lookup can be done 422 // with a binary search. 423 std::map<uint64_t, Record*> Dwarf2LMap; 424 for (auto &DwarfRegNum : DwarfRegNums) { 425 int DwarfRegNo = DwarfRegNum.second[I]; 426 if (DwarfRegNo < 0) 427 continue; 428 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; 429 } 430 431 for (auto &I : Dwarf2LMap) 432 OS << " { " << I.first << "U, " << getQualifiedName(I.second) 433 << " },\n"; 434 435 OS << "};\n"; 436 } else { 437 OS << ";\n"; 438 } 439 440 // We have to store the size in a const global, it's used in multiple 441 // places. 442 OS << "extern const unsigned " << Namespace 443 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize"; 444 if (!isCtor) 445 OS << " = std::size(" << Namespace 446 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n"; 447 else 448 OS << ";\n\n"; 449 } 450 } 451 452 for (auto &RE : Regs) { 453 Record *Reg = RE.TheDef; 454 const RecordVal *V = Reg->getValue("DwarfAlias"); 455 if (!V || !V->getValue()) 456 continue; 457 458 DefInit *DI = cast<DefInit>(V->getValue()); 459 Record *Alias = DI->getDef(); 460 const auto &AliasIter = llvm::lower_bound( 461 DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) { 462 return LessRecordRegister()(A.first, B); 463 }); 464 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 465 "Expected Alias to be present in map"); 466 const auto &RegIter = llvm::lower_bound( 467 DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) { 468 return LessRecordRegister()(A.first, B); 469 }); 470 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 471 "Expected Reg to be present in map"); 472 RegIter->second = AliasIter->second; 473 } 474 475 // Emit information about the dwarf register numbers. 476 for (unsigned j = 0; j < 2; ++j) { 477 for (unsigned i = 0, e = maxLength; i != e; ++i) { 478 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 479 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 480 OS << i << "L2Dwarf[]"; 481 if (!isCtor) { 482 OS << " = {\n"; 483 // Store the mapping sorted by the Dwarf reg num so lookup can be done 484 // with a binary search. 485 for (auto &DwarfRegNum : DwarfRegNums) { 486 int RegNo = DwarfRegNum.second[i]; 487 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 488 continue; 489 490 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo 491 << "U },\n"; 492 } 493 OS << "};\n"; 494 } else { 495 OS << ";\n"; 496 } 497 498 // We have to store the size in a const global, it's used in multiple 499 // places. 500 OS << "extern const unsigned " << Namespace 501 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 502 if (!isCtor) 503 OS << " = std::size(" << Namespace 504 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 505 else 506 OS << ";\n\n"; 507 } 508 } 509 } 510 511 void RegisterInfoEmitter::EmitRegMapping( 512 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 513 // Emit the initializer so the tables from EmitRegMappingTables get wired up 514 // to the MCRegisterInfo object. 515 unsigned maxLength = 0; 516 for (auto &RE : Regs) { 517 Record *Reg = RE.TheDef; 518 maxLength = std::max((size_t)maxLength, 519 Reg->getValueAsListOfInts("DwarfNumbers").size()); 520 } 521 522 if (!maxLength) 523 return; 524 525 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 526 527 // Emit reverse information about the dwarf register numbers. 528 for (unsigned j = 0; j < 2; ++j) { 529 OS << " switch ("; 530 if (j == 0) 531 OS << "DwarfFlavour"; 532 else 533 OS << "EHFlavour"; 534 OS << ") {\n" 535 << " default:\n" 536 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 537 538 for (unsigned i = 0, e = maxLength; i != e; ++i) { 539 OS << " case " << i << ":\n"; 540 OS << " "; 541 if (!isCtor) 542 OS << "RI->"; 543 std::string Tmp; 544 raw_string_ostream(Tmp) << Namespace 545 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 546 << "Dwarf2L"; 547 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 548 if (j == 0) 549 OS << "false"; 550 else 551 OS << "true"; 552 OS << ");\n"; 553 OS << " break;\n"; 554 } 555 OS << " }\n"; 556 } 557 558 // Emit information about the dwarf register numbers. 559 for (unsigned j = 0; j < 2; ++j) { 560 OS << " switch ("; 561 if (j == 0) 562 OS << "DwarfFlavour"; 563 else 564 OS << "EHFlavour"; 565 OS << ") {\n" 566 << " default:\n" 567 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 568 569 for (unsigned i = 0, e = maxLength; i != e; ++i) { 570 OS << " case " << i << ":\n"; 571 OS << " "; 572 if (!isCtor) 573 OS << "RI->"; 574 std::string Tmp; 575 raw_string_ostream(Tmp) << Namespace 576 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 577 << "L2Dwarf"; 578 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 579 if (j == 0) 580 OS << "false"; 581 else 582 OS << "true"; 583 OS << ");\n"; 584 OS << " break;\n"; 585 } 586 OS << " }\n"; 587 } 588 } 589 590 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 591 // Width is the number of bits per hex number. 592 static void printBitVectorAsHex(raw_ostream &OS, 593 const BitVector &Bits, 594 unsigned Width) { 595 assert(Width <= 32 && "Width too large"); 596 unsigned Digits = (Width + 3) / 4; 597 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 598 unsigned Value = 0; 599 for (unsigned j = 0; j != Width && i + j != e; ++j) 600 Value |= Bits.test(i + j) << j; 601 OS << format("0x%0*x, ", Digits, Value); 602 } 603 } 604 605 // Helper to emit a set of bits into a constant byte array. 606 class BitVectorEmitter { 607 BitVector Values; 608 public: 609 void add(unsigned v) { 610 if (v >= Values.size()) 611 Values.resize(((v/8)+1)*8); // Round up to the next byte. 612 Values[v] = true; 613 } 614 615 void print(raw_ostream &OS) { 616 printBitVectorAsHex(OS, Values, 8); 617 } 618 }; 619 620 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 621 OS << getEnumName(VT); 622 } 623 624 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 625 OS << Idx->EnumValue; 626 } 627 628 // Differentially encoded register and regunit lists allow for better 629 // compression on regular register banks. The sequence is computed from the 630 // differential list as: 631 // 632 // out[0] = InitVal; 633 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 634 // 635 // The initial value depends on the specific list. The list is terminated by a 636 // 0 differential which means we can't encode repeated elements. 637 638 typedef SmallVector<int16_t, 4> DiffVec; 639 typedef SmallVector<LaneBitmask, 4> MaskVec; 640 641 // Fills V with differentials between every two consecutive elements of List. 642 static DiffVec &diffEncode(DiffVec &V, SparseBitVector<> List) { 643 assert(V.empty() && "Clear DiffVec before diffEncode."); 644 SparseBitVector<>::iterator I = List.begin(), E = List.end(); 645 unsigned Val = *I; 646 while (++I != E) { 647 unsigned Cur = *I; 648 V.push_back(Cur - Val); 649 Val = Cur; 650 } 651 return V; 652 } 653 654 template<typename Iter> 655 static 656 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 657 assert(V.empty() && "Clear DiffVec before diffEncode."); 658 unsigned Val = InitVal; 659 for (Iter I = Begin; I != End; ++I) { 660 unsigned Cur = (*I)->EnumValue; 661 V.push_back(Cur - Val); 662 Val = Cur; 663 } 664 return V; 665 } 666 667 static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; } 668 669 static void printMask(raw_ostream &OS, LaneBitmask Val) { 670 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 671 } 672 673 // Try to combine Idx's compose map into Vec if it is compatible. 674 // Return false if it's not possible. 675 static bool combine(const CodeGenSubRegIndex *Idx, 676 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 677 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 678 for (const auto &I : Map) { 679 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 680 if (Entry && Entry != I.second) 681 return false; 682 } 683 684 // All entries are compatible. Make it so. 685 for (const auto &I : Map) { 686 auto *&Entry = Vec[I.first->EnumValue - 1]; 687 assert((!Entry || Entry == I.second) && 688 "Expected EnumValue to be unique"); 689 Entry = I.second; 690 } 691 return true; 692 } 693 694 void 695 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 696 CodeGenRegBank &RegBank, 697 const std::string &ClName) { 698 const auto &SubRegIndices = RegBank.getSubRegIndices(); 699 OS << "unsigned " << ClName 700 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 701 702 // Many sub-register indexes are composition-compatible, meaning that 703 // 704 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 705 // 706 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 707 // The illegal entries can be use as wildcards to compress the table further. 708 709 // Map each Sub-register index to a compatible table row. 710 SmallVector<unsigned, 4> RowMap; 711 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 712 713 auto SubRegIndicesSize = 714 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 715 for (const auto &Idx : SubRegIndices) { 716 unsigned Found = ~0u; 717 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 718 if (combine(&Idx, Rows[r])) { 719 Found = r; 720 break; 721 } 722 } 723 if (Found == ~0u) { 724 Found = Rows.size(); 725 Rows.resize(Found + 1); 726 Rows.back().resize(SubRegIndicesSize); 727 combine(&Idx, Rows.back()); 728 } 729 RowMap.push_back(Found); 730 } 731 732 // Output the row map if there is multiple rows. 733 if (Rows.size() > 1) { 734 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 735 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 736 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 737 OS << RowMap[i] << ", "; 738 OS << "\n };\n"; 739 } 740 741 // Output the rows. 742 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 743 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 744 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 745 OS << " { "; 746 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 747 if (Rows[r][i]) 748 OS << Rows[r][i]->getQualifiedName() << ", "; 749 else 750 OS << "0, "; 751 OS << "},\n"; 752 } 753 OS << " };\n\n"; 754 755 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" 756 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 757 if (Rows.size() > 1) 758 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 759 else 760 OS << " return Rows[0][IdxB];\n"; 761 OS << "}\n\n"; 762 } 763 764 void 765 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 766 CodeGenRegBank &RegBank, 767 const std::string &ClName) { 768 // See the comments in computeSubRegLaneMasks() for our goal here. 769 const auto &SubRegIndices = RegBank.getSubRegIndices(); 770 771 // Create a list of Mask+Rotate operations, with equivalent entries merged. 772 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 773 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 774 for (const auto &Idx : SubRegIndices) { 775 const SmallVector<MaskRolPair, 1> &IdxSequence 776 = Idx.CompositionLaneMaskTransform; 777 778 unsigned Found = ~0u; 779 unsigned SIdx = 0; 780 unsigned NextSIdx; 781 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 782 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 783 NextSIdx = SIdx + Sequence.size() + 1; 784 if (Sequence == IdxSequence) { 785 Found = SIdx; 786 break; 787 } 788 } 789 if (Found == ~0u) { 790 Sequences.push_back(IdxSequence); 791 Found = SIdx; 792 } 793 SubReg2SequenceIndexMap.push_back(Found); 794 } 795 796 OS << " struct MaskRolOp {\n" 797 " LaneBitmask Mask;\n" 798 " uint8_t RotateLeft;\n" 799 " };\n" 800 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 801 unsigned Idx = 0; 802 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 803 OS << " "; 804 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 805 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 806 const MaskRolPair &P = Sequence[p]; 807 printMask(OS << "{ ", P.Mask); 808 OS << format(", %2u }, ", P.RotateLeft); 809 } 810 OS << "{ LaneBitmask::getNone(), 0 }"; 811 if (s+1 != se) 812 OS << ", "; 813 OS << " // Sequence " << Idx << "\n"; 814 Idx += Sequence.size() + 1; 815 } 816 auto *IntType = getMinimalTypeForRange(*std::max_element( 817 SubReg2SequenceIndexMap.begin(), SubReg2SequenceIndexMap.end())); 818 OS << " };\n" 819 " static const " 820 << IntType << " CompositeSequences[] = {\n"; 821 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 822 OS << " "; 823 OS << SubReg2SequenceIndexMap[i]; 824 if (i+1 != e) 825 OS << ","; 826 OS << " // to " << SubRegIndices[i].getName() << "\n"; 827 } 828 OS << " };\n\n"; 829 830 OS << "LaneBitmask " << ClName 831 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 832 " const {\n" 833 " --IdxA; assert(IdxA < " << SubRegIndices.size() 834 << " && \"Subregister index out of bounds\");\n" 835 " LaneBitmask Result;\n" 836 " for (const MaskRolOp *Ops =\n" 837 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 838 " Ops->Mask.any(); ++Ops) {\n" 839 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 840 " if (unsigned S = Ops->RotateLeft)\n" 841 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 842 " else\n" 843 " Result |= LaneBitmask(M);\n" 844 " }\n" 845 " return Result;\n" 846 "}\n\n"; 847 848 OS << "LaneBitmask " << ClName 849 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 850 " LaneBitmask LaneMask) const {\n" 851 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 852 " --IdxA; assert(IdxA < " << SubRegIndices.size() 853 << " && \"Subregister index out of bounds\");\n" 854 " LaneBitmask Result;\n" 855 " for (const MaskRolOp *Ops =\n" 856 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 857 " Ops->Mask.any(); ++Ops) {\n" 858 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 859 " if (unsigned S = Ops->RotateLeft)\n" 860 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 861 " else\n" 862 " Result |= LaneBitmask(M);\n" 863 " }\n" 864 " return Result;\n" 865 "}\n\n"; 866 } 867 868 // 869 // runMCDesc - Print out MC register descriptions. 870 // 871 void 872 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 873 CodeGenRegBank &RegBank) { 874 emitSourceFileHeader("MC Register Information", OS); 875 876 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 877 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 878 879 const auto &Regs = RegBank.getRegisters(); 880 881 auto &SubRegIndices = RegBank.getSubRegIndices(); 882 // The lists of sub-registers and super-registers go in the same array. That 883 // allows us to share suffixes. 884 typedef std::vector<const CodeGenRegister*> RegVec; 885 886 // Differentially encoded lists. 887 SequenceToOffsetTable<DiffVec> DiffSeqs; 888 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 889 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 890 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 891 892 // List of lane masks accompanying register unit sequences. 893 SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 894 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 895 896 // Keep track of sub-register names as well. These are not differentially 897 // encoded. 898 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 899 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs; 900 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 901 902 SequenceToOffsetTable<std::string> RegStrings; 903 904 // Precompute register lists for the SequenceToOffsetTable. 905 unsigned i = 0; 906 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 907 const auto &Reg = *I; 908 RegStrings.add(std::string(Reg.getName())); 909 910 // Compute the ordered sub-register list. 911 SetVector<const CodeGenRegister*> SR; 912 Reg.addSubRegsPreOrder(SR, RegBank); 913 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 914 DiffSeqs.add(SubRegLists[i]); 915 916 // Compute the corresponding sub-register indexes. 917 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 918 for (const CodeGenRegister *S : SR) 919 SRIs.push_back(Reg.getSubRegIndex(S)); 920 SubRegIdxSeqs.add(SRIs); 921 922 // Super-registers are already computed. 923 const RegVec &SuperRegList = Reg.getSuperRegs(); 924 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 925 SuperRegList.end()); 926 DiffSeqs.add(SuperRegLists[i]); 927 928 const SparseBitVector<> &RUs = Reg.getNativeRegUnits(); 929 DiffSeqs.add(diffEncode(RegUnitLists[i], RUs)); 930 931 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 932 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 933 assert(LaneMaskVec.empty()); 934 llvm::append_range(LaneMaskVec, RUMasks); 935 // Terminator mask should not be used inside of the list. 936 #ifndef NDEBUG 937 for (LaneBitmask M : LaneMaskVec) { 938 assert(!M.all() && "terminator mask should not be part of the list"); 939 } 940 #endif 941 LaneMaskSeqs.add(LaneMaskVec); 942 } 943 944 // Compute the final layout of the sequence table. 945 DiffSeqs.layout(); 946 LaneMaskSeqs.layout(); 947 SubRegIdxSeqs.layout(); 948 949 OS << "namespace llvm {\n\n"; 950 951 const std::string &TargetName = std::string(Target.getName()); 952 953 // Emit the shared table of differential lists. 954 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n"; 955 DiffSeqs.emit(OS, printDiff16); 956 OS << "};\n\n"; 957 958 // Emit the shared table of regunit lane mask sequences. 959 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 960 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 961 OS << "};\n\n"; 962 963 // Emit the table of sub-register indexes. 964 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 965 SubRegIdxSeqs.emit(OS, printSubRegIndex); 966 OS << "};\n\n"; 967 968 // Emit the table of sub-register index sizes. 969 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 970 << TargetName << "SubRegIdxRanges[] = {\n"; 971 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 972 for (const auto &Idx : SubRegIndices) { 973 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 974 << Idx.getName() << "\n"; 975 } 976 OS << "};\n\n"; 977 978 // Emit the string table. 979 RegStrings.layout(); 980 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + 981 "RegStrings[]"); 982 983 OS << "extern const MCRegisterDesc " << TargetName 984 << "RegDesc[] = { // Descriptors\n"; 985 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 986 987 // Emit the register descriptors now. 988 i = 0; 989 for (const auto &Reg : Regs) { 990 unsigned FirstRU = Reg.getNativeRegUnits().find_first(); 991 unsigned Offset = DiffSeqs.get(RegUnitLists[i]); 992 // The value must be kept in sync with MCRegisterInfo.h. 993 constexpr unsigned RegUnitBits = 12; 994 assert(isUInt<RegUnitBits>(FirstRU) && "Too many regunits"); 995 assert(isUInt<32 - RegUnitBits>(Offset) && "Offset is too big"); 996 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " 997 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 998 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 999 << (Offset << RegUnitBits | FirstRU) << ", " 1000 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1001 ++i; 1002 } 1003 OS << "};\n\n"; // End of register descriptors... 1004 1005 // Emit the table of register unit roots. Each regunit has one or two root 1006 // registers. 1007 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1008 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1009 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 1010 assert(!Roots.empty() && "All regunits must have a root register."); 1011 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1012 OS << " { "; 1013 ListSeparator LS; 1014 for (const CodeGenRegister *R : Roots) 1015 OS << LS << getQualifiedName(R->TheDef); 1016 OS << " },\n"; 1017 } 1018 OS << "};\n\n"; 1019 1020 const auto &RegisterClasses = RegBank.getRegClasses(); 1021 1022 // Loop over all of the register classes... emitting each one. 1023 OS << "namespace { // Register classes...\n"; 1024 1025 SequenceToOffsetTable<std::string> RegClassStrings; 1026 1027 // Emit the register enum value arrays for each RegisterClass 1028 for (const auto &RC : RegisterClasses) { 1029 ArrayRef<Record*> Order = RC.getOrder(); 1030 1031 // Give the register class a legal C name if it's anonymous. 1032 const std::string &Name = RC.getName(); 1033 1034 RegClassStrings.add(Name); 1035 1036 // Emit the register list now (unless it would be a zero-length array). 1037 if (!Order.empty()) { 1038 OS << " // " << Name << " Register Class...\n" 1039 << " const MCPhysReg " << Name << "[] = {\n "; 1040 for (Record *Reg : Order) { 1041 OS << getQualifiedName(Reg) << ", "; 1042 } 1043 OS << "\n };\n\n"; 1044 1045 OS << " // " << Name << " Bit set.\n" 1046 << " const uint8_t " << Name << "Bits[] = {\n "; 1047 BitVectorEmitter BVE; 1048 for (Record *Reg : Order) { 1049 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1050 } 1051 BVE.print(OS); 1052 OS << "\n };\n\n"; 1053 } 1054 } 1055 OS << "} // end anonymous namespace\n\n"; 1056 1057 RegClassStrings.layout(); 1058 RegClassStrings.emitStringLiteralDef( 1059 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); 1060 1061 OS << "extern const MCRegisterClass " << TargetName 1062 << "MCRegisterClasses[] = {\n"; 1063 1064 for (const auto &RC : RegisterClasses) { 1065 ArrayRef<Record *> Order = RC.getOrder(); 1066 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); 1067 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; 1068 std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")"; 1069 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1070 uint32_t RegSize = 0; 1071 if (RC.RSI.isSimple()) 1072 RegSize = RC.RSI.getSimple().RegSize; 1073 OS << " { " << RCName << ", " << RCBitsName << ", " 1074 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() 1075 << ", " << RCBitsSize << ", " << RC.getQualifiedName() + "RegClassID" 1076 << ", " << RegSize << ", " << RC.CopyCost << ", " 1077 << (RC.Allocatable ? "true" : "false") << " },\n"; 1078 } 1079 1080 OS << "};\n\n"; 1081 1082 EmitRegMappingTables(OS, Regs, false); 1083 1084 // Emit Reg encoding table 1085 OS << "extern const uint16_t " << TargetName; 1086 OS << "RegEncodingTable[] = {\n"; 1087 // Add entry for NoRegister 1088 OS << " 0,\n"; 1089 for (const auto &RE : Regs) { 1090 Record *Reg = RE.TheDef; 1091 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1092 uint64_t Value = 0; 1093 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1094 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1095 Value |= (uint64_t)B->getValue() << b; 1096 } 1097 OS << " " << Value << ",\n"; 1098 } 1099 OS << "};\n"; // End of HW encoding table 1100 1101 // MCRegisterInfo initialization routine. 1102 OS << "static inline void Init" << TargetName 1103 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1104 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1105 "{\n" 1106 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1107 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1108 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1109 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1110 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1111 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1112 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1113 << TargetName << "SubRegIdxRanges, " << TargetName 1114 << "RegEncodingTable);\n\n"; 1115 1116 EmitRegMapping(OS, Regs, false); 1117 1118 OS << "}\n\n"; 1119 1120 OS << "} // end namespace llvm\n\n"; 1121 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1122 } 1123 1124 void 1125 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1126 CodeGenRegBank &RegBank) { 1127 emitSourceFileHeader("Register Information Header Fragment", OS); 1128 1129 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1130 OS << "#undef GET_REGINFO_HEADER\n\n"; 1131 1132 const std::string &TargetName = std::string(Target.getName()); 1133 std::string ClassName = TargetName + "GenRegisterInfo"; 1134 1135 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1136 1137 OS << "namespace llvm {\n\n"; 1138 1139 OS << "class " << TargetName << "FrameLowering;\n\n"; 1140 1141 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1142 << " explicit " << ClassName 1143 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1144 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1145 if (!RegBank.getSubRegIndices().empty()) { 1146 OS << " unsigned composeSubRegIndicesImpl" 1147 << "(unsigned, unsigned) const override;\n" 1148 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1149 << "(unsigned, LaneBitmask) const override;\n" 1150 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1151 << "(unsigned, LaneBitmask) const override;\n" 1152 << " const TargetRegisterClass *getSubClassWithSubReg" 1153 << "(const TargetRegisterClass *, unsigned) const override;\n" 1154 << " const TargetRegisterClass *getSubRegisterClass" 1155 << "(const TargetRegisterClass *, unsigned) const override;\n"; 1156 } 1157 OS << " const RegClassWeight &getRegClassWeight(" 1158 << "const TargetRegisterClass *RC) const override;\n" 1159 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1160 << " unsigned getNumRegPressureSets() const override;\n" 1161 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1162 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1163 "Idx) const override;\n" 1164 << " const int *getRegClassPressureSets(" 1165 << "const TargetRegisterClass *RC) const override;\n" 1166 << " const int *getRegUnitPressureSets(" 1167 << "unsigned RegUnit) const override;\n" 1168 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1169 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1170 << " bool isGeneralPurposeRegister(const MachineFunction &, " 1171 << "MCRegister) const override;\n" 1172 << " bool isFixedRegister(const MachineFunction &, " 1173 << "MCRegister) const override;\n" 1174 << " bool isArgumentRegister(const MachineFunction &, " 1175 << "MCRegister) const override;\n" 1176 << " bool isConstantPhysReg(MCRegister PhysReg) const override final;\n" 1177 << " /// Devirtualized TargetFrameLowering.\n" 1178 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1179 << " const MachineFunction &MF);\n"; 1180 1181 const auto &RegisterClasses = RegBank.getRegClasses(); 1182 if (llvm::any_of(RegisterClasses, [](const auto &RC) { return RC.getBaseClassOrder(); })) { 1183 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const override;\n"; 1184 } 1185 1186 OS << "};\n\n"; 1187 1188 if (!RegisterClasses.empty()) { 1189 OS << "namespace " << RegisterClasses.front().Namespace 1190 << " { // Register classes\n"; 1191 1192 for (const auto &RC : RegisterClasses) { 1193 const std::string &Name = RC.getName(); 1194 1195 // Output the extern for the instance. 1196 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1197 } 1198 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1199 } 1200 OS << "} // end namespace llvm\n\n"; 1201 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1202 } 1203 1204 // 1205 // runTargetDesc - Output the target register and register file descriptions. 1206 // 1207 void 1208 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1209 CodeGenRegBank &RegBank){ 1210 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1211 1212 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1213 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1214 1215 OS << "namespace llvm {\n\n"; 1216 1217 // Get access to MCRegisterClass data. 1218 OS << "extern const MCRegisterClass " << Target.getName() 1219 << "MCRegisterClasses[];\n"; 1220 1221 // Start out by emitting each of the register classes. 1222 const auto &RegisterClasses = RegBank.getRegClasses(); 1223 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1224 1225 // Collect all registers belonging to any allocatable class. 1226 std::set<Record*> AllocatableRegs; 1227 1228 // Collect allocatable registers. 1229 for (const auto &RC : RegisterClasses) { 1230 ArrayRef<Record*> Order = RC.getOrder(); 1231 1232 if (RC.Allocatable) 1233 AllocatableRegs.insert(Order.begin(), Order.end()); 1234 } 1235 1236 const CodeGenHwModes &CGH = Target.getHwModes(); 1237 unsigned NumModes = CGH.getNumModeIds(); 1238 1239 // Build a shared array of value types. 1240 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1241 for (unsigned M = 0; M < NumModes; ++M) { 1242 for (const auto &RC : RegisterClasses) { 1243 std::vector<MVT::SimpleValueType> S; 1244 for (const ValueTypeByHwMode &VVT : RC.VTs) 1245 if (VVT.hasDefault() || VVT.hasMode(M)) 1246 S.push_back(VVT.get(M).SimpleTy); 1247 VTSeqs.add(S); 1248 } 1249 } 1250 VTSeqs.layout(); 1251 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1252 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1253 OS << "};\n"; 1254 1255 // Emit SubRegIndex names, skipping 0. 1256 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; 1257 1258 for (const auto &Idx : SubRegIndices) { 1259 OS << Idx.getName(); 1260 OS << "\", \""; 1261 } 1262 OS << "\" };\n\n"; 1263 1264 // Emit SubRegIndex lane masks, including 0. 1265 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1266 "LaneBitmask::getAll(),\n"; 1267 for (const auto &Idx : SubRegIndices) { 1268 printMask(OS << " ", Idx.LaneMask); 1269 OS << ", // " << Idx.getName() << '\n'; 1270 } 1271 OS << " };\n\n"; 1272 1273 OS << "\n"; 1274 1275 // Now that all of the structs have been emitted, emit the instances. 1276 if (!RegisterClasses.empty()) { 1277 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1278 << " = {\n"; 1279 for (unsigned M = 0; M < NumModes; ++M) { 1280 unsigned EV = 0; 1281 OS << " // Mode = " << M << " ("; 1282 if (M == 0) 1283 OS << "Default"; 1284 else 1285 OS << CGH.getMode(M).Name; 1286 OS << ")\n"; 1287 for (const auto &RC : RegisterClasses) { 1288 assert(RC.EnumValue == EV && "Unexpected order of register classes"); 1289 ++EV; 1290 (void)EV; 1291 const RegSizeInfo &RI = RC.RSI.get(M); 1292 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1293 << RI.SpillAlignment; 1294 std::vector<MVT::SimpleValueType> VTs; 1295 for (const ValueTypeByHwMode &VVT : RC.VTs) 1296 if (VVT.hasDefault() || VVT.hasMode(M)) 1297 VTs.push_back(VVT.get(M).SimpleTy); 1298 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1299 << RC.getName() << '\n'; 1300 } 1301 } 1302 OS << "};\n"; 1303 1304 1305 OS << "\nstatic const TargetRegisterClass *const " 1306 << "NullRegClasses[] = { nullptr };\n\n"; 1307 1308 // Emit register class bit mask tables. The first bit mask emitted for a 1309 // register class, RC, is the set of sub-classes, including RC itself. 1310 // 1311 // If RC has super-registers, also create a list of subreg indices and bit 1312 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1313 // SuperRC, that satisfies: 1314 // 1315 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1316 // 1317 // The 0-terminated list of subreg indices starts at: 1318 // 1319 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1320 // 1321 // The corresponding bitmasks follow the sub-class mask in memory. Each 1322 // mask has RCMaskWords uint32_t entries. 1323 // 1324 // Every bit mask present in the list has at least one bit set. 1325 1326 // Compress the sub-reg index lists. 1327 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1328 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1329 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1330 BitVector MaskBV(RegisterClasses.size()); 1331 1332 for (const auto &RC : RegisterClasses) { 1333 OS << "static const uint32_t " << RC.getName() 1334 << "SubClassMask[] = {\n "; 1335 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1336 1337 // Emit super-reg class masks for any relevant SubRegIndices that can 1338 // project into RC. 1339 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1340 for (auto &Idx : SubRegIndices) { 1341 MaskBV.reset(); 1342 RC.getSuperRegClasses(&Idx, MaskBV); 1343 if (MaskBV.none()) 1344 continue; 1345 SRIList.push_back(&Idx); 1346 OS << "\n "; 1347 printBitVectorAsHex(OS, MaskBV, 32); 1348 OS << "// " << Idx.getName(); 1349 } 1350 SuperRegIdxSeqs.add(SRIList); 1351 OS << "\n};\n\n"; 1352 } 1353 1354 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1355 SuperRegIdxSeqs.layout(); 1356 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1357 OS << "};\n\n"; 1358 1359 // Emit NULL terminated super-class lists. 1360 for (const auto &RC : RegisterClasses) { 1361 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1362 1363 // Skip classes without supers. We can reuse NullRegClasses. 1364 if (Supers.empty()) 1365 continue; 1366 1367 OS << "static const TargetRegisterClass *const " 1368 << RC.getName() << "Superclasses[] = {\n"; 1369 for (const auto *Super : Supers) 1370 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1371 OS << " nullptr\n};\n\n"; 1372 } 1373 1374 // Emit methods. 1375 for (const auto &RC : RegisterClasses) { 1376 if (!RC.AltOrderSelect.empty()) { 1377 OS << "\nstatic inline unsigned " << RC.getName() 1378 << "AltOrderSelect(const MachineFunction &MF) {" 1379 << RC.AltOrderSelect << "}\n\n" 1380 << "static ArrayRef<MCPhysReg> " << RC.getName() 1381 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1382 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1383 ArrayRef<Record*> Elems = RC.getOrder(oi); 1384 if (!Elems.empty()) { 1385 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1386 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1387 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1388 OS << " };\n"; 1389 } 1390 } 1391 OS << " const MCRegisterClass &MCR = " << Target.getName() 1392 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1393 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1394 << " ArrayRef(MCR.begin(), MCR.getNumRegs()"; 1395 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1396 if (RC.getOrder(oi).empty()) 1397 OS << "),\n ArrayRef<MCPhysReg>("; 1398 else 1399 OS << "),\n ArrayRef(AltOrder" << oi; 1400 OS << ")\n };\n const unsigned Select = " << RC.getName() 1401 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1402 << ");\n return Order[Select];\n}\n"; 1403 } 1404 } 1405 1406 // Now emit the actual value-initialized register class instances. 1407 OS << "\nnamespace " << RegisterClasses.front().Namespace 1408 << " { // Register class instances\n"; 1409 1410 for (const auto &RC : RegisterClasses) { 1411 OS << " extern const TargetRegisterClass " << RC.getName() 1412 << "RegClass = {\n " << '&' << Target.getName() 1413 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1414 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1415 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1416 printMask(OS, RC.LaneMask); 1417 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1418 << (RC.GlobalPriority ? "true" : "false") << ",\n " 1419 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n " 1420 << (RC.HasDisjunctSubRegs ? "true" : "false") 1421 << ", /* HasDisjunctSubRegs */\n " 1422 << (RC.CoveredBySubRegs ? "true" : "false") 1423 << ", /* CoveredBySubRegs */\n "; 1424 if (RC.getSuperClasses().empty()) 1425 OS << "NullRegClasses,\n "; 1426 else 1427 OS << RC.getName() << "Superclasses,\n "; 1428 if (RC.AltOrderSelect.empty()) 1429 OS << "nullptr\n"; 1430 else 1431 OS << RC.getName() << "GetRawAllocationOrder\n"; 1432 OS << " };\n\n"; 1433 } 1434 1435 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1436 } 1437 1438 OS << "\nnamespace {\n"; 1439 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; 1440 for (const auto &RC : RegisterClasses) 1441 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1442 OS << " };\n"; 1443 OS << "} // end anonymous namespace\n"; 1444 1445 // Emit extra information about registers. 1446 const std::string &TargetName = std::string(Target.getName()); 1447 const auto &Regs = RegBank.getRegisters(); 1448 unsigned NumRegCosts = 1; 1449 for (const auto &Reg : Regs) 1450 NumRegCosts = std::max((size_t)NumRegCosts, Reg.CostPerUse.size()); 1451 1452 std::vector<unsigned> AllRegCostPerUse; 1453 llvm::BitVector InAllocClass(Regs.size() + 1, false); 1454 AllRegCostPerUse.insert(AllRegCostPerUse.end(), NumRegCosts, 0); 1455 1456 // Populate the vector RegCosts with the CostPerUse list of the registers 1457 // in the order they are read. Have at most NumRegCosts entries for 1458 // each register. Fill with zero for values which are not explicitly given. 1459 for (const auto &Reg : Regs) { 1460 auto Costs = Reg.CostPerUse; 1461 AllRegCostPerUse.insert(AllRegCostPerUse.end(), Costs.begin(), Costs.end()); 1462 if (NumRegCosts > Costs.size()) 1463 AllRegCostPerUse.insert(AllRegCostPerUse.end(), 1464 NumRegCosts - Costs.size(), 0); 1465 1466 if (AllocatableRegs.count(Reg.TheDef)) 1467 InAllocClass.set(Reg.EnumValue); 1468 } 1469 1470 // Emit the cost values as a 1D-array after grouping them by their indices, 1471 // i.e. the costs for all registers corresponds to index 0, 1, 2, etc. 1472 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1). 1473 OS << "\nstatic const uint8_t " 1474 << "CostPerUseTable[] = { \n"; 1475 for (unsigned int I = 0; I < NumRegCosts; ++I) { 1476 for (unsigned J = I, E = AllRegCostPerUse.size(); J < E; J += NumRegCosts) 1477 OS << AllRegCostPerUse[J] << ", "; 1478 } 1479 OS << "};\n\n"; 1480 1481 OS << "\nstatic const bool " 1482 << "InAllocatableClassTable[] = { \n"; 1483 for (unsigned I = 0, E = InAllocClass.size(); I < E; ++I) { 1484 OS << (InAllocClass[I] ? "true" : "false") << ", "; 1485 } 1486 OS << "};\n\n"; 1487 1488 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName 1489 << "RegInfoDesc = { // Extra Descriptors\n"; 1490 OS << "CostPerUseTable, " << NumRegCosts << ", " 1491 << "InAllocatableClassTable"; 1492 OS << "};\n\n"; // End of register descriptors... 1493 1494 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1495 1496 auto SubRegIndicesSize = 1497 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1498 1499 if (!SubRegIndices.empty()) { 1500 emitComposeSubRegIndices(OS, RegBank, ClassName); 1501 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1502 } 1503 1504 if (!SubRegIndices.empty()) { 1505 // Emit getSubClassWithSubReg. 1506 OS << "const TargetRegisterClass *" << ClassName 1507 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1508 << " const {\n"; 1509 // Use the smallest type that can hold a regclass ID with room for a 1510 // sentinel. 1511 if (RegisterClasses.size() <= UINT8_MAX) 1512 OS << " static const uint8_t Table["; 1513 else if (RegisterClasses.size() <= UINT16_MAX) 1514 OS << " static const uint16_t Table["; 1515 else 1516 PrintFatalError("Too many register classes."); 1517 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1518 for (const auto &RC : RegisterClasses) { 1519 OS << " {\t// " << RC.getName() << "\n"; 1520 for (auto &Idx : SubRegIndices) { 1521 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1522 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1523 << " -> " << SRC->getName() << "\n"; 1524 else 1525 OS << " 0,\t// " << Idx.getName() << "\n"; 1526 } 1527 OS << " },\n"; 1528 } 1529 OS << " };\n assert(RC && \"Missing regclass\");\n" 1530 << " if (!Idx) return RC;\n --Idx;\n" 1531 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1532 << " unsigned TV = Table[RC->getID()][Idx];\n" 1533 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1534 1535 // Emit getSubRegisterClass 1536 OS << "const TargetRegisterClass *" << ClassName 1537 << "::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx)" 1538 << " const {\n"; 1539 1540 // Use the smallest type that can hold a regclass ID with room for a 1541 // sentinel. 1542 if (RegisterClasses.size() <= UINT8_MAX) 1543 OS << " static const uint8_t Table["; 1544 else if (RegisterClasses.size() <= UINT16_MAX) 1545 OS << " static const uint16_t Table["; 1546 else 1547 PrintFatalError("Too many register classes."); 1548 1549 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1550 1551 for (const auto &RC : RegisterClasses) { 1552 OS << " {\t// " << RC.getName() << '\n'; 1553 for (auto &Idx : SubRegIndices) { 1554 std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>> 1555 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx); 1556 1557 unsigned EnumValue = 0; 1558 if (MatchingSubClass) { 1559 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; 1560 EnumValue = SubRegClass->EnumValue + 1; 1561 } 1562 1563 OS << " " << EnumValue << ",\t// " 1564 << RC.getName() << ':' << Idx.getName(); 1565 1566 if (MatchingSubClass) { 1567 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; 1568 OS << " -> " << SubRegClass->getName(); 1569 } 1570 1571 OS << '\n'; 1572 } 1573 1574 OS << " },\n"; 1575 } 1576 OS << " };\n assert(RC && \"Missing regclass\");\n" 1577 << " if (!Idx) return RC;\n --Idx;\n" 1578 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1579 << " unsigned TV = Table[RC->getID()][Idx];\n" 1580 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1581 } 1582 1583 EmitRegUnitPressure(OS, RegBank, ClassName); 1584 1585 // Emit register base class mapper 1586 if (!RegisterClasses.empty()) { 1587 // Collect base classes 1588 SmallVector<const CodeGenRegisterClass*> BaseClasses; 1589 for (const auto &RC : RegisterClasses) { 1590 if (RC.getBaseClassOrder()) 1591 BaseClasses.push_back(&RC); 1592 } 1593 if (!BaseClasses.empty()) { 1594 // Represent class indexes with uint8_t and allocate one index for nullptr 1595 assert(BaseClasses.size() <= UINT8_MAX && "Too many base register classes"); 1596 1597 // Apply order 1598 struct BaseClassOrdering { 1599 bool operator()(const CodeGenRegisterClass *LHS, const CodeGenRegisterClass *RHS) const { 1600 return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) 1601 < std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue); 1602 } 1603 }; 1604 llvm::stable_sort(BaseClasses, BaseClassOrdering()); 1605 1606 // Build mapping for Regs (+1 for NoRegister) 1607 std::vector<uint8_t> Mapping(Regs.size() + 1, 0); 1608 for (int RCIdx = BaseClasses.size() - 1; RCIdx >= 0; --RCIdx) { 1609 for (const auto Reg : BaseClasses[RCIdx]->getMembers()) 1610 Mapping[Reg->EnumValue] = RCIdx + 1; 1611 } 1612 1613 OS << "\n// Register to base register class mapping\n\n"; 1614 OS << "\n"; 1615 OS << "const TargetRegisterClass *" << ClassName 1616 << "::getPhysRegBaseClass(MCRegister Reg)" 1617 << " const {\n"; 1618 OS << " static const TargetRegisterClass *BaseClasses[" << (BaseClasses.size() + 1) << "] = {\n"; 1619 OS << " nullptr,\n"; 1620 for (const auto RC : BaseClasses) 1621 OS << " &" << RC->getQualifiedName() << "RegClass,\n"; 1622 OS << " };\n"; 1623 OS << " static const uint8_t Mapping[" << Mapping.size() << "] = {\n "; 1624 for (const uint8_t Value : Mapping) 1625 OS << (unsigned)Value << ","; 1626 OS << " };\n\n"; 1627 OS << " assert(Reg < sizeof(Mapping));\n"; 1628 OS << " return BaseClasses[Mapping[Reg]];\n"; 1629 OS << "}\n"; 1630 } 1631 } 1632 1633 // Emit the constructor of the class... 1634 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1635 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n"; 1636 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1637 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1638 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1639 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1640 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1641 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1642 << TargetName << "SubRegIdxRanges[];\n"; 1643 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1644 1645 EmitRegMappingTables(OS, Regs, true); 1646 1647 OS << ClassName << "::\n" 1648 << ClassName 1649 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1650 " unsigned PC, unsigned HwMode)\n" 1651 << " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc" 1652 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1653 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1654 << " "; 1655 printMask(OS, RegBank.CoveringLanes); 1656 OS << ", RegClassInfos, HwMode) {\n" 1657 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1658 << ", RA, PC,\n " << TargetName 1659 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1660 << " " << TargetName << "RegUnitRoots,\n" 1661 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1662 << " " << TargetName << "RegDiffLists,\n" 1663 << " " << TargetName << "LaneMaskLists,\n" 1664 << " " << TargetName << "RegStrings,\n" 1665 << " " << TargetName << "RegClassStrings,\n" 1666 << " " << TargetName << "SubRegIdxLists,\n" 1667 << " " << SubRegIndicesSize + 1 << ",\n" 1668 << " " << TargetName << "SubRegIdxRanges,\n" 1669 << " " << TargetName << "RegEncodingTable);\n\n"; 1670 1671 EmitRegMapping(OS, Regs, true); 1672 1673 OS << "}\n\n"; 1674 1675 // Emit CalleeSavedRegs information. 1676 std::vector<Record*> CSRSets = 1677 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1678 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1679 Record *CSRSet = CSRSets[i]; 1680 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1681 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1682 1683 // Emit the *_SaveList list of callee-saved registers. 1684 OS << "static const MCPhysReg " << CSRSet->getName() 1685 << "_SaveList[] = { "; 1686 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1687 OS << getQualifiedName((*Regs)[r]) << ", "; 1688 OS << "0 };\n"; 1689 1690 // Emit the *_RegMask bit mask of call-preserved registers. 1691 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1692 1693 // Check for an optional OtherPreserved set. 1694 // Add those registers to RegMask, but not to SaveList. 1695 if (DagInit *OPDag = 1696 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1697 SetTheory::RecSet OPSet; 1698 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1699 Covered |= RegBank.computeCoveredRegisters( 1700 ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1701 } 1702 1703 // Add all constant physical registers to the preserved mask: 1704 SetTheory::RecSet ConstantSet; 1705 for (auto &Reg : RegBank.getRegisters()) { 1706 if (Reg.Constant) 1707 ConstantSet.insert(Reg.TheDef); 1708 } 1709 Covered |= RegBank.computeCoveredRegisters( 1710 ArrayRef<Record *>(ConstantSet.begin(), ConstantSet.end())); 1711 1712 OS << "static const uint32_t " << CSRSet->getName() 1713 << "_RegMask[] = { "; 1714 printBitVectorAsHex(OS, Covered, 32); 1715 OS << "};\n"; 1716 } 1717 OS << "\n\n"; 1718 1719 OS << "ArrayRef<const uint32_t *> " << ClassName 1720 << "::getRegMasks() const {\n"; 1721 if (!CSRSets.empty()) { 1722 OS << " static const uint32_t *const Masks[] = {\n"; 1723 for (Record *CSRSet : CSRSets) 1724 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1725 OS << " };\n"; 1726 OS << " return ArrayRef(Masks);\n"; 1727 } else { 1728 OS << " return std::nullopt;\n"; 1729 } 1730 OS << "}\n\n"; 1731 1732 const std::list<CodeGenRegisterCategory> &RegCategories = 1733 RegBank.getRegCategories(); 1734 OS << "bool " << ClassName << "::\n" 1735 << "isGeneralPurposeRegister(const MachineFunction &MF, " 1736 << "MCRegister PhysReg) const {\n" 1737 << " return\n"; 1738 for (const CodeGenRegisterCategory &Category : RegCategories) 1739 if (Category.getName() == "GeneralPurposeRegisters") { 1740 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1741 OS << " " << RC->getQualifiedName() 1742 << "RegClass.contains(PhysReg) ||\n"; 1743 break; 1744 } 1745 OS << " false;\n"; 1746 OS << "}\n\n"; 1747 1748 OS << "bool " << ClassName << "::\n" 1749 << "isFixedRegister(const MachineFunction &MF, " 1750 << "MCRegister PhysReg) const {\n" 1751 << " return\n"; 1752 for (const CodeGenRegisterCategory &Category : RegCategories) 1753 if (Category.getName() == "FixedRegisters") { 1754 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1755 OS << " " << RC->getQualifiedName() 1756 << "RegClass.contains(PhysReg) ||\n"; 1757 break; 1758 } 1759 OS << " false;\n"; 1760 OS << "}\n\n"; 1761 1762 OS << "bool " << ClassName << "::\n" 1763 << "isArgumentRegister(const MachineFunction &MF, " 1764 << "MCRegister PhysReg) const {\n" 1765 << " return\n"; 1766 for (const CodeGenRegisterCategory &Category : RegCategories) 1767 if (Category.getName() == "ArgumentRegisters") { 1768 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1769 OS << " " << RC->getQualifiedName() 1770 << "RegClass.contains(PhysReg) ||\n"; 1771 break; 1772 } 1773 OS << " false;\n"; 1774 OS << "}\n\n"; 1775 1776 OS << "bool " << ClassName << "::\n" 1777 << "isConstantPhysReg(MCRegister PhysReg) const {\n" 1778 << " return\n"; 1779 for (const auto &Reg : Regs) 1780 if (Reg.Constant) 1781 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n"; 1782 OS << " false;\n"; 1783 OS << "}\n\n"; 1784 1785 OS << "ArrayRef<const char *> " << ClassName 1786 << "::getRegMaskNames() const {\n"; 1787 if (!CSRSets.empty()) { 1788 OS << " static const char *Names[] = {\n"; 1789 for (Record *CSRSet : CSRSets) 1790 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1791 OS << " };\n"; 1792 OS << " return ArrayRef(Names);\n"; 1793 } else { 1794 OS << " return std::nullopt;\n"; 1795 } 1796 OS << "}\n\n"; 1797 1798 OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1799 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1800 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1801 << " MF.getSubtarget().getFrameLowering());\n" 1802 << "}\n\n"; 1803 1804 OS << "} // end namespace llvm\n\n"; 1805 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1806 } 1807 1808 void RegisterInfoEmitter::run(raw_ostream &OS) { 1809 CodeGenRegBank &RegBank = Target.getRegBank(); 1810 Records.startTimer("Print enums"); 1811 runEnums(OS, Target, RegBank); 1812 1813 Records.startTimer("Print MC registers"); 1814 runMCDesc(OS, Target, RegBank); 1815 1816 Records.startTimer("Print header fragment"); 1817 runTargetHeader(OS, Target, RegBank); 1818 1819 Records.startTimer("Print target registers"); 1820 runTargetDesc(OS, Target, RegBank); 1821 1822 if (RegisterInfoDebug) 1823 debugDump(errs()); 1824 } 1825 1826 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1827 CodeGenRegBank &RegBank = Target.getRegBank(); 1828 const CodeGenHwModes &CGH = Target.getHwModes(); 1829 unsigned NumModes = CGH.getNumModeIds(); 1830 auto getModeName = [CGH] (unsigned M) -> StringRef { 1831 if (M == 0) 1832 return "Default"; 1833 return CGH.getMode(M).Name; 1834 }; 1835 1836 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1837 OS << "RegisterClass " << RC.getName() << ":\n"; 1838 OS << "\tSpillSize: {"; 1839 for (unsigned M = 0; M != NumModes; ++M) 1840 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1841 OS << " }\n\tSpillAlignment: {"; 1842 for (unsigned M = 0; M != NumModes; ++M) 1843 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1844 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1845 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1846 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1847 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1848 OS << "\tAllocatable: " << RC.Allocatable << '\n'; 1849 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; 1850 OS << "\tRegs:"; 1851 for (const CodeGenRegister *R : RC.getMembers()) { 1852 OS << " " << R->getName(); 1853 } 1854 OS << '\n'; 1855 OS << "\tSubClasses:"; 1856 const BitVector &SubClasses = RC.getSubClasses(); 1857 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1858 if (!SubClasses.test(SRC.EnumValue)) 1859 continue; 1860 OS << " " << SRC.getName(); 1861 } 1862 OS << '\n'; 1863 OS << "\tSuperClasses:"; 1864 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1865 OS << " " << SRC->getName(); 1866 } 1867 OS << '\n'; 1868 } 1869 1870 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1871 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1872 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1873 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1874 OS << "\tOffset, Size: " << SRI.Offset << ", " << SRI.Size << '\n'; 1875 } 1876 1877 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1878 OS << "Register " << R.getName() << ":\n"; 1879 OS << "\tCostPerUse: "; 1880 for (const auto &Cost : R.CostPerUse) 1881 OS << Cost << " "; 1882 OS << '\n'; 1883 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1884 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1885 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1886 OS << "\tSubReg " << P.first->getName() 1887 << " = " << P.second->getName() << '\n'; 1888 } 1889 } 1890 } 1891 1892 static TableGen::Emitter::OptClass<RegisterInfoEmitter> 1893 X("gen-register-info", "Generate registers and register classes info"); 1894