1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend is responsible for emitting a description of a target 10 // register file for a code generator. It uses instances of the Register, 11 // RegisterAliases, and RegisterClass classes to gather this information. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "CodeGenRegisters.h" 16 #include "CodeGenTarget.h" 17 #include "SequenceToOffsetTable.h" 18 #include "Types.h" 19 #include "llvm/ADT/ArrayRef.h" 20 #include "llvm/ADT/BitVector.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/ADT/SetVector.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/ADT/SparseBitVector.h" 25 #include "llvm/ADT/Twine.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/Format.h" 29 #include "llvm/Support/MachineValueType.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/TableGen/Error.h" 32 #include "llvm/TableGen/Record.h" 33 #include "llvm/TableGen/SetTheory.h" 34 #include "llvm/TableGen/TableGenBackend.h" 35 #include <algorithm> 36 #include <cassert> 37 #include <cstddef> 38 #include <cstdint> 39 #include <deque> 40 #include <iterator> 41 #include <set> 42 #include <string> 43 #include <vector> 44 45 using namespace llvm; 46 47 cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 48 49 static cl::opt<bool> 50 RegisterInfoDebug("register-info-debug", cl::init(false), 51 cl::desc("Dump register information to help debugging"), 52 cl::cat(RegisterInfoCat)); 53 54 namespace { 55 56 class RegisterInfoEmitter { 57 CodeGenTarget Target; 58 RecordKeeper &Records; 59 60 public: 61 RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) { 62 CodeGenRegBank &RegBank = Target.getRegBank(); 63 RegBank.computeDerivedInfo(); 64 } 65 66 // runEnums - Print out enum values for all of the registers. 67 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 68 69 // runMCDesc - Print out MC register descriptions. 70 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); 71 72 // runTargetHeader - Emit a header fragment for the register info emitter. 73 void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, 74 CodeGenRegBank &Bank); 75 76 // runTargetDesc - Output the target register and register file descriptions. 77 void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, 78 CodeGenRegBank &Bank); 79 80 // run - Output the register file description. 81 void run(raw_ostream &o); 82 83 void debugDump(raw_ostream &OS); 84 85 private: 86 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 87 bool isCtor); 88 void EmitRegMappingTables(raw_ostream &o, 89 const std::deque<CodeGenRegister> &Regs, 90 bool isCtor); 91 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 92 const std::string &ClassName); 93 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, 94 const std::string &ClassName); 95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank, 96 const std::string &ClassName); 97 }; 98 99 } // end anonymous namespace 100 101 // runEnums - Print out enum values for all of the registers. 102 void RegisterInfoEmitter::runEnums(raw_ostream &OS, 103 CodeGenTarget &Target, CodeGenRegBank &Bank) { 104 const auto &Registers = Bank.getRegisters(); 105 106 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 107 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 108 109 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 110 111 emitSourceFileHeader("Target Register Enum Values", OS); 112 113 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 114 OS << "#undef GET_REGINFO_ENUM\n\n"; 115 116 OS << "namespace llvm {\n\n"; 117 118 OS << "class MCRegisterClass;\n" 119 << "extern const MCRegisterClass " << Target.getName() 120 << "MCRegisterClasses[];\n\n"; 121 122 if (!Namespace.empty()) 123 OS << "namespace " << Namespace << " {\n"; 124 OS << "enum {\n NoRegister,\n"; 125 126 for (const auto &Reg : Registers) 127 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 128 assert(Registers.size() == Registers.back().EnumValue && 129 "Register enum value mismatch!"); 130 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 131 OS << "};\n"; 132 if (!Namespace.empty()) 133 OS << "} // end namespace " << Namespace << "\n"; 134 135 const auto &RegisterClasses = Bank.getRegClasses(); 136 if (!RegisterClasses.empty()) { 137 138 // RegisterClass enums are stored as uint16_t in the tables. 139 assert(RegisterClasses.size() <= 0xffff && 140 "Too many register classes to fit in tables"); 141 142 OS << "\n// Register classes\n\n"; 143 if (!Namespace.empty()) 144 OS << "namespace " << Namespace << " {\n"; 145 OS << "enum {\n"; 146 for (const auto &RC : RegisterClasses) 147 OS << " " << RC.getName() << "RegClassID" 148 << " = " << RC.EnumValue << ",\n"; 149 OS << "\n };\n"; 150 if (!Namespace.empty()) 151 OS << "} // end namespace " << Namespace << "\n\n"; 152 } 153 154 const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); 155 // If the only definition is the default NoRegAltName, we don't need to 156 // emit anything. 157 if (RegAltNameIndices.size() > 1) { 158 OS << "\n// Register alternate name indices\n\n"; 159 if (!Namespace.empty()) 160 OS << "namespace " << Namespace << " {\n"; 161 OS << "enum {\n"; 162 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 163 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 164 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 165 OS << "};\n"; 166 if (!Namespace.empty()) 167 OS << "} // end namespace " << Namespace << "\n\n"; 168 } 169 170 auto &SubRegIndices = Bank.getSubRegIndices(); 171 if (!SubRegIndices.empty()) { 172 OS << "\n// Subregister indices\n\n"; 173 std::string Namespace = SubRegIndices.front().getNamespace(); 174 if (!Namespace.empty()) 175 OS << "namespace " << Namespace << " {\n"; 176 OS << "enum {\n NoSubRegister,\n"; 177 unsigned i = 0; 178 for (const auto &Idx : SubRegIndices) 179 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 180 OS << " NUM_TARGET_SUBREGS\n};\n"; 181 if (!Namespace.empty()) 182 OS << "} // end namespace " << Namespace << "\n\n"; 183 } 184 185 OS << "} // end namespace llvm\n\n"; 186 OS << "#endif // GET_REGINFO_ENUM\n\n"; 187 } 188 189 static void printInt(raw_ostream &OS, int Val) { 190 OS << Val; 191 } 192 193 void RegisterInfoEmitter:: 194 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, 195 const std::string &ClassName) { 196 unsigned NumRCs = RegBank.getRegClasses().size(); 197 unsigned NumSets = RegBank.getNumRegPressureSets(); 198 199 OS << "/// Get the weight in units of pressure for this register class.\n" 200 << "const RegClassWeight &" << ClassName << "::\n" 201 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 202 << " static const RegClassWeight RCWeightTable[] = {\n"; 203 for (const auto &RC : RegBank.getRegClasses()) { 204 const CodeGenRegister::Vec &Regs = RC.getMembers(); 205 if (Regs.empty() || RC.Artificial) 206 OS << " {0, 0"; 207 else { 208 std::vector<unsigned> RegUnits; 209 RC.buildRegUnitSet(RegBank, RegUnits); 210 OS << " {" << (*Regs.begin())->getWeight(RegBank) 211 << ", " << RegBank.getRegUnitSetWeight(RegUnits); 212 } 213 OS << "}, \t// " << RC.getName() << "\n"; 214 } 215 OS << " };\n" 216 << " return RCWeightTable[RC->getID()];\n" 217 << "}\n\n"; 218 219 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 220 // bother generating a table. 221 bool RegUnitsHaveUnitWeight = true; 222 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 223 UnitIdx < UnitEnd; ++UnitIdx) { 224 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 225 RegUnitsHaveUnitWeight = false; 226 } 227 OS << "/// Get the weight in units of pressure for this register unit.\n" 228 << "unsigned " << ClassName << "::\n" 229 << "getRegUnitWeight(unsigned RegUnit) const {\n" 230 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 231 << " && \"invalid register unit\");\n"; 232 if (!RegUnitsHaveUnitWeight) { 233 OS << " static const uint8_t RUWeightTable[] = {\n "; 234 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 235 UnitIdx < UnitEnd; ++UnitIdx) { 236 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 237 assert(RU.Weight < 256 && "RegUnit too heavy"); 238 OS << RU.Weight << ", "; 239 } 240 OS << "};\n" 241 << " return RUWeightTable[RegUnit];\n"; 242 } 243 else { 244 OS << " // All register units have unit weight.\n" 245 << " return 1;\n"; 246 } 247 OS << "}\n\n"; 248 249 OS << "\n" 250 << "// Get the number of dimensions of register pressure.\n" 251 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 252 << " return " << NumSets << ";\n}\n\n"; 253 254 OS << "// Get the name of this register unit pressure set.\n" 255 << "const char *" << ClassName << "::\n" 256 << "getRegPressureSetName(unsigned Idx) const {\n" 257 << " static const char *const PressureNameTable[] = {\n"; 258 unsigned MaxRegUnitWeight = 0; 259 for (unsigned i = 0; i < NumSets; ++i ) { 260 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 261 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 262 OS << " \"" << RegUnits.Name << "\",\n"; 263 } 264 OS << " };\n" 265 << " return PressureNameTable[Idx];\n" 266 << "}\n\n"; 267 268 OS << "// Get the register unit pressure limit for this dimension.\n" 269 << "// This limit must be adjusted dynamically for reserved registers.\n" 270 << "unsigned " << ClassName << "::\n" 271 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 272 "{\n" 273 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 274 << " PressureLimitTable[] = {\n"; 275 for (unsigned i = 0; i < NumSets; ++i ) { 276 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 277 OS << " " << RegUnits.Weight << ", \t// " << i << ": " 278 << RegUnits.Name << "\n"; 279 } 280 OS << " };\n" 281 << " return PressureLimitTable[Idx];\n" 282 << "}\n\n"; 283 284 SequenceToOffsetTable<std::vector<int>> PSetsSeqs; 285 286 // This table may be larger than NumRCs if some register units needed a list 287 // of unit sets that did not correspond to a register class. 288 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 289 std::vector<std::vector<int>> PSets(NumRCUnitSets); 290 291 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 292 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 293 PSets[i].reserve(PSetIDs.size()); 294 for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), 295 PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { 296 PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order); 297 } 298 llvm::sort(PSets[i]); 299 PSetsSeqs.add(PSets[i]); 300 } 301 302 PSetsSeqs.layout(); 303 304 OS << "/// Table of pressure sets per register class or unit.\n" 305 << "static const int RCSetsTable[] = {\n"; 306 PSetsSeqs.emit(OS, printInt, "-1"); 307 OS << "};\n\n"; 308 309 OS << "/// Get the dimensions of register pressure impacted by this " 310 << "register class.\n" 311 << "/// Returns a -1 terminated array of pressure set IDs\n" 312 << "const int* " << ClassName << "::\n" 313 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 314 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 315 << " RCSetStartTable[] = {\n "; 316 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 317 OS << PSetsSeqs.get(PSets[i]) << ","; 318 } 319 OS << "};\n" 320 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 321 << "}\n\n"; 322 323 OS << "/// Get the dimensions of register pressure impacted by this " 324 << "register unit.\n" 325 << "/// Returns a -1 terminated array of pressure set IDs\n" 326 << "const int* " << ClassName << "::\n" 327 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 328 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 329 << " && \"invalid register unit\");\n"; 330 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 331 << " RUSetStartTable[] = {\n "; 332 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 333 UnitIdx < UnitEnd; ++UnitIdx) { 334 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 335 << ","; 336 } 337 OS << "};\n" 338 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 339 << "}\n\n"; 340 } 341 342 using DwarfRegNumsMapPair = std::pair<Record*, std::vector<int64_t>>; 343 using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 344 345 void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 346 // Sort and unique to get a map-like vector. We want the last assignment to 347 // match previous behaviour. 348 std::stable_sort(DwarfRegNums.begin(), DwarfRegNums.end(), 349 on_first<LessRecordRegister>()); 350 // Warn about duplicate assignments. 351 const Record *LastSeenReg = nullptr; 352 for (const auto &X : DwarfRegNums) { 353 const auto &Reg = X.first; 354 // The only way LessRecordRegister can return equal is if they're the same 355 // string. Use simple equality instead. 356 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 357 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 358 getQualifiedName(Reg) + 359 "specified multiple times"); 360 LastSeenReg = Reg; 361 } 362 auto Last = std::unique( 363 DwarfRegNums.begin(), DwarfRegNums.end(), 364 [](const DwarfRegNumsMapPair &A, const DwarfRegNumsMapPair &B) { 365 return A.first->getName() == B.first->getName(); 366 }); 367 DwarfRegNums.erase(Last, DwarfRegNums.end()); 368 } 369 370 void RegisterInfoEmitter::EmitRegMappingTables( 371 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 372 // Collect all information about dwarf register numbers 373 DwarfRegNumsVecTy DwarfRegNums; 374 375 // First, just pull all provided information to the map 376 unsigned maxLength = 0; 377 for (auto &RE : Regs) { 378 Record *Reg = RE.TheDef; 379 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 380 maxLength = std::max((size_t)maxLength, RegNums.size()); 381 DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 382 } 383 finalizeDwarfRegNumsKeys(DwarfRegNums); 384 385 if (!maxLength) 386 return; 387 388 // Now we know maximal length of number list. Append -1's, where needed 389 for (DwarfRegNumsVecTy::iterator I = DwarfRegNums.begin(), 390 E = DwarfRegNums.end(); 391 I != E; ++I) 392 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 393 I->second.push_back(-1); 394 395 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 396 397 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 398 399 // Emit reverse information about the dwarf register numbers. 400 for (unsigned j = 0; j < 2; ++j) { 401 for (unsigned i = 0, e = maxLength; i != e; ++i) { 402 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 403 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 404 OS << i << "Dwarf2L[]"; 405 406 if (!isCtor) { 407 OS << " = {\n"; 408 409 // Store the mapping sorted by the LLVM reg num so lookup can be done 410 // with a binary search. 411 std::map<uint64_t, Record*> Dwarf2LMap; 412 for (DwarfRegNumsVecTy::iterator 413 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 414 int DwarfRegNo = I->second[i]; 415 if (DwarfRegNo < 0) 416 continue; 417 Dwarf2LMap[DwarfRegNo] = I->first; 418 } 419 420 for (std::map<uint64_t, Record*>::iterator 421 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I) 422 OS << " { " << I->first << "U, " << getQualifiedName(I->second) 423 << " },\n"; 424 425 OS << "};\n"; 426 } else { 427 OS << ";\n"; 428 } 429 430 // We have to store the size in a const global, it's used in multiple 431 // places. 432 OS << "extern const unsigned " << Namespace 433 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize"; 434 if (!isCtor) 435 OS << " = array_lengthof(" << Namespace 436 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 437 << "Dwarf2L);\n\n"; 438 else 439 OS << ";\n\n"; 440 } 441 } 442 443 for (auto &RE : Regs) { 444 Record *Reg = RE.TheDef; 445 const RecordVal *V = Reg->getValue("DwarfAlias"); 446 if (!V || !V->getValue()) 447 continue; 448 449 DefInit *DI = cast<DefInit>(V->getValue()); 450 Record *Alias = DI->getDef(); 451 const auto &AliasIter = 452 std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Alias, 453 [](const DwarfRegNumsMapPair &A, const Record *B) { 454 return LessRecordRegister()(A.first, B); 455 }); 456 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 457 "Expected Alias to be present in map"); 458 const auto &RegIter = 459 std::lower_bound(DwarfRegNums.begin(), DwarfRegNums.end(), Reg, 460 [](const DwarfRegNumsMapPair &A, const Record *B) { 461 return LessRecordRegister()(A.first, B); 462 }); 463 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 464 "Expected Reg to be present in map"); 465 RegIter->second = AliasIter->second; 466 } 467 468 // Emit information about the dwarf register numbers. 469 for (unsigned j = 0; j < 2; ++j) { 470 for (unsigned i = 0, e = maxLength; i != e; ++i) { 471 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 472 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 473 OS << i << "L2Dwarf[]"; 474 if (!isCtor) { 475 OS << " = {\n"; 476 // Store the mapping sorted by the Dwarf reg num so lookup can be done 477 // with a binary search. 478 for (DwarfRegNumsVecTy::iterator 479 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 480 int RegNo = I->second[i]; 481 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 482 continue; 483 484 OS << " { " << getQualifiedName(I->first) << ", " << RegNo 485 << "U },\n"; 486 } 487 OS << "};\n"; 488 } else { 489 OS << ";\n"; 490 } 491 492 // We have to store the size in a const global, it's used in multiple 493 // places. 494 OS << "extern const unsigned " << Namespace 495 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 496 if (!isCtor) 497 OS << " = array_lengthof(" << Namespace 498 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 499 else 500 OS << ";\n\n"; 501 } 502 } 503 } 504 505 void RegisterInfoEmitter::EmitRegMapping( 506 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 507 // Emit the initializer so the tables from EmitRegMappingTables get wired up 508 // to the MCRegisterInfo object. 509 unsigned maxLength = 0; 510 for (auto &RE : Regs) { 511 Record *Reg = RE.TheDef; 512 maxLength = std::max((size_t)maxLength, 513 Reg->getValueAsListOfInts("DwarfNumbers").size()); 514 } 515 516 if (!maxLength) 517 return; 518 519 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 520 521 // Emit reverse information about the dwarf register numbers. 522 for (unsigned j = 0; j < 2; ++j) { 523 OS << " switch ("; 524 if (j == 0) 525 OS << "DwarfFlavour"; 526 else 527 OS << "EHFlavour"; 528 OS << ") {\n" 529 << " default:\n" 530 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 531 532 for (unsigned i = 0, e = maxLength; i != e; ++i) { 533 OS << " case " << i << ":\n"; 534 OS << " "; 535 if (!isCtor) 536 OS << "RI->"; 537 std::string Tmp; 538 raw_string_ostream(Tmp) << Namespace 539 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 540 << "Dwarf2L"; 541 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 542 if (j == 0) 543 OS << "false"; 544 else 545 OS << "true"; 546 OS << ");\n"; 547 OS << " break;\n"; 548 } 549 OS << " }\n"; 550 } 551 552 // Emit information about the dwarf register numbers. 553 for (unsigned j = 0; j < 2; ++j) { 554 OS << " switch ("; 555 if (j == 0) 556 OS << "DwarfFlavour"; 557 else 558 OS << "EHFlavour"; 559 OS << ") {\n" 560 << " default:\n" 561 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 562 563 for (unsigned i = 0, e = maxLength; i != e; ++i) { 564 OS << " case " << i << ":\n"; 565 OS << " "; 566 if (!isCtor) 567 OS << "RI->"; 568 std::string Tmp; 569 raw_string_ostream(Tmp) << Namespace 570 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 571 << "L2Dwarf"; 572 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 573 if (j == 0) 574 OS << "false"; 575 else 576 OS << "true"; 577 OS << ");\n"; 578 OS << " break;\n"; 579 } 580 OS << " }\n"; 581 } 582 } 583 584 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 585 // Width is the number of bits per hex number. 586 static void printBitVectorAsHex(raw_ostream &OS, 587 const BitVector &Bits, 588 unsigned Width) { 589 assert(Width <= 32 && "Width too large"); 590 unsigned Digits = (Width + 3) / 4; 591 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 592 unsigned Value = 0; 593 for (unsigned j = 0; j != Width && i + j != e; ++j) 594 Value |= Bits.test(i + j) << j; 595 OS << format("0x%0*x, ", Digits, Value); 596 } 597 } 598 599 // Helper to emit a set of bits into a constant byte array. 600 class BitVectorEmitter { 601 BitVector Values; 602 public: 603 void add(unsigned v) { 604 if (v >= Values.size()) 605 Values.resize(((v/8)+1)*8); // Round up to the next byte. 606 Values[v] = true; 607 } 608 609 void print(raw_ostream &OS) { 610 printBitVectorAsHex(OS, Values, 8); 611 } 612 }; 613 614 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 615 OS << getEnumName(VT); 616 } 617 618 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 619 OS << Idx->EnumValue; 620 } 621 622 // Differentially encoded register and regunit lists allow for better 623 // compression on regular register banks. The sequence is computed from the 624 // differential list as: 625 // 626 // out[0] = InitVal; 627 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 628 // 629 // The initial value depends on the specific list. The list is terminated by a 630 // 0 differential which means we can't encode repeated elements. 631 632 typedef SmallVector<uint16_t, 4> DiffVec; 633 typedef SmallVector<LaneBitmask, 4> MaskVec; 634 635 // Differentially encode a sequence of numbers into V. The starting value and 636 // terminating 0 are not added to V, so it will have the same size as List. 637 static 638 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) { 639 assert(V.empty() && "Clear DiffVec before diffEncode."); 640 uint16_t Val = uint16_t(InitVal); 641 642 for (uint16_t Cur : List) { 643 V.push_back(Cur - Val); 644 Val = Cur; 645 } 646 return V; 647 } 648 649 template<typename Iter> 650 static 651 DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 652 assert(V.empty() && "Clear DiffVec before diffEncode."); 653 uint16_t Val = uint16_t(InitVal); 654 for (Iter I = Begin; I != End; ++I) { 655 uint16_t Cur = (*I)->EnumValue; 656 V.push_back(Cur - Val); 657 Val = Cur; 658 } 659 return V; 660 } 661 662 static void printDiff16(raw_ostream &OS, uint16_t Val) { 663 OS << Val; 664 } 665 666 static void printMask(raw_ostream &OS, LaneBitmask Val) { 667 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 668 } 669 670 // Try to combine Idx's compose map into Vec if it is compatible. 671 // Return false if it's not possible. 672 static bool combine(const CodeGenSubRegIndex *Idx, 673 SmallVectorImpl<CodeGenSubRegIndex*> &Vec) { 674 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 675 for (const auto &I : Map) { 676 CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 677 if (Entry && Entry != I.second) 678 return false; 679 } 680 681 // All entries are compatible. Make it so. 682 for (const auto &I : Map) { 683 auto *&Entry = Vec[I.first->EnumValue - 1]; 684 assert((!Entry || Entry == I.second) && 685 "Expected EnumValue to be unique"); 686 Entry = I.second; 687 } 688 return true; 689 } 690 691 void 692 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 693 CodeGenRegBank &RegBank, 694 const std::string &ClName) { 695 const auto &SubRegIndices = RegBank.getSubRegIndices(); 696 OS << "unsigned " << ClName 697 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 698 699 // Many sub-register indexes are composition-compatible, meaning that 700 // 701 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 702 // 703 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 704 // The illegal entries can be use as wildcards to compress the table further. 705 706 // Map each Sub-register index to a compatible table row. 707 SmallVector<unsigned, 4> RowMap; 708 SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows; 709 710 auto SubRegIndicesSize = 711 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 712 for (const auto &Idx : SubRegIndices) { 713 unsigned Found = ~0u; 714 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 715 if (combine(&Idx, Rows[r])) { 716 Found = r; 717 break; 718 } 719 } 720 if (Found == ~0u) { 721 Found = Rows.size(); 722 Rows.resize(Found + 1); 723 Rows.back().resize(SubRegIndicesSize); 724 combine(&Idx, Rows.back()); 725 } 726 RowMap.push_back(Found); 727 } 728 729 // Output the row map if there is multiple rows. 730 if (Rows.size() > 1) { 731 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 732 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 733 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 734 OS << RowMap[i] << ", "; 735 OS << "\n };\n"; 736 } 737 738 // Output the rows. 739 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 740 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 741 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 742 OS << " { "; 743 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 744 if (Rows[r][i]) 745 OS << Rows[r][i]->getQualifiedName() << ", "; 746 else 747 OS << "0, "; 748 OS << "},\n"; 749 } 750 OS << " };\n\n"; 751 752 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 753 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 754 if (Rows.size() > 1) 755 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 756 else 757 OS << " return Rows[0][IdxB];\n"; 758 OS << "}\n\n"; 759 } 760 761 void 762 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 763 CodeGenRegBank &RegBank, 764 const std::string &ClName) { 765 // See the comments in computeSubRegLaneMasks() for our goal here. 766 const auto &SubRegIndices = RegBank.getSubRegIndices(); 767 768 // Create a list of Mask+Rotate operations, with equivalent entries merged. 769 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 770 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 771 for (const auto &Idx : SubRegIndices) { 772 const SmallVector<MaskRolPair, 1> &IdxSequence 773 = Idx.CompositionLaneMaskTransform; 774 775 unsigned Found = ~0u; 776 unsigned SIdx = 0; 777 unsigned NextSIdx; 778 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 779 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 780 NextSIdx = SIdx + Sequence.size() + 1; 781 if (Sequence == IdxSequence) { 782 Found = SIdx; 783 break; 784 } 785 } 786 if (Found == ~0u) { 787 Sequences.push_back(IdxSequence); 788 Found = SIdx; 789 } 790 SubReg2SequenceIndexMap.push_back(Found); 791 } 792 793 OS << " struct MaskRolOp {\n" 794 " LaneBitmask Mask;\n" 795 " uint8_t RotateLeft;\n" 796 " };\n" 797 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 798 unsigned Idx = 0; 799 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 800 OS << " "; 801 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 802 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) { 803 const MaskRolPair &P = Sequence[p]; 804 printMask(OS << "{ ", P.Mask); 805 OS << format(", %2u }, ", P.RotateLeft); 806 } 807 OS << "{ LaneBitmask::getNone(), 0 }"; 808 if (s+1 != se) 809 OS << ", "; 810 OS << " // Sequence " << Idx << "\n"; 811 Idx += Sequence.size() + 1; 812 } 813 OS << " };\n" 814 " static const MaskRolOp *const CompositeSequences[] = {\n"; 815 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 816 OS << " "; 817 unsigned Idx = SubReg2SequenceIndexMap[i]; 818 OS << format("&LaneMaskComposeSequences[%u]", Idx); 819 if (i+1 != e) 820 OS << ","; 821 OS << " // to " << SubRegIndices[i].getName() << "\n"; 822 } 823 OS << " };\n\n"; 824 825 OS << "LaneBitmask " << ClName 826 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 827 " const {\n" 828 " --IdxA; assert(IdxA < " << SubRegIndices.size() 829 << " && \"Subregister index out of bounds\");\n" 830 " LaneBitmask Result;\n" 831 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 832 " LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();\n" 833 " if (unsigned S = Ops->RotateLeft)\n" 834 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));\n" 835 " else\n" 836 " Result |= LaneBitmask(M);\n" 837 " }\n" 838 " return Result;\n" 839 "}\n\n"; 840 841 OS << "LaneBitmask " << ClName 842 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 843 " LaneBitmask LaneMask) const {\n" 844 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 845 " --IdxA; assert(IdxA < " << SubRegIndices.size() 846 << " && \"Subregister index out of bounds\");\n" 847 " LaneBitmask Result;\n" 848 " for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {\n" 849 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 850 " if (unsigned S = Ops->RotateLeft)\n" 851 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));\n" 852 " else\n" 853 " Result |= LaneBitmask(M);\n" 854 " }\n" 855 " return Result;\n" 856 "}\n\n"; 857 } 858 859 // 860 // runMCDesc - Print out MC register descriptions. 861 // 862 void 863 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 864 CodeGenRegBank &RegBank) { 865 emitSourceFileHeader("MC Register Information", OS); 866 867 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 868 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 869 870 const auto &Regs = RegBank.getRegisters(); 871 872 auto &SubRegIndices = RegBank.getSubRegIndices(); 873 // The lists of sub-registers and super-registers go in the same array. That 874 // allows us to share suffixes. 875 typedef std::vector<const CodeGenRegister*> RegVec; 876 877 // Differentially encoded lists. 878 SequenceToOffsetTable<DiffVec> DiffSeqs; 879 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 880 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 881 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 882 SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); 883 884 // List of lane masks accompanying register unit sequences. 885 SequenceToOffsetTable<MaskVec> LaneMaskSeqs; 886 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 887 888 // Keep track of sub-register names as well. These are not differentially 889 // encoded. 890 typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; 891 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs; 892 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 893 894 SequenceToOffsetTable<std::string> RegStrings; 895 896 // Precompute register lists for the SequenceToOffsetTable. 897 unsigned i = 0; 898 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 899 const auto &Reg = *I; 900 RegStrings.add(Reg.getName()); 901 902 // Compute the ordered sub-register list. 903 SetVector<const CodeGenRegister*> SR; 904 Reg.addSubRegsPreOrder(SR, RegBank); 905 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 906 DiffSeqs.add(SubRegLists[i]); 907 908 // Compute the corresponding sub-register indexes. 909 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 910 for (const CodeGenRegister *S : SR) 911 SRIs.push_back(Reg.getSubRegIndex(S)); 912 SubRegIdxSeqs.add(SRIs); 913 914 // Super-registers are already computed. 915 const RegVec &SuperRegList = Reg.getSuperRegs(); 916 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 917 SuperRegList.end()); 918 DiffSeqs.add(SuperRegLists[i]); 919 920 // Differentially encode the register unit list, seeded by register number. 921 // First compute a scale factor that allows more diff-lists to be reused: 922 // 923 // D0 -> (S0, S1) 924 // D1 -> (S2, S3) 925 // 926 // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial 927 // value for the differential decoder is the register number multiplied by 928 // the scale. 929 // 930 // Check the neighboring registers for arithmetic progressions. 931 unsigned ScaleA = ~0u, ScaleB = ~0u; 932 SparseBitVector<> RUs = Reg.getNativeRegUnits(); 933 if (I != Regs.begin() && 934 std::prev(I)->getNativeRegUnits().count() == RUs.count()) 935 ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin(); 936 if (std::next(I) != Regs.end() && 937 std::next(I)->getNativeRegUnits().count() == RUs.count()) 938 ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin(); 939 unsigned Scale = std::min(ScaleB, ScaleA); 940 // Default the scale to 0 if it can't be encoded in 4 bits. 941 if (Scale >= 16) 942 Scale = 0; 943 RegUnitInitScale[i] = Scale; 944 DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs)); 945 946 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 947 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 948 assert(LaneMaskVec.empty()); 949 LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end()); 950 // Terminator mask should not be used inside of the list. 951 #ifndef NDEBUG 952 for (LaneBitmask M : LaneMaskVec) { 953 assert(!M.all() && "terminator mask should not be part of the list"); 954 } 955 #endif 956 LaneMaskSeqs.add(LaneMaskVec); 957 } 958 959 // Compute the final layout of the sequence table. 960 DiffSeqs.layout(); 961 LaneMaskSeqs.layout(); 962 SubRegIdxSeqs.layout(); 963 964 OS << "namespace llvm {\n\n"; 965 966 const std::string &TargetName = Target.getName(); 967 968 // Emit the shared table of differential lists. 969 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; 970 DiffSeqs.emit(OS, printDiff16); 971 OS << "};\n\n"; 972 973 // Emit the shared table of regunit lane mask sequences. 974 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 975 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); 976 OS << "};\n\n"; 977 978 // Emit the table of sub-register indexes. 979 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 980 SubRegIdxSeqs.emit(OS, printSubRegIndex); 981 OS << "};\n\n"; 982 983 // Emit the table of sub-register index sizes. 984 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 985 << TargetName << "SubRegIdxRanges[] = {\n"; 986 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 987 for (const auto &Idx : SubRegIndices) { 988 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " 989 << Idx.getName() << "\n"; 990 } 991 OS << "};\n\n"; 992 993 // Emit the string table. 994 RegStrings.layout(); 995 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; 996 RegStrings.emit(OS, printChar); 997 OS << "};\n\n"; 998 999 OS << "extern const MCRegisterDesc " << TargetName 1000 << "RegDesc[] = { // Descriptors\n"; 1001 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; 1002 1003 // Emit the register descriptors now. 1004 i = 0; 1005 for (const auto &Reg : Regs) { 1006 OS << " { " << RegStrings.get(Reg.getName()) << ", " 1007 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1008 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1009 << (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", " 1010 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n"; 1011 ++i; 1012 } 1013 OS << "};\n\n"; // End of register descriptors... 1014 1015 // Emit the table of register unit roots. Each regunit has one or two root 1016 // registers. 1017 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1018 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1019 ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots(); 1020 assert(!Roots.empty() && "All regunits must have a root register."); 1021 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1022 OS << " { " << getQualifiedName(Roots.front()->TheDef); 1023 for (unsigned r = 1; r != Roots.size(); ++r) 1024 OS << ", " << getQualifiedName(Roots[r]->TheDef); 1025 OS << " },\n"; 1026 } 1027 OS << "};\n\n"; 1028 1029 const auto &RegisterClasses = RegBank.getRegClasses(); 1030 1031 // Loop over all of the register classes... emitting each one. 1032 OS << "namespace { // Register classes...\n"; 1033 1034 SequenceToOffsetTable<std::string> RegClassStrings; 1035 1036 // Emit the register enum value arrays for each RegisterClass 1037 for (const auto &RC : RegisterClasses) { 1038 ArrayRef<Record*> Order = RC.getOrder(); 1039 1040 // Give the register class a legal C name if it's anonymous. 1041 const std::string &Name = RC.getName(); 1042 1043 RegClassStrings.add(Name); 1044 1045 // Emit the register list now. 1046 OS << " // " << Name << " Register Class...\n" 1047 << " const MCPhysReg " << Name 1048 << "[] = {\n "; 1049 for (Record *Reg : Order) { 1050 OS << getQualifiedName(Reg) << ", "; 1051 } 1052 OS << "\n };\n\n"; 1053 1054 OS << " // " << Name << " Bit set.\n" 1055 << " const uint8_t " << Name 1056 << "Bits[] = {\n "; 1057 BitVectorEmitter BVE; 1058 for (Record *Reg : Order) { 1059 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 1060 } 1061 BVE.print(OS); 1062 OS << "\n };\n\n"; 1063 1064 } 1065 OS << "} // end anonymous namespace\n\n"; 1066 1067 RegClassStrings.layout(); 1068 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; 1069 RegClassStrings.emit(OS, printChar); 1070 OS << "};\n\n"; 1071 1072 OS << "extern const MCRegisterClass " << TargetName 1073 << "MCRegisterClasses[] = {\n"; 1074 1075 for (const auto &RC : RegisterClasses) { 1076 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1077 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " 1078 << RegClassStrings.get(RC.getName()) << ", " 1079 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " 1080 << RC.getQualifiedName() + "RegClassID" << ", " 1081 << RC.CopyCost << ", " 1082 << ( RC.Allocatable ? "true" : "false" ) << " },\n"; 1083 } 1084 1085 OS << "};\n\n"; 1086 1087 EmitRegMappingTables(OS, Regs, false); 1088 1089 // Emit Reg encoding table 1090 OS << "extern const uint16_t " << TargetName; 1091 OS << "RegEncodingTable[] = {\n"; 1092 // Add entry for NoRegister 1093 OS << " 0,\n"; 1094 for (const auto &RE : Regs) { 1095 Record *Reg = RE.TheDef; 1096 BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1097 uint64_t Value = 0; 1098 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1099 if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1100 Value |= (uint64_t)B->getValue() << b; 1101 } 1102 OS << " " << Value << ",\n"; 1103 } 1104 OS << "};\n"; // End of HW encoding table 1105 1106 // MCRegisterInfo initialization routine. 1107 OS << "static inline void Init" << TargetName 1108 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1109 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1110 "{\n" 1111 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1112 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1113 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1114 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1115 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1116 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1117 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1118 << TargetName << "SubRegIdxRanges, " << TargetName 1119 << "RegEncodingTable);\n\n"; 1120 1121 EmitRegMapping(OS, Regs, false); 1122 1123 OS << "}\n\n"; 1124 1125 OS << "} // end namespace llvm\n\n"; 1126 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1127 } 1128 1129 void 1130 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 1131 CodeGenRegBank &RegBank) { 1132 emitSourceFileHeader("Register Information Header Fragment", OS); 1133 1134 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1135 OS << "#undef GET_REGINFO_HEADER\n\n"; 1136 1137 const std::string &TargetName = Target.getName(); 1138 std::string ClassName = TargetName + "GenRegisterInfo"; 1139 1140 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1141 1142 OS << "namespace llvm {\n\n"; 1143 1144 OS << "class " << TargetName << "FrameLowering;\n\n"; 1145 1146 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1147 << " explicit " << ClassName 1148 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1149 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1150 if (!RegBank.getSubRegIndices().empty()) { 1151 OS << " unsigned composeSubRegIndicesImpl" 1152 << "(unsigned, unsigned) const override;\n" 1153 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1154 << "(unsigned, LaneBitmask) const override;\n" 1155 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1156 << "(unsigned, LaneBitmask) const override;\n" 1157 << " const TargetRegisterClass *getSubClassWithSubReg" 1158 << "(const TargetRegisterClass*, unsigned) const override;\n"; 1159 } 1160 OS << " const RegClassWeight &getRegClassWeight(" 1161 << "const TargetRegisterClass *RC) const override;\n" 1162 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1163 << " unsigned getNumRegPressureSets() const override;\n" 1164 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1165 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1166 "Idx) const override;\n" 1167 << " const int *getRegClassPressureSets(" 1168 << "const TargetRegisterClass *RC) const override;\n" 1169 << " const int *getRegUnitPressureSets(" 1170 << "unsigned RegUnit) const override;\n" 1171 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1172 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1173 << " /// Devirtualized TargetFrameLowering.\n" 1174 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1175 << " const MachineFunction &MF);\n" 1176 << "};\n\n"; 1177 1178 const auto &RegisterClasses = RegBank.getRegClasses(); 1179 1180 if (!RegisterClasses.empty()) { 1181 OS << "namespace " << RegisterClasses.front().Namespace 1182 << " { // Register classes\n"; 1183 1184 for (const auto &RC : RegisterClasses) { 1185 const std::string &Name = RC.getName(); 1186 1187 // Output the extern for the instance. 1188 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1189 } 1190 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1191 } 1192 OS << "} // end namespace llvm\n\n"; 1193 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1194 } 1195 1196 // 1197 // runTargetDesc - Output the target register and register file descriptions. 1198 // 1199 void 1200 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 1201 CodeGenRegBank &RegBank){ 1202 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1203 1204 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1205 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1206 1207 OS << "namespace llvm {\n\n"; 1208 1209 // Get access to MCRegisterClass data. 1210 OS << "extern const MCRegisterClass " << Target.getName() 1211 << "MCRegisterClasses[];\n"; 1212 1213 // Start out by emitting each of the register classes. 1214 const auto &RegisterClasses = RegBank.getRegClasses(); 1215 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1216 1217 // Collect all registers belonging to any allocatable class. 1218 std::set<Record*> AllocatableRegs; 1219 1220 // Collect allocatable registers. 1221 for (const auto &RC : RegisterClasses) { 1222 ArrayRef<Record*> Order = RC.getOrder(); 1223 1224 if (RC.Allocatable) 1225 AllocatableRegs.insert(Order.begin(), Order.end()); 1226 } 1227 1228 const CodeGenHwModes &CGH = Target.getHwModes(); 1229 unsigned NumModes = CGH.getNumModeIds(); 1230 1231 // Build a shared array of value types. 1232 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs; 1233 for (unsigned M = 0; M < NumModes; ++M) { 1234 for (const auto &RC : RegisterClasses) { 1235 std::vector<MVT::SimpleValueType> S; 1236 for (const ValueTypeByHwMode &VVT : RC.VTs) 1237 S.push_back(VVT.get(M).SimpleTy); 1238 VTSeqs.add(S); 1239 } 1240 } 1241 VTSeqs.layout(); 1242 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1243 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); 1244 OS << "};\n"; 1245 1246 // Emit SubRegIndex names, skipping 0. 1247 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; 1248 1249 for (const auto &Idx : SubRegIndices) { 1250 OS << Idx.getName(); 1251 OS << "\", \""; 1252 } 1253 OS << "\" };\n\n"; 1254 1255 // Emit SubRegIndex lane masks, including 0. 1256 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1257 "LaneBitmask::getAll(),\n"; 1258 for (const auto &Idx : SubRegIndices) { 1259 printMask(OS << " ", Idx.LaneMask); 1260 OS << ", // " << Idx.getName() << '\n'; 1261 } 1262 OS << " };\n\n"; 1263 1264 OS << "\n"; 1265 1266 // Now that all of the structs have been emitted, emit the instances. 1267 if (!RegisterClasses.empty()) { 1268 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1269 << " = {\n"; 1270 for (unsigned M = 0; M < NumModes; ++M) { 1271 unsigned EV = 0; 1272 OS << " // Mode = " << M << " ("; 1273 if (M == 0) 1274 OS << "Default"; 1275 else 1276 OS << CGH.getMode(M).Name; 1277 OS << ")\n"; 1278 for (const auto &RC : RegisterClasses) { 1279 assert(RC.EnumValue == EV++ && "Unexpected order of register classes"); 1280 (void)EV; 1281 const RegSizeInfo &RI = RC.RSI.get(M); 1282 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1283 << RI.SpillAlignment; 1284 std::vector<MVT::SimpleValueType> VTs; 1285 for (const ValueTypeByHwMode &VVT : RC.VTs) 1286 VTs.push_back(VVT.get(M).SimpleTy); 1287 OS << ", VTLists+" << VTSeqs.get(VTs) << " }, // " 1288 << RC.getName() << '\n'; 1289 } 1290 } 1291 OS << "};\n"; 1292 1293 1294 OS << "\nstatic const TargetRegisterClass *const " 1295 << "NullRegClasses[] = { nullptr };\n\n"; 1296 1297 // Emit register class bit mask tables. The first bit mask emitted for a 1298 // register class, RC, is the set of sub-classes, including RC itself. 1299 // 1300 // If RC has super-registers, also create a list of subreg indices and bit 1301 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1302 // SuperRC, that satisfies: 1303 // 1304 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1305 // 1306 // The 0-terminated list of subreg indices starts at: 1307 // 1308 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1309 // 1310 // The corresponding bitmasks follow the sub-class mask in memory. Each 1311 // mask has RCMaskWords uint32_t entries. 1312 // 1313 // Every bit mask present in the list has at least one bit set. 1314 1315 // Compress the sub-reg index lists. 1316 typedef std::vector<const CodeGenSubRegIndex*> IdxList; 1317 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1318 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1319 BitVector MaskBV(RegisterClasses.size()); 1320 1321 for (const auto &RC : RegisterClasses) { 1322 OS << "static const uint32_t " << RC.getName() 1323 << "SubClassMask[] = {\n "; 1324 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1325 1326 // Emit super-reg class masks for any relevant SubRegIndices that can 1327 // project into RC. 1328 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1329 for (auto &Idx : SubRegIndices) { 1330 MaskBV.reset(); 1331 RC.getSuperRegClasses(&Idx, MaskBV); 1332 if (MaskBV.none()) 1333 continue; 1334 SRIList.push_back(&Idx); 1335 OS << "\n "; 1336 printBitVectorAsHex(OS, MaskBV, 32); 1337 OS << "// " << Idx.getName(); 1338 } 1339 SuperRegIdxSeqs.add(SRIList); 1340 OS << "\n};\n\n"; 1341 } 1342 1343 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1344 SuperRegIdxSeqs.layout(); 1345 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1346 OS << "};\n\n"; 1347 1348 // Emit NULL terminated super-class lists. 1349 for (const auto &RC : RegisterClasses) { 1350 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); 1351 1352 // Skip classes without supers. We can reuse NullRegClasses. 1353 if (Supers.empty()) 1354 continue; 1355 1356 OS << "static const TargetRegisterClass *const " 1357 << RC.getName() << "Superclasses[] = {\n"; 1358 for (const auto *Super : Supers) 1359 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; 1360 OS << " nullptr\n};\n\n"; 1361 } 1362 1363 // Emit methods. 1364 for (const auto &RC : RegisterClasses) { 1365 if (!RC.AltOrderSelect.empty()) { 1366 OS << "\nstatic inline unsigned " << RC.getName() 1367 << "AltOrderSelect(const MachineFunction &MF) {" 1368 << RC.AltOrderSelect << "}\n\n" 1369 << "static ArrayRef<MCPhysReg> " << RC.getName() 1370 << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; 1371 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 1372 ArrayRef<Record*> Elems = RC.getOrder(oi); 1373 if (!Elems.empty()) { 1374 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1375 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1376 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1377 OS << " };\n"; 1378 } 1379 } 1380 OS << " const MCRegisterClass &MCR = " << Target.getName() 1381 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1382 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1383 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 1384 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1385 if (RC.getOrder(oi).empty()) 1386 OS << "),\n ArrayRef<MCPhysReg>("; 1387 else 1388 OS << "),\n makeArrayRef(AltOrder" << oi; 1389 OS << ")\n };\n const unsigned Select = " << RC.getName() 1390 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 1391 << ");\n return Order[Select];\n}\n"; 1392 } 1393 } 1394 1395 // Now emit the actual value-initialized register class instances. 1396 OS << "\nnamespace " << RegisterClasses.front().Namespace 1397 << " { // Register class instances\n"; 1398 1399 for (const auto &RC : RegisterClasses) { 1400 OS << " extern const TargetRegisterClass " << RC.getName() 1401 << "RegClass = {\n " << '&' << Target.getName() 1402 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1403 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1404 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1405 printMask(OS, RC.LaneMask); 1406 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1407 << (RC.HasDisjunctSubRegs?"true":"false") 1408 << ", /* HasDisjunctSubRegs */\n " 1409 << (RC.CoveredBySubRegs?"true":"false") 1410 << ", /* CoveredBySubRegs */\n "; 1411 if (RC.getSuperClasses().empty()) 1412 OS << "NullRegClasses,\n "; 1413 else 1414 OS << RC.getName() << "Superclasses,\n "; 1415 if (RC.AltOrderSelect.empty()) 1416 OS << "nullptr\n"; 1417 else 1418 OS << RC.getName() << "GetRawAllocationOrder\n"; 1419 OS << " };\n\n"; 1420 } 1421 1422 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1423 } 1424 1425 OS << "\nnamespace {\n"; 1426 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 1427 for (const auto &RC : RegisterClasses) 1428 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1429 OS << " };\n"; 1430 OS << "} // end anonymous namespace\n"; 1431 1432 // Emit extra information about registers. 1433 const std::string &TargetName = Target.getName(); 1434 OS << "\nstatic const TargetRegisterInfoDesc " 1435 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; 1436 OS << " { 0, false },\n"; 1437 1438 const auto &Regs = RegBank.getRegisters(); 1439 for (const auto &Reg : Regs) { 1440 OS << " { "; 1441 OS << Reg.CostPerUse << ", " 1442 << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" ) 1443 << " },\n"; 1444 } 1445 OS << "};\n"; // End of register descriptors... 1446 1447 1448 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1449 1450 auto SubRegIndicesSize = 1451 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1452 1453 if (!SubRegIndices.empty()) { 1454 emitComposeSubRegIndices(OS, RegBank, ClassName); 1455 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); 1456 } 1457 1458 // Emit getSubClassWithSubReg. 1459 if (!SubRegIndices.empty()) { 1460 OS << "const TargetRegisterClass *" << ClassName 1461 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1462 << " const {\n"; 1463 // Use the smallest type that can hold a regclass ID with room for a 1464 // sentinel. 1465 if (RegisterClasses.size() < UINT8_MAX) 1466 OS << " static const uint8_t Table["; 1467 else if (RegisterClasses.size() < UINT16_MAX) 1468 OS << " static const uint16_t Table["; 1469 else 1470 PrintFatalError("Too many register classes."); 1471 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1472 for (const auto &RC : RegisterClasses) { 1473 OS << " {\t// " << RC.getName() << "\n"; 1474 for (auto &Idx : SubRegIndices) { 1475 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1476 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1477 << " -> " << SRC->getName() << "\n"; 1478 else 1479 OS << " 0,\t// " << Idx.getName() << "\n"; 1480 } 1481 OS << " },\n"; 1482 } 1483 OS << " };\n assert(RC && \"Missing regclass\");\n" 1484 << " if (!Idx) return RC;\n --Idx;\n" 1485 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1486 << " unsigned TV = Table[RC->getID()][Idx];\n" 1487 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1488 } 1489 1490 EmitRegUnitPressure(OS, RegBank, ClassName); 1491 1492 // Emit the constructor of the class... 1493 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1494 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; 1495 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1496 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1497 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1498 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1499 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1500 OS << "extern const MCRegisterInfo::SubRegCoveredBits " 1501 << TargetName << "SubRegIdxRanges[];\n"; 1502 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1503 1504 EmitRegMappingTables(OS, Regs, true); 1505 1506 OS << ClassName << "::\n" << ClassName 1507 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1508 " unsigned PC, unsigned HwMode)\n" 1509 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 1510 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1511 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n" 1512 << " "; 1513 printMask(OS, RegBank.CoveringLanes); 1514 OS << ", RegClassInfos, HwMode) {\n" 1515 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1516 << ", RA, PC,\n " << TargetName 1517 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1518 << " " << TargetName << "RegUnitRoots,\n" 1519 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1520 << " " << TargetName << "RegDiffLists,\n" 1521 << " " << TargetName << "LaneMaskLists,\n" 1522 << " " << TargetName << "RegStrings,\n" 1523 << " " << TargetName << "RegClassStrings,\n" 1524 << " " << TargetName << "SubRegIdxLists,\n" 1525 << " " << SubRegIndicesSize + 1 << ",\n" 1526 << " " << TargetName << "SubRegIdxRanges,\n" 1527 << " " << TargetName << "RegEncodingTable);\n\n"; 1528 1529 EmitRegMapping(OS, Regs, true); 1530 1531 OS << "}\n\n"; 1532 1533 // Emit CalleeSavedRegs information. 1534 std::vector<Record*> CSRSets = 1535 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1536 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { 1537 Record *CSRSet = CSRSets[i]; 1538 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1539 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1540 1541 // Emit the *_SaveList list of callee-saved registers. 1542 OS << "static const MCPhysReg " << CSRSet->getName() 1543 << "_SaveList[] = { "; 1544 for (unsigned r = 0, re = Regs->size(); r != re; ++r) 1545 OS << getQualifiedName((*Regs)[r]) << ", "; 1546 OS << "0 };\n"; 1547 1548 // Emit the *_RegMask bit mask of call-preserved registers. 1549 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1550 1551 // Check for an optional OtherPreserved set. 1552 // Add those registers to RegMask, but not to SaveList. 1553 if (DagInit *OPDag = 1554 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1555 SetTheory::RecSet OPSet; 1556 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1557 Covered |= RegBank.computeCoveredRegisters( 1558 ArrayRef<Record*>(OPSet.begin(), OPSet.end())); 1559 } 1560 1561 OS << "static const uint32_t " << CSRSet->getName() 1562 << "_RegMask[] = { "; 1563 printBitVectorAsHex(OS, Covered, 32); 1564 OS << "};\n"; 1565 } 1566 OS << "\n\n"; 1567 1568 OS << "ArrayRef<const uint32_t *> " << ClassName 1569 << "::getRegMasks() const {\n"; 1570 if (!CSRSets.empty()) { 1571 OS << " static const uint32_t *const Masks[] = {\n"; 1572 for (Record *CSRSet : CSRSets) 1573 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1574 OS << " };\n"; 1575 OS << " return makeArrayRef(Masks);\n"; 1576 } else { 1577 OS << " return None;\n"; 1578 } 1579 OS << "}\n\n"; 1580 1581 OS << "ArrayRef<const char *> " << ClassName 1582 << "::getRegMaskNames() const {\n"; 1583 if (!CSRSets.empty()) { 1584 OS << " static const char *const Names[] = {\n"; 1585 for (Record *CSRSet : CSRSets) 1586 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1587 OS << " };\n"; 1588 OS << " return makeArrayRef(Names);\n"; 1589 } else { 1590 OS << " return None;\n"; 1591 } 1592 OS << "}\n\n"; 1593 1594 OS << "const " << TargetName << "FrameLowering *\n" << TargetName 1595 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1596 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1597 << " MF.getSubtarget().getFrameLowering());\n" 1598 << "}\n\n"; 1599 1600 OS << "} // end namespace llvm\n\n"; 1601 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1602 } 1603 1604 void RegisterInfoEmitter::run(raw_ostream &OS) { 1605 CodeGenRegBank &RegBank = Target.getRegBank(); 1606 runEnums(OS, Target, RegBank); 1607 runMCDesc(OS, Target, RegBank); 1608 runTargetHeader(OS, Target, RegBank); 1609 runTargetDesc(OS, Target, RegBank); 1610 1611 if (RegisterInfoDebug) 1612 debugDump(errs()); 1613 } 1614 1615 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1616 CodeGenRegBank &RegBank = Target.getRegBank(); 1617 const CodeGenHwModes &CGH = Target.getHwModes(); 1618 unsigned NumModes = CGH.getNumModeIds(); 1619 auto getModeName = [CGH] (unsigned M) -> StringRef { 1620 if (M == 0) 1621 return "Default"; 1622 return CGH.getMode(M).Name; 1623 }; 1624 1625 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1626 OS << "RegisterClass " << RC.getName() << ":\n"; 1627 OS << "\tSpillSize: {"; 1628 for (unsigned M = 0; M != NumModes; ++M) 1629 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1630 OS << " }\n\tSpillAlignment: {"; 1631 for (unsigned M = 0; M != NumModes; ++M) 1632 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1633 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1634 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1635 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1636 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1637 OS << "\tRegs:"; 1638 for (const CodeGenRegister *R : RC.getMembers()) { 1639 OS << " " << R->getName(); 1640 } 1641 OS << '\n'; 1642 OS << "\tSubClasses:"; 1643 const BitVector &SubClasses = RC.getSubClasses(); 1644 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1645 if (!SubClasses.test(SRC.EnumValue)) 1646 continue; 1647 OS << " " << SRC.getName(); 1648 } 1649 OS << '\n'; 1650 OS << "\tSuperClasses:"; 1651 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1652 OS << " " << SRC->getName(); 1653 } 1654 OS << '\n'; 1655 } 1656 1657 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1658 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1659 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1660 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1661 } 1662 1663 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1664 OS << "Register " << R.getName() << ":\n"; 1665 OS << "\tCostPerUse: " << R.CostPerUse << '\n'; 1666 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1667 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1668 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : R.getSubRegs()) { 1669 OS << "\tSubReg " << P.first->getName() 1670 << " = " << P.second->getName() << '\n'; 1671 } 1672 } 1673 } 1674 1675 namespace llvm { 1676 1677 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { 1678 RegisterInfoEmitter(RK).run(OS); 1679 } 1680 1681 } // end namespace llvm 1682