1 //===- WebAssemblyDisassemblerEmitter.cpp - Disassembler tables -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the WebAssembly Disassembler Emitter.
10 // It contains the implementation of the disassembler tables.
11 // Documentation for the disassembler emitter in general can be found in
12 // WebAssemblyDisassemblerEmitter.h.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "WebAssemblyDisassemblerEmitter.h"
17 #include "CodeGenInstruction.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/Support/raw_ostream.h"
20 #include "llvm/TableGen/Record.h"
21 
22 namespace llvm {
23 
24 static constexpr int WebAssemblyInstructionTableSize = 256;
25 
26 void emitWebAssemblyDisassemblerTables(
27     raw_ostream &OS,
28     const ArrayRef<const CodeGenInstruction *> &NumberedInstructions) {
29   // First lets organize all opcodes by (prefix) byte. Prefix 0 is the
30   // starting table.
31   std::map<unsigned,
32            std::map<unsigned, std::pair<unsigned, const CodeGenInstruction *>>>
33       OpcodeTable;
34   for (unsigned I = 0; I != NumberedInstructions.size(); ++I) {
35     auto &CGI = *NumberedInstructions[I];
36     auto &Def = *CGI.TheDef;
37     if (!Def.getValue("Inst"))
38       continue;
39     auto &Inst = *Def.getValueAsBitsInit("Inst");
40     RecordKeeper &RK = Inst.getRecordKeeper();
41     unsigned Opc = static_cast<unsigned>(
42         cast<IntInit>(Inst.convertInitializerTo(IntRecTy::get(RK)))
43             ->getValue());
44     if (Opc == 0xFFFFFFFF)
45       continue; // No opcode defined.
46     assert(Opc <= 0xFFFFFF);
47     unsigned Prefix;
48     if (Opc <= 0xFFFF) {
49       Prefix = Opc >> 8;
50       Opc = Opc & 0xFF;
51     } else {
52       Prefix = Opc >> 16;
53       Opc = Opc & 0xFFFF;
54     }
55     auto &CGIP = OpcodeTable[Prefix][Opc];
56     // All wasm instructions have a StackBased field of type string, we only
57     // want the instructions for which this is "true".
58     bool IsStackBased = Def.getValueAsBit("StackBased");
59     if (!IsStackBased)
60       continue;
61     if (CGIP.second) {
62       // We already have an instruction for this slot, so decide which one
63       // should be the canonical one. This determines which variant gets
64       // printed in a disassembly. We want e.g. "call" not "i32.call", and
65       // "end" when we don't know if its "end_loop" or "end_block" etc.
66       bool IsCanonicalExisting = CGIP.second->TheDef->getValueAsBit("IsCanonical");
67       // We already have one marked explicitly as canonical, so keep it.
68       if (IsCanonicalExisting)
69         continue;
70       bool IsCanonicalNew = Def.getValueAsBit("IsCanonical");
71       // If the new one is explicitly marked as canonical, take it.
72       if (!IsCanonicalNew) {
73         // Neither the existing or new instruction is canonical.
74         // Pick the one with the shortest name as heuristic.
75         // Though ideally IsCanonical is always defined for at least one
76         // variant so this never has to apply.
77         if (CGIP.second->AsmString.size() <= CGI.AsmString.size())
78           continue;
79       }
80     }
81     // Set this instruction as the one to use.
82     CGIP = std::make_pair(I, &CGI);
83   }
84   OS << "#include \"MCTargetDesc/WebAssemblyMCTargetDesc.h\"\n";
85   OS << "\n";
86   OS << "namespace llvm {\n\n";
87   OS << "static constexpr int WebAssemblyInstructionTableSize = ";
88   OS << WebAssemblyInstructionTableSize << ";\n\n";
89   OS << "enum EntryType : uint8_t { ";
90   OS << "ET_Unused, ET_Prefix, ET_Instruction };\n\n";
91   OS << "struct WebAssemblyInstruction {\n";
92   OS << "  uint16_t Opcode;\n";
93   OS << "  EntryType ET;\n";
94   OS << "  uint8_t NumOperands;\n";
95   OS << "  uint16_t OperandStart;\n";
96   OS << "};\n\n";
97   std::vector<std::string> OperandTable, CurOperandList;
98   // Output one table per prefix.
99   for (auto &PrefixPair : OpcodeTable) {
100     if (PrefixPair.second.empty())
101       continue;
102     OS << "WebAssemblyInstruction InstructionTable" << PrefixPair.first;
103     OS << "[] = {\n";
104     for (unsigned I = 0; I < WebAssemblyInstructionTableSize; I++) {
105       auto InstIt = PrefixPair.second.find(I);
106       if (InstIt != PrefixPair.second.end()) {
107         // Regular instruction.
108         assert(InstIt->second.second);
109         auto &CGI = *InstIt->second.second;
110         OS << "  // 0x";
111         OS.write_hex(static_cast<unsigned long long>(I));
112         OS << ": " << CGI.AsmString << "\n";
113         OS << "  { " << InstIt->second.first << ", ET_Instruction, ";
114         OS << CGI.Operands.OperandList.size() << ", ";
115         // Collect operand types for storage in a shared list.
116         CurOperandList.clear();
117         for (auto &Op : CGI.Operands.OperandList) {
118           assert(Op.OperandType != "MCOI::OPERAND_UNKNOWN");
119           CurOperandList.push_back(Op.OperandType);
120         }
121         // See if we already have stored this sequence before. This is not
122         // strictly necessary but makes the table really small.
123         size_t OperandStart = OperandTable.size();
124         if (CurOperandList.size() <= OperandTable.size()) {
125           for (size_t J = 0; J <= OperandTable.size() - CurOperandList.size();
126                ++J) {
127             size_t K = 0;
128             for (; K < CurOperandList.size(); ++K) {
129               if (OperandTable[J + K] != CurOperandList[K]) break;
130             }
131             if (K == CurOperandList.size()) {
132               OperandStart = J;
133               break;
134             }
135           }
136         }
137         // Store operands if no prior occurrence.
138         if (OperandStart == OperandTable.size()) {
139           llvm::append_range(OperandTable, CurOperandList);
140         }
141         OS << OperandStart;
142       } else {
143         auto PrefixIt = OpcodeTable.find(I);
144         // If we have a non-empty table for it that's not 0, this is a prefix.
145         if (PrefixIt != OpcodeTable.end() && I && !PrefixPair.first) {
146           OS << "  { 0, ET_Prefix, 0, 0";
147         } else {
148           OS << "  { 0, ET_Unused, 0, 0";
149         }
150       }
151       OS << "  },\n";
152     }
153     OS << "};\n\n";
154   }
155   // Create a table of all operands:
156   OS << "const uint8_t OperandTable[] = {\n";
157   for (auto &Op : OperandTable) {
158     OS << "  " << Op << ",\n";
159   }
160   OS << "};\n\n";
161   // Create a table of all extension tables:
162   OS << "struct { uint8_t Prefix; const WebAssemblyInstruction *Table; }\n";
163   OS << "PrefixTable[] = {\n";
164   for (auto &PrefixPair : OpcodeTable) {
165     if (PrefixPair.second.empty() || !PrefixPair.first)
166       continue;
167     OS << "  { " << PrefixPair.first << ", InstructionTable"
168        << PrefixPair.first;
169     OS << " },\n";
170   }
171   OS << "  { 0, nullptr }\n};\n\n";
172   OS << "} // end namespace llvm\n";
173 }
174 
175 } // namespace llvm
176