1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86ModRMFilters.h" 19 #include "llvm/Support/ErrorHandling.h" 20 #include <string> 21 22 using namespace llvm; 23 using namespace X86Disassembler; 24 25 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 26 /// Useful for switch statements and the like. 27 /// 28 /// @param init - A reference to the BitsInit to be decoded. 29 /// @return - The field, with the first bit in the BitsInit as the lowest 30 /// order bit. 31 static uint8_t byteFromBitsInit(BitsInit &init) { 32 int width = init.getNumBits(); 33 34 assert(width <= 8 && "Field is too large for uint8_t!"); 35 36 int index; 37 uint8_t mask = 0x01; 38 39 uint8_t ret = 0; 40 41 for (index = 0; index < width; index++) { 42 if (cast<BitInit>(init.getBit(index))->getValue()) 43 ret |= mask; 44 45 mask <<= 1; 46 } 47 48 return ret; 49 } 50 51 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 52 /// name of the field. 53 /// 54 /// @param rec - The record from which to extract the value. 55 /// @param name - The name of the field in the record. 56 /// @return - The field, as translated by byteFromBitsInit(). 57 static uint8_t byteFromRec(const Record* rec, const std::string &name) { 58 BitsInit* bits = rec->getValueAsBitsInit(name); 59 return byteFromBitsInit(*bits); 60 } 61 62 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 63 const CodeGenInstruction &insn, 64 InstrUID uid) { 65 UID = uid; 66 67 Rec = insn.TheDef; 68 Name = Rec->getName(); 69 Spec = &tables.specForUID(UID); 70 71 if (!Rec->isSubClassOf("X86Inst")) { 72 ShouldBeEmitted = false; 73 return; 74 } 75 76 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 77 OpMap = byteFromRec(Rec, "OpMapBits"); 78 Opcode = byteFromRec(Rec, "Opcode"); 79 Form = byteFromRec(Rec, "FormBits"); 80 Encoding = byteFromRec(Rec, "OpEncBits"); 81 82 OpSize = byteFromRec(Rec, "OpSizeBits"); 83 AdSize = byteFromRec(Rec, "AdSizeBits"); 84 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 85 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 86 HasVEX_W = Rec->getValueAsBit("HasVEX_W"); 87 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W"); 88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 93 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 94 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 95 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 96 97 Name = Rec->getName(); 98 99 Operands = &insn.Operands.OperandList; 100 101 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 102 103 EncodeRC = HasEVEX_B && 104 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 105 106 // Check for 64-bit inst which does not require REX 107 Is32Bit = false; 108 Is64Bit = false; 109 // FIXME: Is there some better way to check for In64BitMode? 110 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 111 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 112 if (Predicates[i]->getName().find("Not64Bit") != Name.npos || 113 Predicates[i]->getName().find("In32Bit") != Name.npos) { 114 Is32Bit = true; 115 break; 116 } 117 if (Predicates[i]->getName().find("In64Bit") != Name.npos) { 118 Is64Bit = true; 119 break; 120 } 121 } 122 123 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 124 ShouldBeEmitted = false; 125 return; 126 } 127 128 // Special case since there is no attribute class for 64-bit and VEX 129 if (Name == "VMASKMOVDQU64") { 130 ShouldBeEmitted = false; 131 return; 132 } 133 134 ShouldBeEmitted = true; 135 } 136 137 void RecognizableInstr::processInstr(DisassemblerTables &tables, 138 const CodeGenInstruction &insn, 139 InstrUID uid) 140 { 141 // Ignore "asm parser only" instructions. 142 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 143 return; 144 145 RecognizableInstr recogInstr(tables, insn, uid); 146 147 if (recogInstr.shouldBeEmitted()) { 148 recogInstr.emitInstructionSpecifier(); 149 recogInstr.emitDecodePath(tables); 150 } 151 } 152 153 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 154 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 155 (HasEVEX_KZ ? n##_KZ : \ 156 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 157 158 InstructionContext RecognizableInstr::insnContext() const { 159 InstructionContext insnContext; 160 161 if (Encoding == X86Local::EVEX) { 162 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 165 } 166 // VEX_L & VEX_W 167 if (!EncodeRC && HasVEX_LPrefix && HasVEX_W) { 168 if (OpPrefix == X86Local::PD) 169 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 170 else if (OpPrefix == X86Local::XS) 171 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 172 else if (OpPrefix == X86Local::XD) 173 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 174 else if (OpPrefix == X86Local::PS) 175 insnContext = EVEX_KB(IC_EVEX_L_W); 176 else { 177 errs() << "Instruction does not use a prefix: " << Name << "\n"; 178 llvm_unreachable("Invalid prefix"); 179 } 180 } else if (!EncodeRC && HasVEX_LPrefix) { 181 // VEX_L 182 if (OpPrefix == X86Local::PD) 183 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 184 else if (OpPrefix == X86Local::XS) 185 insnContext = EVEX_KB(IC_EVEX_L_XS); 186 else if (OpPrefix == X86Local::XD) 187 insnContext = EVEX_KB(IC_EVEX_L_XD); 188 else if (OpPrefix == X86Local::PS) 189 insnContext = EVEX_KB(IC_EVEX_L); 190 else { 191 errs() << "Instruction does not use a prefix: " << Name << "\n"; 192 llvm_unreachable("Invalid prefix"); 193 } 194 } else if (!EncodeRC && HasEVEX_L2Prefix && HasVEX_W) { 195 // EVEX_L2 & VEX_W 196 if (OpPrefix == X86Local::PD) 197 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 198 else if (OpPrefix == X86Local::XS) 199 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 200 else if (OpPrefix == X86Local::XD) 201 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 202 else if (OpPrefix == X86Local::PS) 203 insnContext = EVEX_KB(IC_EVEX_L2_W); 204 else { 205 errs() << "Instruction does not use a prefix: " << Name << "\n"; 206 llvm_unreachable("Invalid prefix"); 207 } 208 } else if (!EncodeRC && HasEVEX_L2Prefix) { 209 // EVEX_L2 210 if (OpPrefix == X86Local::PD) 211 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 212 else if (OpPrefix == X86Local::XD) 213 insnContext = EVEX_KB(IC_EVEX_L2_XD); 214 else if (OpPrefix == X86Local::XS) 215 insnContext = EVEX_KB(IC_EVEX_L2_XS); 216 else if (OpPrefix == X86Local::PS) 217 insnContext = EVEX_KB(IC_EVEX_L2); 218 else { 219 errs() << "Instruction does not use a prefix: " << Name << "\n"; 220 llvm_unreachable("Invalid prefix"); 221 } 222 } 223 else if (HasVEX_W) { 224 // VEX_W 225 if (OpPrefix == X86Local::PD) 226 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 227 else if (OpPrefix == X86Local::XS) 228 insnContext = EVEX_KB(IC_EVEX_W_XS); 229 else if (OpPrefix == X86Local::XD) 230 insnContext = EVEX_KB(IC_EVEX_W_XD); 231 else if (OpPrefix == X86Local::PS) 232 insnContext = EVEX_KB(IC_EVEX_W); 233 else { 234 errs() << "Instruction does not use a prefix: " << Name << "\n"; 235 llvm_unreachable("Invalid prefix"); 236 } 237 } 238 // No L, no W 239 else if (OpPrefix == X86Local::PD) 240 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 241 else if (OpPrefix == X86Local::XD) 242 insnContext = EVEX_KB(IC_EVEX_XD); 243 else if (OpPrefix == X86Local::XS) 244 insnContext = EVEX_KB(IC_EVEX_XS); 245 else if (OpPrefix == X86Local::PS) 246 insnContext = EVEX_KB(IC_EVEX); 247 else { 248 errs() << "Instruction does not use a prefix: " << Name << "\n"; 249 llvm_unreachable("Invalid prefix"); 250 } 251 /// eof EVEX 252 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 253 if (HasVEX_LPrefix && HasVEX_W) { 254 if (OpPrefix == X86Local::PD) 255 insnContext = IC_VEX_L_W_OPSIZE; 256 else if (OpPrefix == X86Local::XS) 257 insnContext = IC_VEX_L_W_XS; 258 else if (OpPrefix == X86Local::XD) 259 insnContext = IC_VEX_L_W_XD; 260 else if (OpPrefix == X86Local::PS) 261 insnContext = IC_VEX_L_W; 262 else { 263 errs() << "Instruction does not use a prefix: " << Name << "\n"; 264 llvm_unreachable("Invalid prefix"); 265 } 266 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 267 insnContext = IC_VEX_L_OPSIZE; 268 else if (OpPrefix == X86Local::PD && HasVEX_W) 269 insnContext = IC_VEX_W_OPSIZE; 270 else if (OpPrefix == X86Local::PD) 271 insnContext = IC_VEX_OPSIZE; 272 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 273 insnContext = IC_VEX_L_XS; 274 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 275 insnContext = IC_VEX_L_XD; 276 else if (HasVEX_W && OpPrefix == X86Local::XS) 277 insnContext = IC_VEX_W_XS; 278 else if (HasVEX_W && OpPrefix == X86Local::XD) 279 insnContext = IC_VEX_W_XD; 280 else if (HasVEX_W && OpPrefix == X86Local::PS) 281 insnContext = IC_VEX_W; 282 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 283 insnContext = IC_VEX_L; 284 else if (OpPrefix == X86Local::XD) 285 insnContext = IC_VEX_XD; 286 else if (OpPrefix == X86Local::XS) 287 insnContext = IC_VEX_XS; 288 else if (OpPrefix == X86Local::PS) 289 insnContext = IC_VEX; 290 else { 291 errs() << "Instruction does not use a prefix: " << Name << "\n"; 292 llvm_unreachable("Invalid prefix"); 293 } 294 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 295 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 296 insnContext = IC_64BIT_REXW_OPSIZE; 297 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 298 insnContext = IC_64BIT_REXW_ADSIZE; 299 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 300 insnContext = IC_64BIT_XD_OPSIZE; 301 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 302 insnContext = IC_64BIT_XS_OPSIZE; 303 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 304 insnContext = IC_64BIT_OPSIZE_ADSIZE; 305 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 306 insnContext = IC_64BIT_OPSIZE_ADSIZE; 307 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 308 insnContext = IC_64BIT_OPSIZE; 309 else if (AdSize == X86Local::AdSize32) 310 insnContext = IC_64BIT_ADSIZE; 311 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 312 insnContext = IC_64BIT_REXW_XS; 313 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 314 insnContext = IC_64BIT_REXW_XD; 315 else if (OpPrefix == X86Local::XD) 316 insnContext = IC_64BIT_XD; 317 else if (OpPrefix == X86Local::XS) 318 insnContext = IC_64BIT_XS; 319 else if (HasREX_WPrefix) 320 insnContext = IC_64BIT_REXW; 321 else 322 insnContext = IC_64BIT; 323 } else { 324 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 325 insnContext = IC_XD_OPSIZE; 326 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 327 insnContext = IC_XS_OPSIZE; 328 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 329 insnContext = IC_XD_ADSIZE; 330 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 331 insnContext = IC_XS_ADSIZE; 332 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 333 insnContext = IC_OPSIZE_ADSIZE; 334 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 335 insnContext = IC_OPSIZE_ADSIZE; 336 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 337 insnContext = IC_OPSIZE; 338 else if (AdSize == X86Local::AdSize16) 339 insnContext = IC_ADSIZE; 340 else if (OpPrefix == X86Local::XD) 341 insnContext = IC_XD; 342 else if (OpPrefix == X86Local::XS) 343 insnContext = IC_XS; 344 else 345 insnContext = IC; 346 } 347 348 return insnContext; 349 } 350 351 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 352 // The scaling factor for AVX512 compressed displacement encoding is an 353 // instruction attribute. Adjust the ModRM encoding type to include the 354 // scale for compressed displacement. 355 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0) 356 return; 357 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 358 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 359 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 360 "Invalid CDisp scaling"); 361 } 362 363 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 364 unsigned &physicalOperandIndex, 365 unsigned numPhysicalOperands, 366 const unsigned *operandMapping, 367 OperandEncoding (*encodingFromString) 368 (const std::string&, 369 uint8_t OpSize)) { 370 if (optional) { 371 if (physicalOperandIndex >= numPhysicalOperands) 372 return; 373 } else { 374 assert(physicalOperandIndex < numPhysicalOperands); 375 } 376 377 while (operandMapping[operandIndex] != operandIndex) { 378 Spec->operands[operandIndex].encoding = ENCODING_DUP; 379 Spec->operands[operandIndex].type = 380 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 381 ++operandIndex; 382 } 383 384 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 385 386 OperandEncoding encoding = encodingFromString(typeName, OpSize); 387 // Adjust the encoding type for an operand based on the instruction. 388 adjustOperandEncoding(encoding); 389 Spec->operands[operandIndex].encoding = encoding; 390 Spec->operands[operandIndex].type = typeFromString(typeName, 391 HasREX_WPrefix, OpSize); 392 393 ++operandIndex; 394 ++physicalOperandIndex; 395 } 396 397 void RecognizableInstr::emitInstructionSpecifier() { 398 Spec->name = Name; 399 400 Spec->insnContext = insnContext(); 401 402 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 403 404 unsigned numOperands = OperandList.size(); 405 unsigned numPhysicalOperands = 0; 406 407 // operandMapping maps from operands in OperandList to their originals. 408 // If operandMapping[i] != i, then the entry is a duplicate. 409 unsigned operandMapping[X86_MAX_OPERANDS]; 410 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 411 412 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 413 if (!OperandList[operandIndex].Constraints.empty()) { 414 const CGIOperandList::ConstraintInfo &Constraint = 415 OperandList[operandIndex].Constraints[0]; 416 if (Constraint.isTied()) { 417 operandMapping[operandIndex] = operandIndex; 418 operandMapping[Constraint.getTiedOperand()] = operandIndex; 419 } else { 420 ++numPhysicalOperands; 421 operandMapping[operandIndex] = operandIndex; 422 } 423 } else { 424 ++numPhysicalOperands; 425 operandMapping[operandIndex] = operandIndex; 426 } 427 } 428 429 #define HANDLE_OPERAND(class) \ 430 handleOperand(false, \ 431 operandIndex, \ 432 physicalOperandIndex, \ 433 numPhysicalOperands, \ 434 operandMapping, \ 435 class##EncodingFromString); 436 437 #define HANDLE_OPTIONAL(class) \ 438 handleOperand(true, \ 439 operandIndex, \ 440 physicalOperandIndex, \ 441 numPhysicalOperands, \ 442 operandMapping, \ 443 class##EncodingFromString); 444 445 // operandIndex should always be < numOperands 446 unsigned operandIndex = 0; 447 // physicalOperandIndex should always be < numPhysicalOperands 448 unsigned physicalOperandIndex = 0; 449 450 #ifndef NDEBUG 451 // Given the set of prefix bits, how many additional operands does the 452 // instruction have? 453 unsigned additionalOperands = 0; 454 if (HasVEX_4V) 455 ++additionalOperands; 456 if (HasEVEX_K) 457 ++additionalOperands; 458 #endif 459 460 switch (Form) { 461 default: llvm_unreachable("Unhandled form"); 462 case X86Local::RawFrmSrc: 463 HANDLE_OPERAND(relocation); 464 return; 465 case X86Local::RawFrmDst: 466 HANDLE_OPERAND(relocation); 467 return; 468 case X86Local::RawFrmDstSrc: 469 HANDLE_OPERAND(relocation); 470 HANDLE_OPERAND(relocation); 471 return; 472 case X86Local::RawFrm: 473 // Operand 1 (optional) is an address or immediate. 474 assert(numPhysicalOperands <= 1 && 475 "Unexpected number of operands for RawFrm"); 476 HANDLE_OPTIONAL(relocation) 477 break; 478 case X86Local::RawFrmMemOffs: 479 // Operand 1 is an address. 480 HANDLE_OPERAND(relocation); 481 break; 482 case X86Local::AddRegFrm: 483 // Operand 1 is added to the opcode. 484 // Operand 2 (optional) is an address. 485 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 486 "Unexpected number of operands for AddRegFrm"); 487 HANDLE_OPERAND(opcodeModifier) 488 HANDLE_OPTIONAL(relocation) 489 break; 490 case X86Local::AddCCFrm: 491 // Operand 1 (optional) is an address or immediate. 492 assert(numPhysicalOperands == 2 && 493 "Unexpected number of operands for AddCCFrm"); 494 HANDLE_OPERAND(relocation) 495 HANDLE_OPERAND(opcodeModifier) 496 break; 497 case X86Local::MRMDestReg: 498 // Operand 1 is a register operand in the R/M field. 499 // - In AVX512 there may be a mask operand here - 500 // Operand 2 is a register operand in the Reg/Opcode field. 501 // - In AVX, there is a register operand in the VEX.vvvv field here - 502 // Operand 3 (optional) is an immediate. 503 assert(numPhysicalOperands >= 2 + additionalOperands && 504 numPhysicalOperands <= 3 + additionalOperands && 505 "Unexpected number of operands for MRMDestRegFrm"); 506 507 HANDLE_OPERAND(rmRegister) 508 if (HasEVEX_K) 509 HANDLE_OPERAND(writemaskRegister) 510 511 if (HasVEX_4V) 512 // FIXME: In AVX, the register below becomes the one encoded 513 // in ModRMVEX and the one above the one in the VEX.VVVV field 514 HANDLE_OPERAND(vvvvRegister) 515 516 HANDLE_OPERAND(roRegister) 517 HANDLE_OPTIONAL(immediate) 518 break; 519 case X86Local::MRMDestMem: 520 // Operand 1 is a memory operand (possibly SIB-extended) 521 // Operand 2 is a register operand in the Reg/Opcode field. 522 // - In AVX, there is a register operand in the VEX.vvvv field here - 523 // Operand 3 (optional) is an immediate. 524 assert(numPhysicalOperands >= 2 + additionalOperands && 525 numPhysicalOperands <= 3 + additionalOperands && 526 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 527 528 HANDLE_OPERAND(memory) 529 530 if (HasEVEX_K) 531 HANDLE_OPERAND(writemaskRegister) 532 533 if (HasVEX_4V) 534 // FIXME: In AVX, the register below becomes the one encoded 535 // in ModRMVEX and the one above the one in the VEX.VVVV field 536 HANDLE_OPERAND(vvvvRegister) 537 538 HANDLE_OPERAND(roRegister) 539 HANDLE_OPTIONAL(immediate) 540 break; 541 case X86Local::MRMSrcReg: 542 // Operand 1 is a register operand in the Reg/Opcode field. 543 // Operand 2 is a register operand in the R/M field. 544 // - In AVX, there is a register operand in the VEX.vvvv field here - 545 // Operand 3 (optional) is an immediate. 546 // Operand 4 (optional) is an immediate. 547 548 assert(numPhysicalOperands >= 2 + additionalOperands && 549 numPhysicalOperands <= 4 + additionalOperands && 550 "Unexpected number of operands for MRMSrcRegFrm"); 551 552 HANDLE_OPERAND(roRegister) 553 554 if (HasEVEX_K) 555 HANDLE_OPERAND(writemaskRegister) 556 557 if (HasVEX_4V) 558 // FIXME: In AVX, the register below becomes the one encoded 559 // in ModRMVEX and the one above the one in the VEX.VVVV field 560 HANDLE_OPERAND(vvvvRegister) 561 562 HANDLE_OPERAND(rmRegister) 563 HANDLE_OPTIONAL(immediate) 564 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 565 break; 566 case X86Local::MRMSrcReg4VOp3: 567 assert(numPhysicalOperands == 3 && 568 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 569 HANDLE_OPERAND(roRegister) 570 HANDLE_OPERAND(rmRegister) 571 HANDLE_OPERAND(vvvvRegister) 572 break; 573 case X86Local::MRMSrcRegOp4: 574 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 575 "Unexpected number of operands for MRMSrcRegOp4Frm"); 576 HANDLE_OPERAND(roRegister) 577 HANDLE_OPERAND(vvvvRegister) 578 HANDLE_OPERAND(immediate) // Register in imm[7:4] 579 HANDLE_OPERAND(rmRegister) 580 HANDLE_OPTIONAL(immediate) 581 break; 582 case X86Local::MRMSrcRegCC: 583 assert(numPhysicalOperands == 3 && 584 "Unexpected number of operands for MRMSrcRegCC"); 585 HANDLE_OPERAND(roRegister) 586 HANDLE_OPERAND(rmRegister) 587 HANDLE_OPERAND(opcodeModifier) 588 break; 589 case X86Local::MRMSrcMem: 590 // Operand 1 is a register operand in the Reg/Opcode field. 591 // Operand 2 is a memory operand (possibly SIB-extended) 592 // - In AVX, there is a register operand in the VEX.vvvv field here - 593 // Operand 3 (optional) is an immediate. 594 595 assert(numPhysicalOperands >= 2 + additionalOperands && 596 numPhysicalOperands <= 4 + additionalOperands && 597 "Unexpected number of operands for MRMSrcMemFrm"); 598 599 HANDLE_OPERAND(roRegister) 600 601 if (HasEVEX_K) 602 HANDLE_OPERAND(writemaskRegister) 603 604 if (HasVEX_4V) 605 // FIXME: In AVX, the register below becomes the one encoded 606 // in ModRMVEX and the one above the one in the VEX.VVVV field 607 HANDLE_OPERAND(vvvvRegister) 608 609 HANDLE_OPERAND(memory) 610 HANDLE_OPTIONAL(immediate) 611 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 612 break; 613 case X86Local::MRMSrcMem4VOp3: 614 assert(numPhysicalOperands == 3 && 615 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 616 HANDLE_OPERAND(roRegister) 617 HANDLE_OPERAND(memory) 618 HANDLE_OPERAND(vvvvRegister) 619 break; 620 case X86Local::MRMSrcMemOp4: 621 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 622 "Unexpected number of operands for MRMSrcMemOp4Frm"); 623 HANDLE_OPERAND(roRegister) 624 HANDLE_OPERAND(vvvvRegister) 625 HANDLE_OPERAND(immediate) // Register in imm[7:4] 626 HANDLE_OPERAND(memory) 627 HANDLE_OPTIONAL(immediate) 628 break; 629 case X86Local::MRMSrcMemCC: 630 assert(numPhysicalOperands == 3 && 631 "Unexpected number of operands for MRMSrcMemCC"); 632 HANDLE_OPERAND(roRegister) 633 HANDLE_OPERAND(memory) 634 HANDLE_OPERAND(opcodeModifier) 635 break; 636 case X86Local::MRMXrCC: 637 assert(numPhysicalOperands == 2 && 638 "Unexpected number of operands for MRMXrCC"); 639 HANDLE_OPERAND(rmRegister) 640 HANDLE_OPERAND(opcodeModifier) 641 break; 642 case X86Local::MRMXr: 643 case X86Local::MRM0r: 644 case X86Local::MRM1r: 645 case X86Local::MRM2r: 646 case X86Local::MRM3r: 647 case X86Local::MRM4r: 648 case X86Local::MRM5r: 649 case X86Local::MRM6r: 650 case X86Local::MRM7r: 651 // Operand 1 is a register operand in the R/M field. 652 // Operand 2 (optional) is an immediate or relocation. 653 // Operand 3 (optional) is an immediate. 654 assert(numPhysicalOperands >= 0 + additionalOperands && 655 numPhysicalOperands <= 3 + additionalOperands && 656 "Unexpected number of operands for MRMnr"); 657 658 if (HasVEX_4V) 659 HANDLE_OPERAND(vvvvRegister) 660 661 if (HasEVEX_K) 662 HANDLE_OPERAND(writemaskRegister) 663 HANDLE_OPTIONAL(rmRegister) 664 HANDLE_OPTIONAL(relocation) 665 HANDLE_OPTIONAL(immediate) 666 break; 667 case X86Local::MRMXmCC: 668 assert(numPhysicalOperands == 2 && 669 "Unexpected number of operands for MRMXm"); 670 HANDLE_OPERAND(memory) 671 HANDLE_OPERAND(opcodeModifier) 672 break; 673 case X86Local::MRMXm: 674 case X86Local::MRM0m: 675 case X86Local::MRM1m: 676 case X86Local::MRM2m: 677 case X86Local::MRM3m: 678 case X86Local::MRM4m: 679 case X86Local::MRM5m: 680 case X86Local::MRM6m: 681 case X86Local::MRM7m: 682 // Operand 1 is a memory operand (possibly SIB-extended) 683 // Operand 2 (optional) is an immediate or relocation. 684 assert(numPhysicalOperands >= 1 + additionalOperands && 685 numPhysicalOperands <= 2 + additionalOperands && 686 "Unexpected number of operands for MRMnm"); 687 688 if (HasVEX_4V) 689 HANDLE_OPERAND(vvvvRegister) 690 if (HasEVEX_K) 691 HANDLE_OPERAND(writemaskRegister) 692 HANDLE_OPERAND(memory) 693 HANDLE_OPTIONAL(relocation) 694 break; 695 case X86Local::RawFrmImm8: 696 // operand 1 is a 16-bit immediate 697 // operand 2 is an 8-bit immediate 698 assert(numPhysicalOperands == 2 && 699 "Unexpected number of operands for X86Local::RawFrmImm8"); 700 HANDLE_OPERAND(immediate) 701 HANDLE_OPERAND(immediate) 702 break; 703 case X86Local::RawFrmImm16: 704 // operand 1 is a 16-bit immediate 705 // operand 2 is a 16-bit immediate 706 HANDLE_OPERAND(immediate) 707 HANDLE_OPERAND(immediate) 708 break; 709 #define MAP(from, to) case X86Local::MRM_##from: 710 X86_INSTR_MRM_MAPPING 711 #undef MAP 712 HANDLE_OPTIONAL(relocation) 713 break; 714 } 715 716 #undef HANDLE_OPERAND 717 #undef HANDLE_OPTIONAL 718 } 719 720 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 721 // Special cases where the LLVM tables are not complete 722 723 #define MAP(from, to) \ 724 case X86Local::MRM_##from: 725 726 llvm::Optional<OpcodeType> opcodeType; 727 switch (OpMap) { 728 default: llvm_unreachable("Invalid map!"); 729 case X86Local::OB: opcodeType = ONEBYTE; break; 730 case X86Local::TB: opcodeType = TWOBYTE; break; 731 case X86Local::T8: opcodeType = THREEBYTE_38; break; 732 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 733 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 734 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 735 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 736 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 737 } 738 739 std::unique_ptr<ModRMFilter> filter; 740 switch (Form) { 741 default: llvm_unreachable("Invalid form!"); 742 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 743 case X86Local::RawFrm: 744 case X86Local::AddRegFrm: 745 case X86Local::RawFrmMemOffs: 746 case X86Local::RawFrmSrc: 747 case X86Local::RawFrmDst: 748 case X86Local::RawFrmDstSrc: 749 case X86Local::RawFrmImm8: 750 case X86Local::RawFrmImm16: 751 case X86Local::AddCCFrm: 752 filter = std::make_unique<DumbFilter>(); 753 break; 754 case X86Local::MRMDestReg: 755 case X86Local::MRMSrcReg: 756 case X86Local::MRMSrcReg4VOp3: 757 case X86Local::MRMSrcRegOp4: 758 case X86Local::MRMSrcRegCC: 759 case X86Local::MRMXrCC: 760 case X86Local::MRMXr: 761 filter = std::make_unique<ModFilter>(true); 762 break; 763 case X86Local::MRMDestMem: 764 case X86Local::MRMSrcMem: 765 case X86Local::MRMSrcMem4VOp3: 766 case X86Local::MRMSrcMemOp4: 767 case X86Local::MRMSrcMemCC: 768 case X86Local::MRMXmCC: 769 case X86Local::MRMXm: 770 filter = std::make_unique<ModFilter>(false); 771 break; 772 case X86Local::MRM0r: case X86Local::MRM1r: 773 case X86Local::MRM2r: case X86Local::MRM3r: 774 case X86Local::MRM4r: case X86Local::MRM5r: 775 case X86Local::MRM6r: case X86Local::MRM7r: 776 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 777 break; 778 case X86Local::MRM0m: case X86Local::MRM1m: 779 case X86Local::MRM2m: case X86Local::MRM3m: 780 case X86Local::MRM4m: case X86Local::MRM5m: 781 case X86Local::MRM6m: case X86Local::MRM7m: 782 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 783 break; 784 X86_INSTR_MRM_MAPPING 785 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 786 break; 787 } // switch (Form) 788 789 uint8_t opcodeToSet = Opcode; 790 791 unsigned AddressSize = 0; 792 switch (AdSize) { 793 case X86Local::AdSize16: AddressSize = 16; break; 794 case X86Local::AdSize32: AddressSize = 32; break; 795 case X86Local::AdSize64: AddressSize = 64; break; 796 } 797 798 assert(opcodeType && "Opcode type not set"); 799 assert(filter && "Filter not set"); 800 801 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 802 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 803 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { 804 unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16; 805 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 806 807 uint8_t currentOpcode; 808 809 for (currentOpcode = opcodeToSet; currentOpcode < opcodeToSet + Count; 810 ++currentOpcode) 811 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 812 UID, Is32Bit, OpPrefix == 0, 813 IgnoresVEX_L || EncodeRC, 814 IgnoresVEX_W, AddressSize); 815 } else { 816 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 817 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 818 IgnoresVEX_W, AddressSize); 819 } 820 821 #undef MAP 822 } 823 824 #define TYPE(str, type) if (s == str) return type; 825 OperandType RecognizableInstr::typeFromString(const std::string &s, 826 bool hasREX_WPrefix, 827 uint8_t OpSize) { 828 if(hasREX_WPrefix) { 829 // For instructions with a REX_W prefix, a declared 32-bit register encoding 830 // is special. 831 TYPE("GR32", TYPE_R32) 832 } 833 if(OpSize == X86Local::OpSize16) { 834 // For OpSize16 instructions, a declared 16-bit register or 835 // immediate encoding is special. 836 TYPE("GR16", TYPE_Rv) 837 } else if(OpSize == X86Local::OpSize32) { 838 // For OpSize32 instructions, a declared 32-bit register or 839 // immediate encoding is special. 840 TYPE("GR32", TYPE_Rv) 841 } 842 TYPE("i16mem", TYPE_M) 843 TYPE("i16imm", TYPE_IMM) 844 TYPE("i16i8imm", TYPE_IMM) 845 TYPE("GR16", TYPE_R16) 846 TYPE("i32mem", TYPE_M) 847 TYPE("i32imm", TYPE_IMM) 848 TYPE("i32i8imm", TYPE_IMM) 849 TYPE("GR32", TYPE_R32) 850 TYPE("GR32orGR64", TYPE_R32) 851 TYPE("i64mem", TYPE_M) 852 TYPE("i64i32imm", TYPE_IMM) 853 TYPE("i64i8imm", TYPE_IMM) 854 TYPE("GR64", TYPE_R64) 855 TYPE("i8mem", TYPE_M) 856 TYPE("i8imm", TYPE_IMM) 857 TYPE("u4imm", TYPE_UIMM8) 858 TYPE("u8imm", TYPE_UIMM8) 859 TYPE("i16u8imm", TYPE_UIMM8) 860 TYPE("i32u8imm", TYPE_UIMM8) 861 TYPE("i64u8imm", TYPE_UIMM8) 862 TYPE("GR8", TYPE_R8) 863 TYPE("VR128", TYPE_XMM) 864 TYPE("VR128X", TYPE_XMM) 865 TYPE("f128mem", TYPE_M) 866 TYPE("f256mem", TYPE_M) 867 TYPE("f512mem", TYPE_M) 868 TYPE("FR128", TYPE_XMM) 869 TYPE("FR64", TYPE_XMM) 870 TYPE("FR64X", TYPE_XMM) 871 TYPE("f64mem", TYPE_M) 872 TYPE("sdmem", TYPE_M) 873 TYPE("FR32", TYPE_XMM) 874 TYPE("FR32X", TYPE_XMM) 875 TYPE("f32mem", TYPE_M) 876 TYPE("ssmem", TYPE_M) 877 TYPE("RST", TYPE_ST) 878 TYPE("RSTi", TYPE_ST) 879 TYPE("i128mem", TYPE_M) 880 TYPE("i256mem", TYPE_M) 881 TYPE("i512mem", TYPE_M) 882 TYPE("i64i32imm_brtarget", TYPE_REL) 883 TYPE("i16imm_brtarget", TYPE_REL) 884 TYPE("i32imm_brtarget", TYPE_REL) 885 TYPE("ccode", TYPE_IMM) 886 TYPE("AVX512RC", TYPE_IMM) 887 TYPE("brtarget32", TYPE_REL) 888 TYPE("brtarget16", TYPE_REL) 889 TYPE("brtarget8", TYPE_REL) 890 TYPE("f80mem", TYPE_M) 891 TYPE("lea64_32mem", TYPE_M) 892 TYPE("lea64mem", TYPE_M) 893 TYPE("VR64", TYPE_MM64) 894 TYPE("i64imm", TYPE_IMM) 895 TYPE("anymem", TYPE_M) 896 TYPE("opaquemem", TYPE_M) 897 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 898 TYPE("DEBUG_REG", TYPE_DEBUGREG) 899 TYPE("CONTROL_REG", TYPE_CONTROLREG) 900 TYPE("srcidx8", TYPE_SRCIDX) 901 TYPE("srcidx16", TYPE_SRCIDX) 902 TYPE("srcidx32", TYPE_SRCIDX) 903 TYPE("srcidx64", TYPE_SRCIDX) 904 TYPE("dstidx8", TYPE_DSTIDX) 905 TYPE("dstidx16", TYPE_DSTIDX) 906 TYPE("dstidx32", TYPE_DSTIDX) 907 TYPE("dstidx64", TYPE_DSTIDX) 908 TYPE("offset16_8", TYPE_MOFFS) 909 TYPE("offset16_16", TYPE_MOFFS) 910 TYPE("offset16_32", TYPE_MOFFS) 911 TYPE("offset32_8", TYPE_MOFFS) 912 TYPE("offset32_16", TYPE_MOFFS) 913 TYPE("offset32_32", TYPE_MOFFS) 914 TYPE("offset32_64", TYPE_MOFFS) 915 TYPE("offset64_8", TYPE_MOFFS) 916 TYPE("offset64_16", TYPE_MOFFS) 917 TYPE("offset64_32", TYPE_MOFFS) 918 TYPE("offset64_64", TYPE_MOFFS) 919 TYPE("VR256", TYPE_YMM) 920 TYPE("VR256X", TYPE_YMM) 921 TYPE("VR512", TYPE_ZMM) 922 TYPE("VK1", TYPE_VK) 923 TYPE("VK1WM", TYPE_VK) 924 TYPE("VK2", TYPE_VK) 925 TYPE("VK2WM", TYPE_VK) 926 TYPE("VK4", TYPE_VK) 927 TYPE("VK4WM", TYPE_VK) 928 TYPE("VK8", TYPE_VK) 929 TYPE("VK8WM", TYPE_VK) 930 TYPE("VK16", TYPE_VK) 931 TYPE("VK16WM", TYPE_VK) 932 TYPE("VK32", TYPE_VK) 933 TYPE("VK32WM", TYPE_VK) 934 TYPE("VK64", TYPE_VK) 935 TYPE("VK64WM", TYPE_VK) 936 TYPE("VK1Pair", TYPE_VK_PAIR) 937 TYPE("VK2Pair", TYPE_VK_PAIR) 938 TYPE("VK4Pair", TYPE_VK_PAIR) 939 TYPE("VK8Pair", TYPE_VK_PAIR) 940 TYPE("VK16Pair", TYPE_VK_PAIR) 941 TYPE("vx64mem", TYPE_MVSIBX) 942 TYPE("vx128mem", TYPE_MVSIBX) 943 TYPE("vx256mem", TYPE_MVSIBX) 944 TYPE("vy128mem", TYPE_MVSIBY) 945 TYPE("vy256mem", TYPE_MVSIBY) 946 TYPE("vx64xmem", TYPE_MVSIBX) 947 TYPE("vx128xmem", TYPE_MVSIBX) 948 TYPE("vx256xmem", TYPE_MVSIBX) 949 TYPE("vy128xmem", TYPE_MVSIBY) 950 TYPE("vy256xmem", TYPE_MVSIBY) 951 TYPE("vy512xmem", TYPE_MVSIBY) 952 TYPE("vz256mem", TYPE_MVSIBZ) 953 TYPE("vz512mem", TYPE_MVSIBZ) 954 TYPE("BNDR", TYPE_BNDR) 955 errs() << "Unhandled type string " << s << "\n"; 956 llvm_unreachable("Unhandled type string"); 957 } 958 #undef TYPE 959 960 #define ENCODING(str, encoding) if (s == str) return encoding; 961 OperandEncoding 962 RecognizableInstr::immediateEncodingFromString(const std::string &s, 963 uint8_t OpSize) { 964 if(OpSize != X86Local::OpSize16) { 965 // For instructions without an OpSize prefix, a declared 16-bit register or 966 // immediate encoding is special. 967 ENCODING("i16imm", ENCODING_IW) 968 } 969 ENCODING("i32i8imm", ENCODING_IB) 970 ENCODING("AVX512RC", ENCODING_IRC) 971 ENCODING("i16imm", ENCODING_Iv) 972 ENCODING("i16i8imm", ENCODING_IB) 973 ENCODING("i32imm", ENCODING_Iv) 974 ENCODING("i64i32imm", ENCODING_ID) 975 ENCODING("i64i8imm", ENCODING_IB) 976 ENCODING("i8imm", ENCODING_IB) 977 ENCODING("u4imm", ENCODING_IB) 978 ENCODING("u8imm", ENCODING_IB) 979 ENCODING("i16u8imm", ENCODING_IB) 980 ENCODING("i32u8imm", ENCODING_IB) 981 ENCODING("i64u8imm", ENCODING_IB) 982 // This is not a typo. Instructions like BLENDVPD put 983 // register IDs in 8-bit immediates nowadays. 984 ENCODING("FR32", ENCODING_IB) 985 ENCODING("FR64", ENCODING_IB) 986 ENCODING("FR128", ENCODING_IB) 987 ENCODING("VR128", ENCODING_IB) 988 ENCODING("VR256", ENCODING_IB) 989 ENCODING("FR32X", ENCODING_IB) 990 ENCODING("FR64X", ENCODING_IB) 991 ENCODING("VR128X", ENCODING_IB) 992 ENCODING("VR256X", ENCODING_IB) 993 ENCODING("VR512", ENCODING_IB) 994 errs() << "Unhandled immediate encoding " << s << "\n"; 995 llvm_unreachable("Unhandled immediate encoding"); 996 } 997 998 OperandEncoding 999 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1000 uint8_t OpSize) { 1001 ENCODING("RST", ENCODING_FP) 1002 ENCODING("RSTi", ENCODING_FP) 1003 ENCODING("GR16", ENCODING_RM) 1004 ENCODING("GR32", ENCODING_RM) 1005 ENCODING("GR32orGR64", ENCODING_RM) 1006 ENCODING("GR64", ENCODING_RM) 1007 ENCODING("GR8", ENCODING_RM) 1008 ENCODING("VR128", ENCODING_RM) 1009 ENCODING("VR128X", ENCODING_RM) 1010 ENCODING("FR128", ENCODING_RM) 1011 ENCODING("FR64", ENCODING_RM) 1012 ENCODING("FR32", ENCODING_RM) 1013 ENCODING("FR64X", ENCODING_RM) 1014 ENCODING("FR32X", ENCODING_RM) 1015 ENCODING("VR64", ENCODING_RM) 1016 ENCODING("VR256", ENCODING_RM) 1017 ENCODING("VR256X", ENCODING_RM) 1018 ENCODING("VR512", ENCODING_RM) 1019 ENCODING("VK1", ENCODING_RM) 1020 ENCODING("VK2", ENCODING_RM) 1021 ENCODING("VK4", ENCODING_RM) 1022 ENCODING("VK8", ENCODING_RM) 1023 ENCODING("VK16", ENCODING_RM) 1024 ENCODING("VK32", ENCODING_RM) 1025 ENCODING("VK64", ENCODING_RM) 1026 ENCODING("VK1PAIR", ENCODING_RM) 1027 ENCODING("VK2PAIR", ENCODING_RM) 1028 ENCODING("VK4PAIR", ENCODING_RM) 1029 ENCODING("VK8PAIR", ENCODING_RM) 1030 ENCODING("VK16PAIR", ENCODING_RM) 1031 ENCODING("BNDR", ENCODING_RM) 1032 errs() << "Unhandled R/M register encoding " << s << "\n"; 1033 llvm_unreachable("Unhandled R/M register encoding"); 1034 } 1035 1036 OperandEncoding 1037 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1038 uint8_t OpSize) { 1039 ENCODING("GR16", ENCODING_REG) 1040 ENCODING("GR32", ENCODING_REG) 1041 ENCODING("GR32orGR64", ENCODING_REG) 1042 ENCODING("GR64", ENCODING_REG) 1043 ENCODING("GR8", ENCODING_REG) 1044 ENCODING("VR128", ENCODING_REG) 1045 ENCODING("FR128", ENCODING_REG) 1046 ENCODING("FR64", ENCODING_REG) 1047 ENCODING("FR32", ENCODING_REG) 1048 ENCODING("VR64", ENCODING_REG) 1049 ENCODING("SEGMENT_REG", ENCODING_REG) 1050 ENCODING("DEBUG_REG", ENCODING_REG) 1051 ENCODING("CONTROL_REG", ENCODING_REG) 1052 ENCODING("VR256", ENCODING_REG) 1053 ENCODING("VR256X", ENCODING_REG) 1054 ENCODING("VR128X", ENCODING_REG) 1055 ENCODING("FR64X", ENCODING_REG) 1056 ENCODING("FR32X", ENCODING_REG) 1057 ENCODING("VR512", ENCODING_REG) 1058 ENCODING("VK1", ENCODING_REG) 1059 ENCODING("VK2", ENCODING_REG) 1060 ENCODING("VK4", ENCODING_REG) 1061 ENCODING("VK8", ENCODING_REG) 1062 ENCODING("VK16", ENCODING_REG) 1063 ENCODING("VK32", ENCODING_REG) 1064 ENCODING("VK64", ENCODING_REG) 1065 ENCODING("VK1Pair", ENCODING_REG) 1066 ENCODING("VK2Pair", ENCODING_REG) 1067 ENCODING("VK4Pair", ENCODING_REG) 1068 ENCODING("VK8Pair", ENCODING_REG) 1069 ENCODING("VK16Pair", ENCODING_REG) 1070 ENCODING("VK1WM", ENCODING_REG) 1071 ENCODING("VK2WM", ENCODING_REG) 1072 ENCODING("VK4WM", ENCODING_REG) 1073 ENCODING("VK8WM", ENCODING_REG) 1074 ENCODING("VK16WM", ENCODING_REG) 1075 ENCODING("VK32WM", ENCODING_REG) 1076 ENCODING("VK64WM", ENCODING_REG) 1077 ENCODING("BNDR", ENCODING_REG) 1078 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1079 llvm_unreachable("Unhandled reg/opcode register encoding"); 1080 } 1081 1082 OperandEncoding 1083 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1084 uint8_t OpSize) { 1085 ENCODING("GR32", ENCODING_VVVV) 1086 ENCODING("GR64", ENCODING_VVVV) 1087 ENCODING("FR32", ENCODING_VVVV) 1088 ENCODING("FR128", ENCODING_VVVV) 1089 ENCODING("FR64", ENCODING_VVVV) 1090 ENCODING("VR128", ENCODING_VVVV) 1091 ENCODING("VR256", ENCODING_VVVV) 1092 ENCODING("FR32X", ENCODING_VVVV) 1093 ENCODING("FR64X", ENCODING_VVVV) 1094 ENCODING("VR128X", ENCODING_VVVV) 1095 ENCODING("VR256X", ENCODING_VVVV) 1096 ENCODING("VR512", ENCODING_VVVV) 1097 ENCODING("VK1", ENCODING_VVVV) 1098 ENCODING("VK2", ENCODING_VVVV) 1099 ENCODING("VK4", ENCODING_VVVV) 1100 ENCODING("VK8", ENCODING_VVVV) 1101 ENCODING("VK16", ENCODING_VVVV) 1102 ENCODING("VK32", ENCODING_VVVV) 1103 ENCODING("VK64", ENCODING_VVVV) 1104 ENCODING("VK1PAIR", ENCODING_VVVV) 1105 ENCODING("VK2PAIR", ENCODING_VVVV) 1106 ENCODING("VK4PAIR", ENCODING_VVVV) 1107 ENCODING("VK8PAIR", ENCODING_VVVV) 1108 ENCODING("VK16PAIR", ENCODING_VVVV) 1109 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1110 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1111 } 1112 1113 OperandEncoding 1114 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1115 uint8_t OpSize) { 1116 ENCODING("VK1WM", ENCODING_WRITEMASK) 1117 ENCODING("VK2WM", ENCODING_WRITEMASK) 1118 ENCODING("VK4WM", ENCODING_WRITEMASK) 1119 ENCODING("VK8WM", ENCODING_WRITEMASK) 1120 ENCODING("VK16WM", ENCODING_WRITEMASK) 1121 ENCODING("VK32WM", ENCODING_WRITEMASK) 1122 ENCODING("VK64WM", ENCODING_WRITEMASK) 1123 errs() << "Unhandled mask register encoding " << s << "\n"; 1124 llvm_unreachable("Unhandled mask register encoding"); 1125 } 1126 1127 OperandEncoding 1128 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1129 uint8_t OpSize) { 1130 ENCODING("i16mem", ENCODING_RM) 1131 ENCODING("i32mem", ENCODING_RM) 1132 ENCODING("i64mem", ENCODING_RM) 1133 ENCODING("i8mem", ENCODING_RM) 1134 ENCODING("ssmem", ENCODING_RM) 1135 ENCODING("sdmem", ENCODING_RM) 1136 ENCODING("f128mem", ENCODING_RM) 1137 ENCODING("f256mem", ENCODING_RM) 1138 ENCODING("f512mem", ENCODING_RM) 1139 ENCODING("f64mem", ENCODING_RM) 1140 ENCODING("f32mem", ENCODING_RM) 1141 ENCODING("i128mem", ENCODING_RM) 1142 ENCODING("i256mem", ENCODING_RM) 1143 ENCODING("i512mem", ENCODING_RM) 1144 ENCODING("f80mem", ENCODING_RM) 1145 ENCODING("lea64_32mem", ENCODING_RM) 1146 ENCODING("lea64mem", ENCODING_RM) 1147 ENCODING("anymem", ENCODING_RM) 1148 ENCODING("opaquemem", ENCODING_RM) 1149 ENCODING("vx64mem", ENCODING_VSIB) 1150 ENCODING("vx128mem", ENCODING_VSIB) 1151 ENCODING("vx256mem", ENCODING_VSIB) 1152 ENCODING("vy128mem", ENCODING_VSIB) 1153 ENCODING("vy256mem", ENCODING_VSIB) 1154 ENCODING("vx64xmem", ENCODING_VSIB) 1155 ENCODING("vx128xmem", ENCODING_VSIB) 1156 ENCODING("vx256xmem", ENCODING_VSIB) 1157 ENCODING("vy128xmem", ENCODING_VSIB) 1158 ENCODING("vy256xmem", ENCODING_VSIB) 1159 ENCODING("vy512xmem", ENCODING_VSIB) 1160 ENCODING("vz256mem", ENCODING_VSIB) 1161 ENCODING("vz512mem", ENCODING_VSIB) 1162 errs() << "Unhandled memory encoding " << s << "\n"; 1163 llvm_unreachable("Unhandled memory encoding"); 1164 } 1165 1166 OperandEncoding 1167 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1168 uint8_t OpSize) { 1169 if(OpSize != X86Local::OpSize16) { 1170 // For instructions without an OpSize prefix, a declared 16-bit register or 1171 // immediate encoding is special. 1172 ENCODING("i16imm", ENCODING_IW) 1173 } 1174 ENCODING("i16imm", ENCODING_Iv) 1175 ENCODING("i16i8imm", ENCODING_IB) 1176 ENCODING("i32imm", ENCODING_Iv) 1177 ENCODING("i32i8imm", ENCODING_IB) 1178 ENCODING("i64i32imm", ENCODING_ID) 1179 ENCODING("i64i8imm", ENCODING_IB) 1180 ENCODING("i8imm", ENCODING_IB) 1181 ENCODING("u8imm", ENCODING_IB) 1182 ENCODING("i16u8imm", ENCODING_IB) 1183 ENCODING("i32u8imm", ENCODING_IB) 1184 ENCODING("i64u8imm", ENCODING_IB) 1185 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1186 ENCODING("i16imm_brtarget", ENCODING_IW) 1187 ENCODING("i32imm_brtarget", ENCODING_ID) 1188 ENCODING("brtarget32", ENCODING_ID) 1189 ENCODING("brtarget16", ENCODING_IW) 1190 ENCODING("brtarget8", ENCODING_IB) 1191 ENCODING("i64imm", ENCODING_IO) 1192 ENCODING("offset16_8", ENCODING_Ia) 1193 ENCODING("offset16_16", ENCODING_Ia) 1194 ENCODING("offset16_32", ENCODING_Ia) 1195 ENCODING("offset32_8", ENCODING_Ia) 1196 ENCODING("offset32_16", ENCODING_Ia) 1197 ENCODING("offset32_32", ENCODING_Ia) 1198 ENCODING("offset32_64", ENCODING_Ia) 1199 ENCODING("offset64_8", ENCODING_Ia) 1200 ENCODING("offset64_16", ENCODING_Ia) 1201 ENCODING("offset64_32", ENCODING_Ia) 1202 ENCODING("offset64_64", ENCODING_Ia) 1203 ENCODING("srcidx8", ENCODING_SI) 1204 ENCODING("srcidx16", ENCODING_SI) 1205 ENCODING("srcidx32", ENCODING_SI) 1206 ENCODING("srcidx64", ENCODING_SI) 1207 ENCODING("dstidx8", ENCODING_DI) 1208 ENCODING("dstidx16", ENCODING_DI) 1209 ENCODING("dstidx32", ENCODING_DI) 1210 ENCODING("dstidx64", ENCODING_DI) 1211 errs() << "Unhandled relocation encoding " << s << "\n"; 1212 llvm_unreachable("Unhandled relocation encoding"); 1213 } 1214 1215 OperandEncoding 1216 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1217 uint8_t OpSize) { 1218 ENCODING("GR32", ENCODING_Rv) 1219 ENCODING("GR64", ENCODING_RO) 1220 ENCODING("GR16", ENCODING_Rv) 1221 ENCODING("GR8", ENCODING_RB) 1222 ENCODING("ccode", ENCODING_CC) 1223 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1224 llvm_unreachable("Unhandled opcode modifier encoding"); 1225 } 1226 #undef ENCODING 1227