1 /* 2 * \file trc_cmp_cfg_etmv3.h 3 * \brief OpenCSD : 4 * 5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved. 6 */ 7 8 9 /* 10 * Redistribution and use in source and binary forms, with or without modification, 11 * are permitted provided that the following conditions are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 20 * 3. Neither the name of the copyright holder nor the names of its contributors 21 * may be used to endorse or promote products derived from this software without 22 * specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #ifndef ARM_TRC_CMP_CFG_ETMV3_H_INCLUDED 37 #define ARM_TRC_CMP_CFG_ETMV3_H_INCLUDED 38 39 #include "trc_pkt_types_etmv3.h" 40 #include "common/trc_cs_config.h" 41 42 43 /** @addtogroup ocsd_protocol_cfg 44 @{*/ 45 46 /** @name ETMV3 configuration 47 @{*/ 48 49 50 /*! 51 * @class EtmV3Config 52 * @brief Interpreter class for etm v3 config structure. 53 * 54 * Provides quick value interpretation methods for the ETMv3 config register values. 55 * Primarily inlined for efficient code. 56 * 57 */ 58 class EtmV3Config : public CSConfig 59 { 60 public: 61 EtmV3Config(); /**< Default constructor */ 62 EtmV3Config(const ocsd_etmv3_cfg *cfg_regs); 63 ~EtmV3Config() {}; /**< Default destructor */ 64 65 /* register bit constants. */ 66 static const uint32_t CTRL_DATAVAL = 0x4; 67 static const uint32_t CTRL_DATAADDR = 0x8; 68 static const uint32_t CTRL_CYCLEACC = 0x1000; 69 static const uint32_t CTRL_DATAONLY = 0x100000; 70 static const uint32_t CTRL_TS_ENA = (0x1 << 28); 71 static const uint32_t CTRL_VMID_ENA = (0x1 << 30); 72 73 static const uint32_t CCER_HAS_TS = (0x1 << 22); 74 static const uint32_t CCER_VIRTEXT = (0x1 << 26); 75 static const uint32_t CCER_TS64BIT = (0x1 << 29); 76 77 static const uint32_t IDR_ALTBRANCH = 0x100000; 78 79 // operations to convert to and from C-API structure 80 81 //! copy assignment operator for C-API base structure into class. 82 EtmV3Config & operator=(const ocsd_etmv3_cfg *p_cfg); 83 84 //! cast operator returning struct const reference 85 operator const ocsd_etmv3_cfg &() const { return m_cfg; }; 86 //! cast operator returning struct const pointer 87 operator const ocsd_etmv3_cfg *() const { return &m_cfg; }; 88 89 //! combination enum to describe trace mode. 90 enum EtmTraceMode { 91 TM_INSTR_ONLY, //!< instruction only trace 92 TM_I_DATA_VAL, //!< instruction + data value 93 TM_I_DATA_ADDR, //!< instruction + data address 94 TM_I_DATA_VAL_ADDR, //!< instr + data value + data address 95 TM_DATAONLY_VAL, //!< data value trace 96 TM_DATAONLY_ADDR, //!< data address trace 97 TM_DATAONLY_VAL_ADDR //!< data value + address trace 98 }; 99 100 EtmTraceMode const GetTraceMode() const; //!< return trace mode 101 102 const bool isInstrTrace() const; //!< instruction trace present. 103 const bool isDataValTrace() const; //!< data value trace present. 104 const bool isDataAddrTrace() const; //!< data address trace present. 105 const bool isDataTrace() const; //!< either or both data trace types present. 106 107 const bool isCycleAcc() const; //!< return true if cycle accurate tracing enabled. 108 109 const int MinorRev() const; //!< return X revision in 3.X 110 111 const bool isV7MArch() const; //!< source is V7M architecture 112 const bool isAltBranch() const; //!< Alternate branch packet encoding used. 113 114 const int CtxtIDBytes() const; //!< number of context ID bytes traced 1,2,4; 115 const bool hasVirtExt() const; //!< processor has virtualisation extensions. 116 const bool isVMIDTrace() const; //!< VMID tracing enabled. 117 118 const bool hasTS() const; //!< Timestamps implemented in trace. 119 const bool isTSEnabled() const; //!< Timestamp trace is enabled. 120 const bool TSPkt64() const; //!< timestamp packet is 64 bits in size. 121 122 virtual const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device. 123 124 const ocsd_arch_version_t getArchVersion() const; //!< architecture version 125 const ocsd_core_profile_t getCoreProfile() const; //!< core profile. 126 127 private: 128 ocsd_etmv3_cfg m_cfg; 129 130 }; 131 132 133 /* inlines for the bit interpretations */ 134 135 inline EtmV3Config & EtmV3Config::operator=(const ocsd_etmv3_cfg *p_cfg) 136 { 137 m_cfg = *p_cfg; 138 return *this; 139 } 140 141 inline const bool EtmV3Config::isCycleAcc() const 142 { 143 return (bool)((m_cfg.reg_ctrl & CTRL_CYCLEACC) != 0); 144 } 145 146 //! return X revision in 3.X 147 inline const int EtmV3Config::MinorRev() const 148 { 149 return ((int)m_cfg.reg_idr & 0xF0) >> 4; 150 } 151 152 inline const bool EtmV3Config::isInstrTrace() const 153 { 154 return (bool)((m_cfg.reg_ctrl & CTRL_DATAONLY) == 0); 155 } 156 157 inline const bool EtmV3Config::isDataValTrace() const 158 { 159 return (bool)((m_cfg.reg_ctrl & CTRL_DATAVAL) != 0); 160 } 161 162 inline const bool EtmV3Config::isDataAddrTrace() const 163 { 164 return (bool)((m_cfg.reg_ctrl & CTRL_DATAADDR) != 0); 165 } 166 167 //! either or both data trace present 168 inline const bool EtmV3Config::isDataTrace() const 169 { 170 return (bool)((m_cfg.reg_ctrl & (CTRL_DATAADDR | CTRL_DATAVAL)) != 0); 171 } 172 173 inline const bool EtmV3Config::isV7MArch() const 174 { 175 return (bool)((m_cfg.arch_ver == ARCH_V7) && (m_cfg.core_prof == profile_CortexM)); 176 } 177 178 //! has alternate branch encoding 179 inline const bool EtmV3Config::isAltBranch() const 180 { 181 return (bool)(((m_cfg.reg_idr & IDR_ALTBRANCH) != 0) && (MinorRev() >= 4)); 182 } 183 184 //! processor implements virtualisation extensions. 185 inline const bool EtmV3Config::hasVirtExt() const 186 { 187 return (bool)((m_cfg.reg_ccer & CCER_VIRTEXT) != 0); 188 } 189 190 //! TS packet is 64 bit. 191 inline const bool EtmV3Config::TSPkt64() const 192 { 193 return (bool)((m_cfg.reg_ccer & CCER_TS64BIT) != 0); 194 } 195 196 //! TS implemented. 197 inline const bool EtmV3Config::hasTS() const 198 { 199 return (bool)((m_cfg.reg_ccer & CCER_HAS_TS) != 0); 200 } 201 202 //! TS is enabled in the trace 203 inline const bool EtmV3Config::isTSEnabled() const 204 { 205 return (bool)((m_cfg.reg_ctrl & CTRL_TS_ENA) != 0); 206 } 207 208 //! tracing VMID 209 inline const bool EtmV3Config::isVMIDTrace() const 210 { 211 return (bool)((m_cfg.reg_ctrl & CTRL_VMID_ENA) != 0); 212 } 213 214 inline const uint8_t EtmV3Config::getTraceID() const 215 { 216 return (uint8_t)(m_cfg.reg_trc_id & 0x7F); 217 } 218 219 inline const ocsd_arch_version_t EtmV3Config::getArchVersion() const 220 { 221 return m_cfg.arch_ver; 222 } 223 224 inline const ocsd_core_profile_t EtmV3Config::getCoreProfile() const 225 { 226 return m_cfg.core_prof; 227 } 228 229 /** @}*/ 230 231 /** @}*/ 232 233 #endif // ARM_TRC_CMP_CFG_ETMV3_H_INCLUDED 234 235 /* End of File trc_cmp_cfg_etmv3.h */ 236