1 /*
2  * \file       trc_cmp_cfg_etmv4.h
3  * \brief      OpenCSD :
4  *
5  * \copyright  Copyright (c) 2015, ARM Limited. All Rights Reserved.
6  */
7 
8 
9 /*
10  * Redistribution and use in source and binary forms, with or without modification,
11  * are permitted provided that the following conditions are met:
12  *
13  * 1. Redistributions of source code must retain the above copyright notice,
14  * this list of conditions and the following disclaimer.
15  *
16  * 2. Redistributions in binary form must reproduce the above copyright notice,
17  * this list of conditions and the following disclaimer in the documentation
18  * and/or other materials provided with the distribution.
19  *
20  * 3. Neither the name of the copyright holder nor the names of its contributors
21  * may be used to endorse or promote products derived from this software without
22  * specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27  * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
37 #define ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
38 
39 #include "trc_pkt_types_etmv4.h"
40 #include "common/trc_cs_config.h"
41 
42 
43 /** @addtogroup ocsd_protocol_cfg
44 @{*/
45 
46 /** @name ETMv4 configuration
47 @{*/
48 
49 /*!
50  * @class EtmV4Config
51  * @brief Interpreter class for etm v4 config structure.
52  *
53  * Provides quick value interpretation methods for the ETMv4 config register values.
54  * Primarily inlined for efficient code.
55  */
56 class EtmV4Config : public CSConfig // public ocsd_etmv4_cfg
57 {
58 public:
59     EtmV4Config();  /**< Default constructor */
60     EtmV4Config(const ocsd_etmv4_cfg *cfg_regs);
61     ~EtmV4Config() {}; /**< Default destructor */
62 
63 // operations to convert to and from C-API structure
64 
65     //! copy assignment operator for base structure into class.
66     EtmV4Config & operator=(const ocsd_etmv4_cfg *p_cfg);
67 
68     //! cast operator returning struct const reference
69     operator const ocsd_etmv4_cfg &() const { return m_cfg; };
70     //! cast operator returning struct const pointer
71     operator const ocsd_etmv4_cfg *() const { return &m_cfg; };
72 
73     const ocsd_core_profile_t &coreProfile() const { return m_cfg.core_prof; };
74     const ocsd_arch_version_t &archVersion() const { return m_cfg.arch_ver; };
75 
76     /* idr 0 */
77     const bool LSasInstP0() const;
78     const bool hasDataTrace() const;
79     const bool hasBranchBroadcast() const;
80     const bool hasCondTrace() const;
81     const bool hasCycleCountI() const;
82     const bool hasRetStack() const;
83     const uint8_t numEvents() const;
84     const bool eteHasTSMarker() const;
85 
86     typedef enum _condType {
87         COND_PASS_FAIL,
88         COND_HAS_ASPR
89     } condType;
90 
91     const condType hasCondType() const;
92 
93     typedef enum _QSuppType {
94         Q_NONE,
95         Q_ICOUNT_ONLY,
96         Q_NO_ICOUNT_ONLY,
97         Q_FULL
98     } QSuppType;
99 
100     const QSuppType getQSuppType();
101     const bool hasQElem();
102     const bool hasQFilter();
103 
104     const bool hasTrcExcpData() const;
105     const uint32_t TimeStampSize() const;
106 
107     const bool commitOpt1() const;
108     const bool commTransP0() const;
109 
110     /* idr 1 */
111     const uint8_t MajVersion() const;
112     const uint8_t MinVersion() const;
113     const uint8_t FullVersion() const;
114 
115     /* idr 2 */
116     const uint32_t iaSizeMax() const;
117     const uint32_t cidSize() const;
118     const uint32_t vmidSize();
119     const uint32_t daSize() const;
120     const uint32_t dvSize() const;
121     const uint32_t ccSize() const;
122     const bool vmidOpt() const;
123     const bool wfiwfeBranch() const;
124 
125     /* id regs 8-13*/
126     const uint32_t MaxSpecDepth() const;
127     const uint32_t P0_Key_Max() const;
128     const uint32_t P1_Key_Max() const;
129     const uint32_t P1_Spcl_Key_Max() const;
130     const uint32_t CondKeyMax() const;
131     const uint32_t CondSpecKeyMax() const;
132     const uint32_t CondKeyMaxIncr() const;
133 
134     /* trace idr */
135     virtual const uint8_t getTraceID() const; //!< CoreSight Trace ID for this device.
136 
137     /* config R */
138     const bool enabledDVTrace() const;
139     const bool enabledDATrace() const;
140     const bool enabledDataTrace() const;
141 
142     typedef enum {
143         LSP0_NONE,
144         LSP0_L,
145         LSP0_S,
146         LSP0_LS
147     } LSP0_t;
148 
149     const bool enabledLSP0Trace() const;
150     const LSP0_t LSP0Type() const;
151 
152     const bool enabledBrBroad() const;
153     const bool enabledCCI() const;
154     const bool enabledCID() const;
155     const bool enabledVMID() const;
156     const bool enabledVMIDOpt() const;
157 
158     typedef enum {
159         COND_TR_DIS,
160         COND_TR_LD,
161         COND_TR_ST,
162         COND_TR_LDST,
163         COND_TR_ALL
164     } CondITrace_t;
165 
166     const CondITrace_t enabledCondITrace();
167 
168     const bool enabledTS() const;
169     const bool enabledRetStack() const;
170 
171     const bool enabledQE() const;
172 
173 private:
174     void PrivateInit();
175     void CalcQSupp();
176     void CalcVMIDSize();
177 
178     bool m_QSuppCalc;
179     bool m_QSuppFilter;
180     QSuppType m_QSuppType;
181 
182     bool m_VMIDSzCalc;
183     uint32_t m_VMIDSize;
184 
185     bool m_condTraceCalc;
186     CondITrace_t m_CondTrace;
187 
188 protected:
189     ocsd_etmv4_cfg m_cfg;
190     uint8_t m_MajVer;
191     uint8_t m_MinVer;
192 
193 };
194 
195 /* idr 0 */
196 inline const bool EtmV4Config::LSasInstP0() const
197 {
198     return (bool)((m_cfg.reg_idr0 & 0x6) == 0x6);
199 }
200 
201 inline const bool EtmV4Config::hasDataTrace() const
202 {
203     return (bool)((m_cfg.reg_idr0 & 0x18) == 0x18);
204 }
205 
206 inline const bool EtmV4Config::hasBranchBroadcast() const
207 {
208     return (bool)((m_cfg.reg_idr0 & 0x20) == 0x20);
209 }
210 
211 inline const bool EtmV4Config::hasCondTrace() const
212 {
213     return (bool)((m_cfg.reg_idr0 & 0x40) == 0x40);
214 }
215 
216 inline const bool EtmV4Config::hasCycleCountI() const
217 {
218     return (bool)((m_cfg.reg_idr0 & 0x80) == 0x80);
219 }
220 
221 inline const bool EtmV4Config::hasRetStack() const
222 {
223     return (bool)((m_cfg.reg_idr0 & 0x200) == 0x200);
224 }
225 
226 inline const uint8_t EtmV4Config::numEvents() const
227 {
228     return ((m_cfg.reg_idr0 >> 10) & 0x3) + 1;
229 }
230 
231 inline const EtmV4Config::condType EtmV4Config::hasCondType() const
232 {
233     return ((m_cfg.reg_idr0 & 0x3000) == 0x1000) ? EtmV4Config::COND_HAS_ASPR : EtmV4Config::COND_PASS_FAIL;
234 }
235 
236 inline const EtmV4Config::QSuppType EtmV4Config::getQSuppType()
237 {
238     if(!m_QSuppCalc) CalcQSupp();
239     return m_QSuppType;
240 }
241 
242 inline const bool EtmV4Config::hasQElem()
243 {
244     if(!m_QSuppCalc) CalcQSupp();
245     return (bool)(m_QSuppType != Q_NONE);
246 }
247 
248 inline const bool EtmV4Config::hasQFilter()
249 {
250     if(!m_QSuppCalc) CalcQSupp();
251     return m_QSuppFilter;
252 }
253 
254 inline const bool EtmV4Config::hasTrcExcpData() const
255 {
256     return (bool)((m_cfg.reg_idr0 & 0x20000) == 0x20000);
257 }
258 
259 inline const bool EtmV4Config::eteHasTSMarker() const
260 {
261     return (FullVersion() >= 0x51) && ((m_cfg.reg_idr0 & 0x800000) == 0x800000);
262 }
263 
264 inline const uint32_t EtmV4Config::TimeStampSize() const
265 {
266     uint32_t tsSizeF = (m_cfg.reg_idr0 >> 24) & 0x1F;
267     if(tsSizeF == 0x6)
268         return 48;
269     if(tsSizeF == 0x8)
270         return 64;
271     return 0;
272 }
273 
274 inline const bool EtmV4Config::commitOpt1() const
275 {
276     return (bool)((m_cfg.reg_idr0 & 0x20000000) == 0x20000000) && hasCycleCountI();
277 }
278 
279 inline const bool EtmV4Config::commTransP0() const
280 {
281     return (bool)((m_cfg.reg_idr0 & 0x40000000) == 0x0);
282 }
283 
284     /* idr 1 */
285 inline const uint8_t EtmV4Config::MajVersion() const
286 {
287     return m_MajVer;
288 }
289 
290 inline const uint8_t EtmV4Config::MinVersion() const
291 {
292     return m_MinVer;
293 }
294 
295 inline const uint8_t EtmV4Config::FullVersion() const
296 {
297     return (m_MajVer << 4) | m_MinVer;
298 }
299 
300 /* idr 2 */
301 inline const uint32_t EtmV4Config::iaSizeMax() const
302 {
303     return ((m_cfg.reg_idr2 & 0x1F) == 0x8) ? 64 : 32;
304 }
305 
306 inline const uint32_t EtmV4Config::cidSize() const
307 {
308     return (((m_cfg.reg_idr2 >> 5) & 0x1F) == 0x4) ? 32 : 0;
309 }
310 
311 inline const uint32_t EtmV4Config::vmidSize()
312 {
313     if(!m_VMIDSzCalc)
314     {
315         CalcVMIDSize();
316     }
317     return m_VMIDSize;
318 }
319 
320 inline const uint32_t EtmV4Config::daSize() const
321 {
322     uint32_t daSizeF = ((m_cfg.reg_idr2 >> 15) & 0x1F);
323     if(daSizeF)
324         return (((m_cfg.reg_idr2 >> 15) & 0x1F) == 0x8) ? 64 : 32;
325     return 0;
326 }
327 
328 inline const uint32_t EtmV4Config::dvSize() const
329 {
330     uint32_t dvSizeF = ((m_cfg.reg_idr2 >> 20) & 0x1F);
331     if(dvSizeF)
332         return (((m_cfg.reg_idr2 >> 20) & 0x1F) == 0x8) ? 64 : 32;
333     return 0;
334 }
335 
336 inline const uint32_t EtmV4Config::ccSize() const
337 {
338     return ((m_cfg.reg_idr2 >> 25) & 0xF) + 12;
339 }
340 
341 inline const bool EtmV4Config::vmidOpt() const
342 {
343     return (bool)((m_cfg.reg_idr2 & 0x20000000) == 0x20000000) && (MinVersion() > 0);
344 }
345 
346 inline const bool EtmV4Config::wfiwfeBranch() const
347 {
348     return (bool)((m_cfg.reg_idr2 & 0x80000000) && (FullVersion() >= 0x43));
349 }
350 
351 
352 /* id regs 8-13*/
353 
354 inline const uint32_t EtmV4Config::MaxSpecDepth() const
355 {
356     return m_cfg.reg_idr8;
357 }
358 
359 inline const uint32_t EtmV4Config::P0_Key_Max() const
360 {
361     return (m_cfg.reg_idr9 == 0) ? 1 : m_cfg.reg_idr9;
362 }
363 
364 inline const uint32_t EtmV4Config::P1_Key_Max() const
365 {
366     return m_cfg.reg_idr10;
367 }
368 
369 inline const uint32_t  EtmV4Config::P1_Spcl_Key_Max() const
370 {
371     return m_cfg.reg_idr11;
372 }
373 
374 inline const uint32_t EtmV4Config::CondKeyMax() const
375 {
376     return m_cfg.reg_idr12;
377 }
378 
379 inline const uint32_t EtmV4Config::CondSpecKeyMax() const
380 {
381     return m_cfg.reg_idr13;
382 }
383 
384 inline const uint32_t EtmV4Config::CondKeyMaxIncr() const
385 {
386     return m_cfg.reg_idr12 - m_cfg.reg_idr13;
387 }
388 
389 inline const uint8_t EtmV4Config::getTraceID() const
390 {
391     return (uint8_t)(m_cfg.reg_traceidr & 0x7F);
392 }
393 
394     /* config R */
395 inline const bool EtmV4Config::enabledDVTrace() const
396 {
397     return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 17)) != 0);
398 }
399 
400 inline const bool EtmV4Config::enabledDATrace() const
401 {
402     return hasDataTrace() && enabledLSP0Trace() && ((m_cfg.reg_configr & (0x1 << 16)) != 0);
403 }
404 
405 inline const bool EtmV4Config::enabledDataTrace() const
406 {
407     return enabledDATrace() || enabledDVTrace();
408 }
409 
410 inline const bool EtmV4Config::enabledLSP0Trace() const
411 {
412     return ((m_cfg.reg_configr & 0x6) != 0);
413 }
414 
415 inline const EtmV4Config::LSP0_t EtmV4Config::LSP0Type() const
416 {
417     return (LSP0_t)((m_cfg.reg_configr & 0x6) >> 1);
418 }
419 
420 inline const bool EtmV4Config::enabledBrBroad() const
421 {
422     return ((m_cfg.reg_configr & (0x1 << 3)) != 0);
423 }
424 
425 inline const bool EtmV4Config::enabledCCI() const
426 {
427     return ((m_cfg.reg_configr & (0x1 << 4)) != 0);
428 }
429 
430 inline const bool EtmV4Config::enabledCID() const
431 {
432     return ((m_cfg.reg_configr & (0x1 << 6)) != 0);
433 }
434 
435 inline const bool EtmV4Config::enabledVMID() const
436 {
437     return ((m_cfg.reg_configr & (0x1 << 7)) != 0);
438 }
439 
440 inline const bool EtmV4Config::enabledVMIDOpt() const
441 {
442     bool vmidOptVal = ((m_cfg.reg_configr & (0x1 << 15)) != 0);
443     /* TRIDR2.VMIDOPT[30:29] determine value used */
444     if (!vmidOpt()) { /* [29] = 1'b0 */
445         vmidOptVal = false; /* res0 */
446         if (FullVersion() >= 0x45) {
447             /* umless version > 4.5 in which case [30] determines res val */
448             vmidOptVal = ((m_cfg.reg_idr2 & (0x1 << 30)) != 0);
449         }
450     }
451     return vmidOptVal;
452 }
453 
454 inline const EtmV4Config::CondITrace_t EtmV4Config::enabledCondITrace()
455 {
456     if(!m_condTraceCalc)
457     {
458         switch((m_cfg.reg_configr >> 8) & 0x7)
459         {
460         default:
461         case 0: m_CondTrace = COND_TR_DIS; break;
462         case 1: m_CondTrace = COND_TR_LD; break;
463         case 2: m_CondTrace = COND_TR_ST; break;
464         case 3: m_CondTrace = COND_TR_LDST; break;
465         case 7: m_CondTrace = COND_TR_ALL; break;
466         }
467         m_condTraceCalc = true;
468     }
469     return m_CondTrace;
470 }
471 
472 inline const bool EtmV4Config::enabledTS() const
473 {
474     return ((m_cfg.reg_configr & (0x1 << 11)) != 0);
475 }
476 
477 inline const bool EtmV4Config::enabledRetStack() const
478 {
479     return ((m_cfg.reg_configr & (0x1 << 12)) != 0);
480 }
481 
482 inline const bool EtmV4Config::enabledQE() const
483 {
484        return ((m_cfg.reg_configr & (0x3 << 13)) != 0);
485 }
486 
487 /** @}*/
488 /** @}*/
489 
490 #endif // ARM_TRC_CMP_CFG_ETMV4_H_INCLUDED
491 
492 /* End of File trc_cmp_cfg_etmv4.h */
493