1 /* 2 * \file trc_pkt_decode_etmv4i.h 3 * \brief OpenCSD : ETMv4 instruction decoder 4 * 5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved. 6 */ 7 8 /* 9 * Redistribution and use in source and binary forms, with or without modification, 10 * are permitted provided that the following conditions are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3. Neither the name of the copyright holder nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef ARM_TRC_PKT_DECODE_ETMV4I_H_INCLUDED 36 #define ARM_TRC_PKT_DECODE_ETMV4I_H_INCLUDED 37 38 #include "common/trc_pkt_decode_base.h" 39 #include "opencsd/etmv4/trc_pkt_elem_etmv4i.h" 40 #include "opencsd/etmv4/trc_cmp_cfg_etmv4.h" 41 #include "common/trc_gen_elem.h" 42 #include "common/trc_ret_stack.h" 43 #include "opencsd/etmv4/trc_etmv4_stack_elem.h" 44 45 class TrcStackElem; 46 class TrcStackElemParam; 47 class TrcStackElemCtxt; 48 49 class TrcPktDecodeEtmV4I : public TrcPktDecodeBase<EtmV4ITrcPacket, EtmV4Config> 50 { 51 public: 52 TrcPktDecodeEtmV4I(); 53 TrcPktDecodeEtmV4I(int instIDNum); 54 virtual ~TrcPktDecodeEtmV4I(); 55 56 protected: 57 /* implementation packet decoding interface */ 58 virtual ocsd_datapath_resp_t processPacket(); 59 virtual ocsd_datapath_resp_t onEOT(); 60 virtual ocsd_datapath_resp_t onReset(); 61 virtual ocsd_datapath_resp_t onFlush(); 62 virtual ocsd_err_t onProtocolConfig(); 63 virtual const uint8_t getCoreSightTraceID() { return m_CSID; }; 64 65 /* local decode methods */ 66 void initDecoder(); // initial state on creation (zeros all config) 67 void resetDecoder(); // reset state to start of decode. (moves state, retains config) 68 69 ocsd_datapath_resp_t decodePacket(bool &Complete); // return true to indicate decode complete - can change FSM to commit state - return is false. 70 ocsd_datapath_resp_t commitElements(bool &Complete); // commit elements - may get wait response, or flag completion. 71 ocsd_datapath_resp_t flushEOT(); 72 73 void doTraceInfoPacket(); 74 void updateContext(TrcStackElemCtxt *pCtxtElem); 75 76 // process atom will output instruction trace, or no memory access trace elements. 77 ocsd_datapath_resp_t processAtom(const ocsd_atm_val, bool &bCont); 78 79 // process an exception element - output instruction trace + exception generic type. 80 ocsd_datapath_resp_t processException(); 81 82 // process a bad packet 83 ocsd_datapath_resp_t handleBadPacket(const char *reason); 84 85 ocsd_datapath_resp_t outputCC(TrcStackElemParam *pParamElem); 86 ocsd_datapath_resp_t outputTS(TrcStackElemParam *pParamElem, bool withCC); 87 ocsd_datapath_resp_t outputEvent(TrcStackElemParam *pParamElem); 88 89 private: 90 void SetInstrInfoInAddrISA(const ocsd_vaddr_t addr_val, const uint8_t isa); 91 92 ocsd_err_t traceInstrToWP(bool &bWPFound, const bool traceToAddrNext = false, const ocsd_vaddr_t nextAddrMatch = 0); //!< follow instructions from the current address to a WP. true if good, false if memory cannot be accessed. 93 94 ocsd_datapath_resp_t returnStackPop(); // pop return stack and update instruction address. 95 96 //** intra packet state (see ETMv4 spec 6.2.1); 97 98 // timestamping 99 uint64_t m_timestamp; // last broadcast global Timestamp. 100 101 // state and context 102 uint32_t m_context_id; // most recent context ID 103 uint32_t m_vmid_id; // most recent VMID 104 bool m_is_secure; // true if Secure 105 bool m_is_64bit; // true if 64 bit 106 107 // cycle counts 108 int m_cc_threshold; 109 110 // speculative trace (unsupported at present in the decoder). 111 int m_curr_spec_depth; 112 int m_max_spec_depth; 113 114 // data trace associative elements (unsupported at present in the decoder). 115 int m_p0_key; 116 int m_p0_key_max; 117 118 // conditional non-branch trace - when data trace active (unsupported at present in the decoder) 119 int m_cond_c_key; 120 int m_cond_r_key; 121 int m_cond_key_max_incr; 122 123 uint8_t m_CSID; //!< Coresight trace ID for this decoder. 124 125 bool m_IASize64; //!< True if 64 bit instruction addresses supported. 126 127 //** Other processor state; 128 129 // trace decode FSM 130 typedef enum { 131 NO_SYNC, //!< pre start trace - init state or after reset or overflow, loss of sync. 132 WAIT_SYNC, //!< waiting for sync packet. 133 WAIT_TINFO, //!< waiting for trace info packet. 134 DECODE_PKTS, //!< processing packets - creating decode elements on stack 135 COMMIT_ELEM, //!< commit elements for execution - create generic trace elements and pass on. 136 } processor_state_t; 137 138 processor_state_t m_curr_state; 139 140 //** P0 element stack 141 EtmV4P0Stack m_P0_stack; //!< P0 decode element stack 142 143 int m_P0_commit; //!< number of elements to commit 144 145 // packet decode state 146 bool m_need_ctxt; //!< need context to continue 147 bool m_need_addr; //!< need an address to continue 148 bool m_except_pending_addr; //!< next address packet is part of exception. 149 150 // exception packet processing state (may need excep elem only, range+excep, range+ 151 typedef enum { 152 EXCEP_POP, // start of processing read exception packets off the stack and analyze 153 EXCEP_RANGE, // output a range element 154 EXCEP_NACC, // output a nacc element 155 EXCEP_EXCEP, // output an ecxeption element. 156 } excep_proc_state_t; 157 158 excep_proc_state_t m_excep_proc; //!< state of exception processing 159 etmv4_addr_val_t m_excep_addr; //!< excepiton return address. 160 ocsd_trc_index_t m_excep_index; //!< trace index for exception element 161 162 ocsd_instr_info m_instr_info; //!< instruction info for code follower - in address is the next to be decoded. 163 164 bool m_mem_nacc_pending; //!< need to output a memory access failure packet 165 ocsd_vaddr_t m_nacc_addr; //!< record unaccessible address 166 167 ocsd_pe_context m_pe_context; //!< current context information 168 etmv4_trace_info_t m_trace_info; //!< trace info for this trace run. 169 170 bool m_prev_overflow; 171 172 bool m_flush_EOT; //!< true if doing an end of trace flush - cleans up lingering events / TS / CC 173 174 TrcAddrReturnStack m_return_stack; 175 176 //** output element 177 OcsdTraceElement m_output_elem; 178 179 }; 180 181 #endif // ARM_TRC_PKT_DECODE_ETMV4I_H_INCLUDED 182 183 /* End of File trc_pkt_decode_etmv4i.h */ 184