1 /* 2 * \file trc_cmp_cfg_stm.h 3 * \brief OpenCSD : STM compnent configuration. 4 * 5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved. 6 */ 7 8 /* 9 * Redistribution and use in source and binary forms, with or without modification, 10 * are permitted provided that the following conditions are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3. Neither the name of the copyright holder nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef ARM_TRC_CMP_CFG_STM_H_INCLUDED 36 #define ARM_TRC_CMP_CFG_STM_H_INCLUDED 37 38 #include "trc_pkt_types_stm.h" 39 #include "common/trc_cs_config.h" 40 41 /** @addtogroup ocsd_protocol_cfg 42 @{*/ 43 44 /** @name STM configuration 45 @{*/ 46 47 /*! 48 * @class STMConfig 49 * @brief STM hardware configuration data. 50 * 51 * Represents the programmed and hardware configured state of an STM device. 52 * Creates default values for most RO register values to effect a default STM 53 * with values of 256 masters, 65536 channels, HW event trace not present / disabled. 54 * 55 * If this default is sufficient a single call to setTraceID() will be all that is 56 * required to decode the STM protocol. 57 * 58 * Can also be initialised with a fully populated ocsd_stm_cfg structure. 59 */ 60 class STMConfig : public CSConfig // public ocsd_stm_cfg 61 { 62 public: 63 STMConfig(); //!< Constructor - creates a default configuration 64 STMConfig(const ocsd_stm_cfg *cfg_regs); 65 ~STMConfig() {}; 66 67 // operations to convert to and from C-API structure 68 69 STMConfig & operator=(const ocsd_stm_cfg *p_cfg); //!< set from full configuration structure. 70 //! cast operator returning struct const reference 71 operator const ocsd_stm_cfg &() const { return m_cfg; }; 72 //! cast operator returning struct const pointer 73 operator const ocsd_stm_cfg *() const { return &m_cfg; }; 74 75 // access functions 76 void setTraceID(const uint8_t traceID); //!< Set the CoreSight trace ID. 77 void setHWTraceFeat(const hw_event_feat_t hw_feat); //!< set usage of STM HW event trace. 78 79 virtual const uint8_t getTraceID() const; //!< Get the CoreSight trace ID. 80 const uint8_t getMaxMasterIdx() const; //!< Get the maximum master index 81 const uint16_t getMaxChannelIdx() const; //!< Get the maximum channel index. 82 const uint16_t getHWTraceMasterIdx() const; //!< Get the master used for HW event trace. 83 bool getHWTraceEn() const; //!< return true if HW trace is present and enabled. 84 85 private: 86 bool m_bHWTraceEn; 87 ocsd_stm_cfg m_cfg; 88 }; 89 90 inline STMConfig::STMConfig() 91 { 92 m_cfg.reg_tcsr = 0; 93 m_cfg.reg_devid = 0xFF; // default to 256 masters. 94 m_cfg.reg_feat3r = 0x10000; // default to 65536 channels. 95 m_cfg.reg_feat1r = 0x0; 96 m_cfg.reg_hwev_mast = 0; // default hwtrace master = 0; 97 m_cfg.hw_event = HwEvent_Unknown_Disabled; // default to not present / disabled. 98 m_bHWTraceEn = false; 99 } 100 101 inline STMConfig::STMConfig(const ocsd_stm_cfg *cfg_regs) 102 { 103 m_cfg = *cfg_regs; 104 setHWTraceFeat(m_cfg.hw_event); 105 } 106 107 inline STMConfig & STMConfig::operator=(const ocsd_stm_cfg *p_cfg) 108 { 109 m_cfg = *p_cfg; 110 setHWTraceFeat(p_cfg->hw_event); 111 return *this; 112 } 113 114 inline void STMConfig::setTraceID(const uint8_t traceID) 115 { 116 uint32_t IDmask = 0x007F0000; 117 m_cfg.reg_tcsr &= ~IDmask; 118 m_cfg.reg_tcsr |= (((uint32_t)traceID) << 16) & IDmask; 119 } 120 121 inline void STMConfig::setHWTraceFeat(const hw_event_feat_t hw_feat) 122 { 123 m_cfg.hw_event = hw_feat; 124 m_bHWTraceEn = (m_cfg.hw_event == HwEvent_Enabled); 125 if(m_cfg.hw_event == HwEvent_UseRegisters) 126 m_bHWTraceEn = (((m_cfg.reg_feat1r & 0xC0000) == 0x80000) && ((m_cfg.reg_tcsr & 0x8) == 0x8)); 127 } 128 129 inline const uint8_t STMConfig::getTraceID() const 130 { 131 return (uint8_t)((m_cfg.reg_tcsr >> 16) & 0x7F); 132 } 133 134 inline const uint8_t STMConfig::getMaxMasterIdx() const 135 { 136 return (uint8_t)(m_cfg.reg_devid & 0xFF); 137 } 138 139 inline const uint16_t STMConfig::getMaxChannelIdx() const 140 { 141 return (uint16_t)(m_cfg.reg_feat3r - 1); 142 } 143 144 inline const uint16_t STMConfig::getHWTraceMasterIdx() const 145 { 146 return (uint16_t)(m_cfg.reg_hwev_mast & 0xFFFF); 147 } 148 149 inline bool STMConfig::getHWTraceEn() const 150 { 151 return m_bHWTraceEn; 152 } 153 154 155 /** @}*/ 156 157 /** @}*/ 158 159 #endif // ARM_TRC_CMP_CFG_STM_H_INCLUDED 160 161 /* End of File trc_cmp_cfg_stm.h */ 162