1#! /usr/bin/env perl
2# Copyright 2010-2020 The OpenSSL Project Authors. All Rights Reserved.
3#
4# Licensed under the Apache License 2.0 (the "License").  You may not use
5# this file except in compliance with the License.  You can obtain a copy
6# in the file LICENSE in the source distribution or at
7# https://www.openssl.org/source/license.html
8
9
10# ====================================================================
11# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
12# project. The module is, however, dual licensed under OpenSSL and
13# CRYPTOGAMS licenses depending on where you obtain it. For further
14# details see http://www.openssl.org/~appro/cryptogams/.
15# ====================================================================
16
17# SHA2 block procedures for MIPS.
18
19# October 2010.
20#
21# SHA256 performance improvement on MIPS R5000 CPU is ~27% over gcc-
22# generated code in o32 build and ~55% in n32/64 build. SHA512 [which
23# for now can only be compiled for MIPS64 ISA] improvement is modest
24# ~17%, but it comes for free, because it's same instruction sequence.
25# Improvement coefficients are for aligned input.
26
27# September 2012.
28#
29# Add MIPS[32|64]R2 code (>25% less instructions).
30
31######################################################################
32# There is a number of MIPS ABI in use, O32 and N32/64 are most
33# widely used. Then there is a new contender: NUBI. It appears that if
34# one picks the latter, it's possible to arrange code in ABI neutral
35# manner. Therefore let's stick to NUBI register layout:
36#
37($zero,$at,$t0,$t1,$t2)=map("\$$_",(0..2,24,25));
38($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
39($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7,$s8,$s9,$s10,$s11)=map("\$$_",(12..23));
40($gp,$tp,$sp,$fp,$ra)=map("\$$_",(3,28..31));
41#
42# The return value is placed in $a0. Following coding rules facilitate
43# interoperability:
44#
45# - never ever touch $tp, "thread pointer", former $gp [o32 can be
46#   excluded from the rule, because it's specified volatile];
47# - copy return value to $t0, former $v0 [or to $a0 if you're adapting
48#   old code];
49# - on O32 populate $a4-$a7 with 'lw $aN,4*N($sp)' if necessary;
50#
51# For reference here is register layout for N32/64 MIPS ABIs:
52#
53# ($zero,$at,$v0,$v1)=map("\$$_",(0..3));
54# ($a0,$a1,$a2,$a3,$a4,$a5,$a6,$a7)=map("\$$_",(4..11));
55# ($t0,$t1,$t2,$t3,$t8,$t9)=map("\$$_",(12..15,24,25));
56# ($s0,$s1,$s2,$s3,$s4,$s5,$s6,$s7)=map("\$$_",(16..23));
57# ($gp,$sp,$fp,$ra)=map("\$$_",(28..31));
58#
59# if $output doesn't have an extension, it's not an output file
60# so use it for $flavour.
61
62# $output is the last argument if it looks like a file (it has an extension)
63# $flavour is the first argument if it doesn't look like a file
64$output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
65# supported flavours are o32,n32,64,nubi32,nubi64, default is o32
66$flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : "o32";
67
68if ($flavour =~ /64|n32/i) {
69	$PTR_LA="dla";
70	$PTR_ADD="daddu";	# incidentally works even on n32
71	$PTR_SUB="dsubu";	# incidentally works even on n32
72	$REG_S="sd";
73	$REG_L="ld";
74	$PTR_SLL="dsll";	# incidentally works even on n32
75	$SZREG=8;
76} else {
77	$PTR_LA="la";
78	$PTR_ADD="addu";
79	$PTR_SUB="subu";
80	$REG_S="sw";
81	$REG_L="lw";
82	$PTR_SLL="sll";
83	$SZREG=4;
84}
85$pf = ($flavour =~ /nubi/i) ? $t0 : $t2;
86#
87# <appro@openssl.org>
88#
89######################################################################
90
91$big_endian=(`echo MIPSEB | $ENV{CC} -E -`=~/MIPSEB/)?0:1 if ($ENV{CC});
92
93open STDOUT,">$output";
94
95if (!defined($big_endian)) { $big_endian=(unpack('L',pack('N',1))==1); }
96
97if ($output =~ /512/) {
98	$label="512";
99	$SZ=8;
100	$LD="ld";		# load from memory
101	$ST="sd";		# store to memory
102	$SLL="dsll";		# shift left logical
103	$SRL="dsrl";		# shift right logical
104	$ADDU="daddu";
105	$ROTR="drotr";
106	@Sigma0=(28,34,39);
107	@Sigma1=(14,18,41);
108	@sigma0=( 7, 1, 8);	# right shift first
109	@sigma1=( 6,19,61);	# right shift first
110	$lastK=0x817;
111	$rounds=80;
112} else {
113	$label="256";
114	$SZ=4;
115	$LD="lw";		# load from memory
116	$ST="sw";		# store to memory
117	$SLL="sll";		# shift left logical
118	$SRL="srl";		# shift right logical
119	$ADDU="addu";
120	$ROTR="rotr";
121	@Sigma0=( 2,13,22);
122	@Sigma1=( 6,11,25);
123	@sigma0=( 3, 7,18);	# right shift first
124	@sigma1=(10,17,19);	# right shift first
125	$lastK=0x8f2;
126	$rounds=64;
127}
128
129$MSB = $big_endian ? 0 : ($SZ-1);
130$LSB = ($SZ-1)&~$MSB;
131
132@V=($A,$B,$C,$D,$E,$F,$G,$H)=map("\$$_",(1,2,3,7,24,25,30,31));
133@X=map("\$$_",(8..23));
134
135$ctx=$a0;
136$inp=$a1;
137$len=$a2;	$Ktbl=$len;
138
139sub BODY_00_15 {
140my ($i,$a,$b,$c,$d,$e,$f,$g,$h)=@_;
141my ($T1,$tmp0,$tmp1,$tmp2)=(@X[4],@X[5],@X[6],@X[7]);
142
143$code.=<<___ if ($i<15);
144#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
145	${LD}	@X[1],`($i+1)*$SZ`($inp)
146#else
147	${LD}l	@X[1],`($i+1)*$SZ+$MSB`($inp)
148	${LD}r	@X[1],`($i+1)*$SZ+$LSB`($inp)
149#endif
150___
151$code.=<<___	if (!$big_endian && $i<16 && $SZ==4);
152#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
153	wsbh	@X[0],@X[0]		# byte swap($i)
154	rotr	@X[0],@X[0],16
155#else
156	srl	$tmp0,@X[0],24		# byte swap($i)
157	srl	$tmp1,@X[0],8
158	andi	$tmp2,@X[0],0xFF00
159	sll	@X[0],@X[0],24
160	andi	$tmp1,0xFF00
161	sll	$tmp2,$tmp2,8
162	or	@X[0],$tmp0
163	or	$tmp1,$tmp2
164	or	@X[0],$tmp1
165#endif
166___
167$code.=<<___	if (!$big_endian && $i<16 && $SZ==8);
168#if defined(_MIPS_ARCH_MIPS64R2)
169	dsbh	@X[0],@X[0]		# byte swap($i)
170	dshd	@X[0],@X[0]
171#else
172	ori	$tmp0,$zero,0xFF
173	dsll	$tmp2,$tmp0,32
174	or	$tmp0,$tmp2		# 0x000000FF000000FF
175	and	$tmp1,@X[0],$tmp0	# byte swap($i)
176	dsrl	$tmp2,@X[0],24
177	dsll	$tmp1,24
178	and	$tmp2,$tmp0
179	dsll	$tmp0,8			# 0x0000FF000000FF00
180	or	$tmp1,$tmp2
181	and	$tmp2,@X[0],$tmp0
182	dsrl	@X[0],8
183	dsll	$tmp2,8
184	and	@X[0],$tmp0
185	or	$tmp1,$tmp2
186	or	@X[0],$tmp1
187	dsrl	$tmp1,@X[0],32
188	dsll	@X[0],32
189	or	@X[0],$tmp1
190#endif
191___
192$code.=<<___;
193#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
194	xor	$tmp2,$f,$g			# $i
195	$ROTR	$tmp0,$e,@Sigma1[0]
196	$ADDU	$T1,$X[0],$h
197	$ROTR	$tmp1,$e,@Sigma1[1]
198	and	$tmp2,$e
199	$ROTR	$h,$e,@Sigma1[2]
200	xor	$tmp0,$tmp1
201	$ROTR	$tmp1,$a,@Sigma0[0]
202	xor	$tmp2,$g			# Ch(e,f,g)
203	xor	$tmp0,$h			# Sigma1(e)
204
205	$ROTR	$h,$a,@Sigma0[1]
206	$ADDU	$T1,$tmp2
207	$LD	$tmp2,`$i*$SZ`($Ktbl)		# K[$i]
208	xor	$h,$tmp1
209	$ROTR	$tmp1,$a,@Sigma0[2]
210	$ADDU	$T1,$tmp0
211	and	$tmp0,$b,$c
212	xor	$h,$tmp1			# Sigma0(a)
213	xor	$tmp1,$b,$c
214#else
215	$ADDU	$T1,$X[0],$h			# $i
216	$SRL	$h,$e,@Sigma1[0]
217	xor	$tmp2,$f,$g
218	$SLL	$tmp1,$e,`$SZ*8-@Sigma1[2]`
219	and	$tmp2,$e
220	$SRL	$tmp0,$e,@Sigma1[1]
221	xor	$h,$tmp1
222	$SLL	$tmp1,$e,`$SZ*8-@Sigma1[1]`
223	xor	$h,$tmp0
224	$SRL	$tmp0,$e,@Sigma1[2]
225	xor	$h,$tmp1
226	$SLL	$tmp1,$e,`$SZ*8-@Sigma1[0]`
227	xor	$h,$tmp0
228	xor	$tmp2,$g			# Ch(e,f,g)
229	xor	$tmp0,$tmp1,$h			# Sigma1(e)
230
231	$SRL	$h,$a,@Sigma0[0]
232	$ADDU	$T1,$tmp2
233	$LD	$tmp2,`$i*$SZ`($Ktbl)		# K[$i]
234	$SLL	$tmp1,$a,`$SZ*8-@Sigma0[2]`
235	$ADDU	$T1,$tmp0
236	$SRL	$tmp0,$a,@Sigma0[1]
237	xor	$h,$tmp1
238	$SLL	$tmp1,$a,`$SZ*8-@Sigma0[1]`
239	xor	$h,$tmp0
240	$SRL	$tmp0,$a,@Sigma0[2]
241	xor	$h,$tmp1
242	$SLL	$tmp1,$a,`$SZ*8-@Sigma0[0]`
243	xor	$h,$tmp0
244	and	$tmp0,$b,$c
245	xor	$h,$tmp1			# Sigma0(a)
246	xor	$tmp1,$b,$c
247#endif
248	$ST	@X[0],`($i%16)*$SZ`($sp)	# offload to ring buffer
249	$ADDU	$h,$tmp0
250	and	$tmp1,$a
251	$ADDU	$T1,$tmp2			# +=K[$i]
252	$ADDU	$h,$tmp1			# +=Maj(a,b,c)
253	$ADDU	$d,$T1
254	$ADDU	$h,$T1
255___
256$code.=<<___ if ($i>=13);
257	$LD	@X[3],`(($i+3)%16)*$SZ`($sp)	# prefetch from ring buffer
258___
259}
260
261sub BODY_16_XX {
262my $i=@_[0];
263my ($tmp0,$tmp1,$tmp2,$tmp3)=(@X[4],@X[5],@X[6],@X[7]);
264
265$code.=<<___;
266#if defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_MIPS64R2)
267	$SRL	$tmp2,@X[1],@sigma0[0]		# Xupdate($i)
268	$ROTR	$tmp0,@X[1],@sigma0[1]
269	$ADDU	@X[0],@X[9]			# +=X[i+9]
270	xor	$tmp2,$tmp0
271	$ROTR	$tmp0,@X[1],@sigma0[2]
272
273	$SRL	$tmp3,@X[14],@sigma1[0]
274	$ROTR	$tmp1,@X[14],@sigma1[1]
275	xor	$tmp2,$tmp0			# sigma0(X[i+1])
276	$ROTR	$tmp0,@X[14],@sigma1[2]
277	xor	$tmp3,$tmp1
278	$ADDU	@X[0],$tmp2
279#else
280	$SRL	$tmp2,@X[1],@sigma0[0]		# Xupdate($i)
281	$ADDU	@X[0],@X[9]			# +=X[i+9]
282	$SLL	$tmp1,@X[1],`$SZ*8-@sigma0[2]`
283	$SRL	$tmp0,@X[1],@sigma0[1]
284	xor	$tmp2,$tmp1
285	$SLL	$tmp1,`@sigma0[2]-@sigma0[1]`
286	xor	$tmp2,$tmp0
287	$SRL	$tmp0,@X[1],@sigma0[2]
288	xor	$tmp2,$tmp1
289
290	$SRL	$tmp3,@X[14],@sigma1[0]
291	xor	$tmp2,$tmp0			# sigma0(X[i+1])
292	$SLL	$tmp1,@X[14],`$SZ*8-@sigma1[2]`
293	$ADDU	@X[0],$tmp2
294	$SRL	$tmp0,@X[14],@sigma1[1]
295	xor	$tmp3,$tmp1
296	$SLL	$tmp1,`@sigma1[2]-@sigma1[1]`
297	xor	$tmp3,$tmp0
298	$SRL	$tmp0,@X[14],@sigma1[2]
299	xor	$tmp3,$tmp1
300#endif
301	xor	$tmp3,$tmp0			# sigma1(X[i+14])
302	$ADDU	@X[0],$tmp3
303___
304	&BODY_00_15(@_);
305}
306
307$FRAMESIZE=16*$SZ+16*$SZREG;
308$SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? "0xc0fff008" : "0xc0ff0000";
309
310$code.=<<___;
311#include "mips_arch.h"
312
313.text
314.set	noat
315#if !defined(__mips_eabi) && (!defined(__vxworks) || defined(__pic__))
316.option	pic2
317#endif
318
319.align	5
320.globl	sha${label}_block_data_order
321.ent	sha${label}_block_data_order
322sha${label}_block_data_order:
323	.frame	$sp,$FRAMESIZE,$ra
324	.mask	$SAVED_REGS_MASK,-$SZREG
325	.set	noreorder
326___
327$code.=<<___ if ($flavour =~ /o32/i);	# o32 PIC-ification
328	.cpload	$pf
329___
330$code.=<<___;
331	$PTR_SUB $sp,$FRAMESIZE
332	$REG_S	$ra,$FRAMESIZE-1*$SZREG($sp)
333	$REG_S	$fp,$FRAMESIZE-2*$SZREG($sp)
334	$REG_S	$s11,$FRAMESIZE-3*$SZREG($sp)
335	$REG_S	$s10,$FRAMESIZE-4*$SZREG($sp)
336	$REG_S	$s9,$FRAMESIZE-5*$SZREG($sp)
337	$REG_S	$s8,$FRAMESIZE-6*$SZREG($sp)
338	$REG_S	$s7,$FRAMESIZE-7*$SZREG($sp)
339	$REG_S	$s6,$FRAMESIZE-8*$SZREG($sp)
340	$REG_S	$s5,$FRAMESIZE-9*$SZREG($sp)
341	$REG_S	$s4,$FRAMESIZE-10*$SZREG($sp)
342___
343$code.=<<___ if ($flavour =~ /nubi/i);	# optimize non-nubi prologue
344	$REG_S	$s3,$FRAMESIZE-11*$SZREG($sp)
345	$REG_S	$s2,$FRAMESIZE-12*$SZREG($sp)
346	$REG_S	$s1,$FRAMESIZE-13*$SZREG($sp)
347	$REG_S	$s0,$FRAMESIZE-14*$SZREG($sp)
348	$REG_S	$gp,$FRAMESIZE-15*$SZREG($sp)
349___
350$code.=<<___;
351	$PTR_SLL @X[15],$len,`log(16*$SZ)/log(2)`
352___
353$code.=<<___ if ($flavour !~ /o32/i);	# non-o32 PIC-ification
354	.cplocal	$Ktbl
355	.cpsetup	$pf,$zero,sha${label}_block_data_order
356___
357$code.=<<___;
358	.set	reorder
359	$PTR_LA	$Ktbl,K${label}		# PIC-ified 'load address'
360
361	$LD	$A,0*$SZ($ctx)		# load context
362	$LD	$B,1*$SZ($ctx)
363	$LD	$C,2*$SZ($ctx)
364	$LD	$D,3*$SZ($ctx)
365	$LD	$E,4*$SZ($ctx)
366	$LD	$F,5*$SZ($ctx)
367	$LD	$G,6*$SZ($ctx)
368	$LD	$H,7*$SZ($ctx)
369
370	$PTR_ADD @X[15],$inp		# pointer to the end of input
371	$REG_S	@X[15],16*$SZ($sp)
372	b	.Loop
373
374.align	5
375.Loop:
376#if defined(_MIPS_ARCH_MIPS32R6) || defined(_MIPS_ARCH_MIPS64R6)
377	${LD}	@X[0],($inp)
378#else
379	${LD}l	@X[0],$MSB($inp)
380	${LD}r	@X[0],$LSB($inp)
381#endif
382___
383for ($i=0;$i<16;$i++)
384{ &BODY_00_15($i,@V); unshift(@V,pop(@V)); push(@X,shift(@X)); }
385$code.=<<___;
386	b	.L16_xx
387.align	4
388.L16_xx:
389___
390for (;$i<32;$i++)
391{ &BODY_16_XX($i,@V); unshift(@V,pop(@V)); push(@X,shift(@X)); }
392$code.=<<___;
393	and	@X[6],0xfff
394	li	@X[7],$lastK
395	.set	noreorder
396	bne	@X[6],@X[7],.L16_xx
397	$PTR_ADD $Ktbl,16*$SZ		# Ktbl+=16
398
399	$REG_L	@X[15],16*$SZ($sp)	# restore pointer to the end of input
400	$LD	@X[0],0*$SZ($ctx)
401	$LD	@X[1],1*$SZ($ctx)
402	$LD	@X[2],2*$SZ($ctx)
403	$PTR_ADD $inp,16*$SZ
404	$LD	@X[3],3*$SZ($ctx)
405	$ADDU	$A,@X[0]
406	$LD	@X[4],4*$SZ($ctx)
407	$ADDU	$B,@X[1]
408	$LD	@X[5],5*$SZ($ctx)
409	$ADDU	$C,@X[2]
410	$LD	@X[6],6*$SZ($ctx)
411	$ADDU	$D,@X[3]
412	$LD	@X[7],7*$SZ($ctx)
413	$ADDU	$E,@X[4]
414	$ST	$A,0*$SZ($ctx)
415	$ADDU	$F,@X[5]
416	$ST	$B,1*$SZ($ctx)
417	$ADDU	$G,@X[6]
418	$ST	$C,2*$SZ($ctx)
419	$ADDU	$H,@X[7]
420	$ST	$D,3*$SZ($ctx)
421	$ST	$E,4*$SZ($ctx)
422	$ST	$F,5*$SZ($ctx)
423	$ST	$G,6*$SZ($ctx)
424	$ST	$H,7*$SZ($ctx)
425
426	bne	$inp,@X[15],.Loop
427	$PTR_SUB $Ktbl,`($rounds-16)*$SZ`	# rewind $Ktbl
428
429	$REG_L	$ra,$FRAMESIZE-1*$SZREG($sp)
430	$REG_L	$fp,$FRAMESIZE-2*$SZREG($sp)
431	$REG_L	$s11,$FRAMESIZE-3*$SZREG($sp)
432	$REG_L	$s10,$FRAMESIZE-4*$SZREG($sp)
433	$REG_L	$s9,$FRAMESIZE-5*$SZREG($sp)
434	$REG_L	$s8,$FRAMESIZE-6*$SZREG($sp)
435	$REG_L	$s7,$FRAMESIZE-7*$SZREG($sp)
436	$REG_L	$s6,$FRAMESIZE-8*$SZREG($sp)
437	$REG_L	$s5,$FRAMESIZE-9*$SZREG($sp)
438	$REG_L	$s4,$FRAMESIZE-10*$SZREG($sp)
439___
440$code.=<<___ if ($flavour =~ /nubi/i);
441	$REG_L	$s3,$FRAMESIZE-11*$SZREG($sp)
442	$REG_L	$s2,$FRAMESIZE-12*$SZREG($sp)
443	$REG_L	$s1,$FRAMESIZE-13*$SZREG($sp)
444	$REG_L	$s0,$FRAMESIZE-14*$SZREG($sp)
445	$REG_L	$gp,$FRAMESIZE-15*$SZREG($sp)
446___
447$code.=<<___;
448	jr	$ra
449	$PTR_ADD $sp,$FRAMESIZE
450.end	sha${label}_block_data_order
451
452.rdata
453.align	5
454K${label}:
455___
456if ($SZ==4) {
457$code.=<<___;
458	.word	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
459	.word	0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
460	.word	0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
461	.word	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
462	.word	0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
463	.word	0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
464	.word	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
465	.word	0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
466	.word	0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
467	.word	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
468	.word	0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
469	.word	0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
470	.word	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
471	.word	0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
472	.word	0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
473	.word	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
474___
475} else {
476$code.=<<___;
477	.dword	0x428a2f98d728ae22, 0x7137449123ef65cd
478	.dword	0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
479	.dword	0x3956c25bf348b538, 0x59f111f1b605d019
480	.dword	0x923f82a4af194f9b, 0xab1c5ed5da6d8118
481	.dword	0xd807aa98a3030242, 0x12835b0145706fbe
482	.dword	0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
483	.dword	0x72be5d74f27b896f, 0x80deb1fe3b1696b1
484	.dword	0x9bdc06a725c71235, 0xc19bf174cf692694
485	.dword	0xe49b69c19ef14ad2, 0xefbe4786384f25e3
486	.dword	0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
487	.dword	0x2de92c6f592b0275, 0x4a7484aa6ea6e483
488	.dword	0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
489	.dword	0x983e5152ee66dfab, 0xa831c66d2db43210
490	.dword	0xb00327c898fb213f, 0xbf597fc7beef0ee4
491	.dword	0xc6e00bf33da88fc2, 0xd5a79147930aa725
492	.dword	0x06ca6351e003826f, 0x142929670a0e6e70
493	.dword	0x27b70a8546d22ffc, 0x2e1b21385c26c926
494	.dword	0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
495	.dword	0x650a73548baf63de, 0x766a0abb3c77b2a8
496	.dword	0x81c2c92e47edaee6, 0x92722c851482353b
497	.dword	0xa2bfe8a14cf10364, 0xa81a664bbc423001
498	.dword	0xc24b8b70d0f89791, 0xc76c51a30654be30
499	.dword	0xd192e819d6ef5218, 0xd69906245565a910
500	.dword	0xf40e35855771202a, 0x106aa07032bbd1b8
501	.dword	0x19a4c116b8d2d0c8, 0x1e376c085141ab53
502	.dword	0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
503	.dword	0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
504	.dword	0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
505	.dword	0x748f82ee5defb2fc, 0x78a5636f43172f60
506	.dword	0x84c87814a1f0ab72, 0x8cc702081a6439ec
507	.dword	0x90befffa23631e28, 0xa4506cebde82bde9
508	.dword	0xbef9a3f7b2c67915, 0xc67178f2e372532b
509	.dword	0xca273eceea26619c, 0xd186b8c721c0c207
510	.dword	0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
511	.dword	0x06f067aa72176fba, 0x0a637dc5a2c898a6
512	.dword	0x113f9804bef90dae, 0x1b710b35131c471b
513	.dword	0x28db77f523047d84, 0x32caab7b40c72493
514	.dword	0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
515	.dword	0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
516	.dword	0x5fcb6fab3ad6faec, 0x6c44198c4a475817
517___
518}
519$code.=<<___;
520.asciiz	"SHA${label} for MIPS, CRYPTOGAMS by <appro\@openssl.org>"
521.align	5
522
523___
524
525$code =~ s/\`([^\`]*)\`/eval $1/gem;
526print $code;
527close STDOUT or die "error closing STDOUT: $!";
528