lib/libpmc/pmc.haswelluc.3

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.Dd March 22, 2013
.Dt PMC.HASWELLUC 3
.Os
.Sh NAME
.Nm pmc.haswelluc
.Nd uncore measurement events for
.Tn Intel
.Tn Haswell
family CPUs
.Sh LIBRARY
.Lb libpmc
.Sh SYNOPSIS
.In pmc.h
.Sh DESCRIPTION
.Tn Intel
.Tn "Haswell"
CPUs contain PMCs conforming to version 3 of the
.Tn Intel
performance measurement architecture.
These CPUs contain two classes of PMCs:
.Bl -tag -width "Li PMC_CLASS_UCP"
.It Li PMC_CLASS_UCF
Fixed-function counters that count only one hardware event per counter.
.It Li PMC_CLASS_UCP
Programmable counters that may be configured to count one of a defined
set of hardware events.
.El
.Pp
The number of PMCs available in each class and their widths need to be
determined at run time by calling
.Xr pmc_cpuinfo 3 .
.Pp
Intel Haswell PMCs are documented in
.Rs
.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
.%N "Order Number: 325462-045US"
.%D January 2013
.%Q "Intel Corporation"
.Re
.Ss HASWELL UNCORE FIXED FUNCTION PMCS
These PMCs and their supported events are documented in
.Xr pmc.ucf 3 .
Not all CPUs in this family implement fixed-function counters.
.Ss HASWELL UNCORE PROGRAMMABLE PMCS
The programmable PMCs support the following capabilities:
.Bl -column "PMC_CAP_INTERRUPT" "Support"
.It Em Capability Ta Em Support
.It PMC_CAP_CASCADE Ta \&No
.It PMC_CAP_EDGE Ta Yes
.It PMC_CAP_INTERRUPT Ta \&No
.It PMC_CAP_INVERT Ta Yes
.It PMC_CAP_READ Ta Yes
.It PMC_CAP_PRECISE Ta \&No
.It PMC_CAP_SYSTEM Ta \&No
.It PMC_CAP_TAGGING Ta \&No
.It PMC_CAP_THRESHOLD Ta Yes
.It PMC_CAP_USER Ta \&No
.It PMC_CAP_WRITE Ta Yes
.El
.Ss Event Qualifiers
Event specifiers for these PMCs support the following common
qualifiers:
.Bl -tag -width indent
.It Li cmask= Ns Ar value
Configure the PMC to increment only if the number of configured
events measured in a cycle is greater than or equal to
.Ar value .
.It Li edge
Configure the PMC to count the number of de-asserted to asserted
transitions of the conditions expressed by the other qualifiers.
If specified, the counter will increment only once whenever a
condition becomes true, irrespective of the number of clocks during
which the condition remains true.
.It Li inv
Invert the sense of comparison when the
.Dq Li cmask
qualifier is present, making the counter increment when the number of
events per cycle is less than the value specified by the
.Dq Li cmask
qualifier.
.El
.Ss Event Specifiers (Programmable PMCs)
Haswell programmable PMCs support the following events:
.Bl -tag -width indent
.It Li UNC_CBO_XSNP_RESPONSE.MISS
.Pq Event 22H , Umask 01H
A snoop misses in some processor core.
.It Li UNC_CBO_XSNP_RESPONSE.INVAL
.Pq Event 22H , Umask 02H
A snoop invalidates a non-modified line in some
processor core.
.It Li UNC_CBO_XSNP_RESPONSE.HIT
.Pq Event 22H , Umask 04H
A snoop hits a non-modified line in some processor
core.
.It Li UNC_CBO_XSNP_RESPONSE.HITM
.Pq Event 22H , Umask 08H
A snoop hits a modified line in some processor core.
.It Li UNC_CBO_XSNP_RESPONSE.INVAL_M
.Pq Event 22H , Umask 10H
A snoop invalidates a modified line in some processor
core.
.It Li UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER
.Pq Event 22H , Umask 20H
Filter on cross-core snoops initiated by this Cbox due
to external snoop request.
.It Li UNC_CBO_XSNP_RESPONSE.XCORE_FILTER
.Pq Event 22H , Umask 40H
Filter on cross-core snoops initiated by this Cbox due
to processor core memory request.
.It Li UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER
.Pq Event 22H , Umask 80H
Filter on cross-core snoops initiated by this Cbox due
to LLC eviction.
.It Li UNC_CBO_CACHE_LOOKUP.M
.Pq Event 34H , Umask 01H
LLC lookup request that access cache and found line in
M-state.
.It Li UNC_CBO_CACHE_LOOKUP.ES
.Pq Event 34H , Umask 06H
LLC lookup request that access cache and found line in
E or S state.
.It Li UNC_CBO_CACHE_LOOKUP.I
.Pq Event 34H , Umask 08H
LLC lookup request that access cache and found line in
I-state.
.It Li UNC_CBO_CACHE_LOOKUP.READ_FILTER
.Pq Event 34H , Umask 10H
Filter on processor core initiated cacheable read
requests.
Must combine with at least one of 01H, 02H, 04H, 08H.
.It Li UNC_CBO_CACHE_LOOKUP.WRITE_FILTER
.Pq Event 34H , Umask 20H
Filter on processor core initiated cacheable write requests.
Must combine with at least one of 01H, 02H, 04H, 08H.
.It Li UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER
.Pq Event 34H , Umask 40H
Filter on external snoop requests.
Must combine with at least one of 01H, 02H, 04H, 08H.
.It Li UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER
.Pq Event 34H , Umask 80H
Filter on any IRQ or IPQ initiated requests including
uncacheable, non-coherent requests.
Must combine with at least one of 01H, 02H, 04H, 08H.
.It Li UNC_ARB_TRK_OCCUPANCY.ALL
.Pq Event 80H , Umask 01H
Counts cycles weighted by the number of requests
waiting for data returning from the memory controller.
Accounts for coherent and non-coherent requests
initiated by IA cores, processor graphic units, or LLC.
.It Li UNC_ARB_TRK_REQUEST.ALL
.Pq Event 81H , Umask 01H
Counts the number of coherent and in-coherent
requests initiated by IA cores, processor graphic units,
or LLC.
.It Li UNC_ARB_TRK_REQUEST.WRITES
.Pq Event 81H , Umask 20H
Counts the number of allocated write entries, include
full, partial, and LLC evictions.
.It Li UNC_ARB_TRK_REQUEST.EVICTIONS
.Pq Event 81H , Umask 80H
Counts the number of LLC evictions allocated.
.It Li UNC_ARB_COH , Umask TRK_OCCUPANCY.ALL
.Pq Event 83H , Umask 01H
Cycles weighted by number of requests pending in
Coherency Tracker.
.It Li UNC_ARB_COH , Umask TRK_REQUEST.ALL
.Pq Event 84H , Umask 01H
Number of requests allocated in Coherency Tracker.
.El
.Sh SEE ALSO
.Xr pmc 3 ,
.Xr pmc.atom 3 ,
.Xr pmc.core 3 ,
.Xr pmc.corei7 3 ,
.Xr pmc.corei7uc 3 ,
.Xr pmc.haswell 3 ,
.Xr pmc.iaf 3 ,
.Xr pmc.k7 3 ,
.Xr pmc.k8 3 ,
.Xr pmc.sandybridge 3 ,
.Xr pmc.sandybridgeuc 3 ,
.Xr pmc.sandybridgexeon 3 ,
.Xr pmc.soft 3 ,
.Xr pmc.tsc 3 ,
.Xr pmc.ucf 3 ,
.Xr pmc.westmere 3 ,
.Xr pmc.westmereuc 3 ,
.Xr pmc_cpuinfo 3 ,
.Xr pmclog 3 ,
.Xr hwpmc 4
.Sh HISTORY
The
.Nm pmc
library first appeared in
.Fx 6.0 .
.Sh AUTHORS
.An -nosplit
The
.Lb libpmc
library was written by
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
The support for the Haswell
microarchitecture was added by
.An Hiren Panchasara Aq Mt hiren.panchasara@gmail.com .