1[
2    {
3        "ArchStdEvent": "MEM_ACCESS"
4    },
5    {
6        "ArchStdEvent": "MEM_ACCESS_RD"
7    },
8    {
9        "ArchStdEvent": "MEM_ACCESS_WR"
10    },
11    {
12        "ArchStdEvent": "UNALIGNED_LD_SPEC"
13    },
14    {
15        "ArchStdEvent": "UNALIGNED_ST_SPEC"
16    },
17    {
18        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
19    }
20]
21