1[
2    {
3        "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5",
6        "EventCode": "0xe6",
7        "EventName": "BACLEARS.ANY",
8        "PEBScounters": "0,1,2,3,4,5",
9        "SampleAfterValue": "100003",
10        "UMask": "0x1",
11        "Unit": "cpu_atom"
12    },
13    {
14        "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5",
17        "EventCode": "0x80",
18        "EventName": "ICACHE.ACCESSES",
19        "PEBScounters": "0,1,2,3,4,5",
20        "SampleAfterValue": "200003",
21        "UMask": "0x3",
22        "Unit": "cpu_atom"
23    },
24    {
25        "BriefDescription": "Counts the number of instruction cache misses.",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3,4,5",
28        "EventCode": "0x80",
29        "EventName": "ICACHE.MISSES",
30        "PEBScounters": "0,1,2,3,4,5",
31        "SampleAfterValue": "200003",
32        "UMask": "0x2",
33        "Unit": "cpu_atom"
34    },
35    {
36        "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
37        "CollectPEBSRecord": "2",
38        "Counter": "0,1,2,3",
39        "EventCode": "0x87",
40        "EventName": "DECODE.LCP",
41        "PEBScounters": "0,1,2,3",
42        "SampleAfterValue": "500009",
43        "UMask": "0x1",
44        "Unit": "cpu_core"
45    },
46    {
47        "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
48        "CollectPEBSRecord": "2",
49        "Counter": "0,1,2,3",
50        "EventCode": "0x61",
51        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
52        "PEBScounters": "0,1,2,3",
53        "SampleAfterValue": "100003",
54        "UMask": "0x2",
55        "Unit": "cpu_core"
56    },
57    {
58        "BriefDescription": "Retired Instructions who experienced DSB miss.",
59        "CollectPEBSRecord": "2",
60        "Counter": "0,1,2,3,4,5,6,7",
61        "EventCode": "0xc6",
62        "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
63        "MSRIndex": "0x3F7",
64        "MSRValue": "0x1",
65        "PEBS": "1",
66        "PEBScounters": "0,1,2,3,4,5,6,7",
67        "SampleAfterValue": "100007",
68        "TakenAlone": "1",
69        "UMask": "0x1",
70        "Unit": "cpu_core"
71    },
72    {
73        "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
74        "CollectPEBSRecord": "2",
75        "Counter": "0,1,2,3,4,5,6,7",
76        "EventCode": "0xc6",
77        "EventName": "FRONTEND_RETIRED.DSB_MISS",
78        "MSRIndex": "0x3F7",
79        "MSRValue": "0x11",
80        "PEBS": "1",
81        "PEBScounters": "0,1,2,3,4,5,6,7",
82        "SampleAfterValue": "100007",
83        "TakenAlone": "1",
84        "UMask": "0x1",
85        "Unit": "cpu_core"
86    },
87    {
88        "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
89        "CollectPEBSRecord": "2",
90        "Counter": "0,1,2,3,4,5,6,7",
91        "EventCode": "0xc6",
92        "EventName": "FRONTEND_RETIRED.ITLB_MISS",
93        "MSRIndex": "0x3F7",
94        "MSRValue": "0x14",
95        "PEBS": "1",
96        "PEBScounters": "0,1,2,3,4,5,6,7",
97        "SampleAfterValue": "100007",
98        "TakenAlone": "1",
99        "UMask": "0x1",
100        "Unit": "cpu_core"
101    },
102    {
103        "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
104        "CollectPEBSRecord": "2",
105        "Counter": "0,1,2,3,4,5,6,7",
106        "EventCode": "0xc6",
107        "EventName": "FRONTEND_RETIRED.L1I_MISS",
108        "MSRIndex": "0x3F7",
109        "MSRValue": "0x12",
110        "PEBS": "1",
111        "PEBScounters": "0,1,2,3,4,5,6,7",
112        "SampleAfterValue": "100007",
113        "TakenAlone": "1",
114        "UMask": "0x1",
115        "Unit": "cpu_core"
116    },
117    {
118        "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
119        "CollectPEBSRecord": "2",
120        "Counter": "0,1,2,3,4,5,6,7",
121        "EventCode": "0xc6",
122        "EventName": "FRONTEND_RETIRED.L2_MISS",
123        "MSRIndex": "0x3F7",
124        "MSRValue": "0x13",
125        "PEBS": "1",
126        "PEBScounters": "0,1,2,3,4,5,6,7",
127        "SampleAfterValue": "100007",
128        "TakenAlone": "1",
129        "UMask": "0x1",
130        "Unit": "cpu_core"
131    },
132    {
133        "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
134        "CollectPEBSRecord": "2",
135        "Counter": "0,1,2,3,4,5,6,7",
136        "EventCode": "0xc6",
137        "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
138        "MSRIndex": "0x3F7",
139        "MSRValue": "0x600106",
140        "PEBS": "1",
141        "PEBScounters": "0,1,2,3,4,5,6,7",
142        "SampleAfterValue": "100007",
143        "TakenAlone": "1",
144        "UMask": "0x1",
145        "Unit": "cpu_core"
146    },
147    {
148        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
149        "CollectPEBSRecord": "2",
150        "Counter": "0,1,2,3,4,5,6,7",
151        "EventCode": "0xc6",
152        "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
153        "MSRIndex": "0x3F7",
154        "MSRValue": "0x608006",
155        "PEBS": "1",
156        "PEBScounters": "0,1,2,3,4,5,6,7",
157        "SampleAfterValue": "100007",
158        "TakenAlone": "1",
159        "UMask": "0x1",
160        "Unit": "cpu_core"
161    },
162    {
163        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
164        "CollectPEBSRecord": "2",
165        "Counter": "0,1,2,3,4,5,6,7",
166        "EventCode": "0xc6",
167        "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
168        "MSRIndex": "0x3F7",
169        "MSRValue": "0x601006",
170        "PEBS": "1",
171        "PEBScounters": "0,1,2,3,4,5,6,7",
172        "SampleAfterValue": "100007",
173        "TakenAlone": "1",
174        "UMask": "0x1",
175        "Unit": "cpu_core"
176    },
177    {
178        "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
179        "CollectPEBSRecord": "2",
180        "Counter": "0,1,2,3,4,5,6,7",
181        "EventCode": "0xc6",
182        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
183        "MSRIndex": "0x3F7",
184        "MSRValue": "0x600206",
185        "PEBS": "1",
186        "PEBScounters": "0,1,2,3,4,5,6,7",
187        "SampleAfterValue": "100007",
188        "TakenAlone": "1",
189        "UMask": "0x1",
190        "Unit": "cpu_core"
191    },
192    {
193        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
194        "CollectPEBSRecord": "2",
195        "Counter": "0,1,2,3,4,5,6,7",
196        "EventCode": "0xc6",
197        "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
198        "MSRIndex": "0x3F7",
199        "MSRValue": "0x610006",
200        "PEBS": "1",
201        "PEBScounters": "0,1,2,3,4,5,6,7",
202        "SampleAfterValue": "100007",
203        "TakenAlone": "1",
204        "UMask": "0x1",
205        "Unit": "cpu_core"
206    },
207    {
208        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
209        "CollectPEBSRecord": "2",
210        "Counter": "0,1,2,3,4,5,6,7",
211        "EventCode": "0xc6",
212        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
213        "MSRIndex": "0x3F7",
214        "MSRValue": "0x100206",
215        "PEBS": "1",
216        "PEBScounters": "0,1,2,3,4,5,6,7",
217        "SampleAfterValue": "100007",
218        "TakenAlone": "1",
219        "UMask": "0x1",
220        "Unit": "cpu_core"
221    },
222    {
223        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
224        "CollectPEBSRecord": "2",
225        "Counter": "0,1,2,3,4,5,6,7",
226        "EventCode": "0xc6",
227        "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
228        "MSRIndex": "0x3F7",
229        "MSRValue": "0x602006",
230        "PEBS": "1",
231        "PEBScounters": "0,1,2,3,4,5,6,7",
232        "SampleAfterValue": "100007",
233        "TakenAlone": "1",
234        "UMask": "0x1",
235        "Unit": "cpu_core"
236    },
237    {
238        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
239        "CollectPEBSRecord": "2",
240        "Counter": "0,1,2,3,4,5,6,7",
241        "EventCode": "0xc6",
242        "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
243        "MSRIndex": "0x3F7",
244        "MSRValue": "0x600406",
245        "PEBS": "1",
246        "PEBScounters": "0,1,2,3,4,5,6,7",
247        "SampleAfterValue": "100007",
248        "TakenAlone": "1",
249        "UMask": "0x1",
250        "Unit": "cpu_core"
251    },
252    {
253        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
254        "CollectPEBSRecord": "2",
255        "Counter": "0,1,2,3,4,5,6,7",
256        "EventCode": "0xc6",
257        "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
258        "MSRIndex": "0x3F7",
259        "MSRValue": "0x620006",
260        "PEBS": "1",
261        "PEBScounters": "0,1,2,3,4,5,6,7",
262        "SampleAfterValue": "100007",
263        "TakenAlone": "1",
264        "UMask": "0x1",
265        "Unit": "cpu_core"
266    },
267    {
268        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
269        "CollectPEBSRecord": "2",
270        "Counter": "0,1,2,3,4,5,6,7",
271        "EventCode": "0xc6",
272        "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
273        "MSRIndex": "0x3F7",
274        "MSRValue": "0x604006",
275        "PEBS": "1",
276        "PEBScounters": "0,1,2,3,4,5,6,7",
277        "SampleAfterValue": "100007",
278        "TakenAlone": "1",
279        "UMask": "0x1",
280        "Unit": "cpu_core"
281    },
282    {
283        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
284        "CollectPEBSRecord": "2",
285        "Counter": "0,1,2,3,4,5,6,7",
286        "EventCode": "0xc6",
287        "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
288        "MSRIndex": "0x3F7",
289        "MSRValue": "0x600806",
290        "PEBS": "1",
291        "PEBScounters": "0,1,2,3,4,5,6,7",
292        "SampleAfterValue": "100007",
293        "TakenAlone": "1",
294        "UMask": "0x1",
295        "Unit": "cpu_core"
296    },
297    {
298        "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
299        "CollectPEBSRecord": "2",
300        "Counter": "0,1,2,3,4,5,6,7",
301        "EventCode": "0xc6",
302        "EventName": "FRONTEND_RETIRED.STLB_MISS",
303        "MSRIndex": "0x3F7",
304        "MSRValue": "0x15",
305        "PEBS": "1",
306        "PEBScounters": "0,1,2,3,4,5,6,7",
307        "SampleAfterValue": "100007",
308        "TakenAlone": "1",
309        "UMask": "0x1",
310        "Unit": "cpu_core"
311    },
312    {
313        "BriefDescription": "TBD",
314        "CollectPEBSRecord": "2",
315        "Counter": "0,1,2,3,4,5,6,7",
316        "EventCode": "0xc6",
317        "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
318        "MSRIndex": "0x3F7",
319        "MSRValue": "0x17",
320        "PEBS": "1",
321        "PEBScounters": "0,1,2,3,4,5,6,7",
322        "SampleAfterValue": "100007",
323        "TakenAlone": "1",
324        "UMask": "0x1",
325        "Unit": "cpu_core"
326    },
327    {
328        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
329        "CollectPEBSRecord": "2",
330        "Counter": "0,1,2,3",
331        "EventCode": "0x80",
332        "EventName": "ICACHE_DATA.STALLS",
333        "PEBScounters": "0,1,2,3",
334        "SampleAfterValue": "500009",
335        "UMask": "0x4",
336        "Unit": "cpu_core"
337    },
338    {
339        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
340        "CollectPEBSRecord": "2",
341        "Counter": "0,1,2,3",
342        "EventCode": "0x83",
343        "EventName": "ICACHE_TAG.STALLS",
344        "PEBScounters": "0,1,2,3",
345        "SampleAfterValue": "200003",
346        "UMask": "0x4",
347        "Unit": "cpu_core"
348    },
349    {
350        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
351        "CollectPEBSRecord": "2",
352        "Counter": "0,1,2,3",
353        "CounterMask": "1",
354        "EventCode": "0x79",
355        "EventName": "IDQ.DSB_CYCLES_ANY",
356        "PEBScounters": "0,1,2,3",
357        "SampleAfterValue": "2000003",
358        "UMask": "0x8",
359        "Unit": "cpu_core"
360    },
361    {
362        "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
363        "CollectPEBSRecord": "2",
364        "Counter": "0,1,2,3",
365        "CounterMask": "6",
366        "EventCode": "0x79",
367        "EventName": "IDQ.DSB_CYCLES_OK",
368        "PEBScounters": "0,1,2,3",
369        "SampleAfterValue": "2000003",
370        "UMask": "0x8",
371        "Unit": "cpu_core"
372    },
373    {
374        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
375        "CollectPEBSRecord": "2",
376        "Counter": "0,1,2,3",
377        "EventCode": "0x79",
378        "EventName": "IDQ.DSB_UOPS",
379        "PEBScounters": "0,1,2,3",
380        "SampleAfterValue": "2000003",
381        "UMask": "0x8",
382        "Unit": "cpu_core"
383    },
384    {
385        "BriefDescription": "Cycles MITE is delivering any Uop",
386        "CollectPEBSRecord": "2",
387        "Counter": "0,1,2,3",
388        "CounterMask": "1",
389        "EventCode": "0x79",
390        "EventName": "IDQ.MITE_CYCLES_ANY",
391        "PEBScounters": "0,1,2,3",
392        "SampleAfterValue": "2000003",
393        "UMask": "0x4",
394        "Unit": "cpu_core"
395    },
396    {
397        "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
398        "CollectPEBSRecord": "2",
399        "Counter": "0,1,2,3",
400        "CounterMask": "6",
401        "EventCode": "0x79",
402        "EventName": "IDQ.MITE_CYCLES_OK",
403        "PEBScounters": "0,1,2,3",
404        "SampleAfterValue": "2000003",
405        "UMask": "0x4",
406        "Unit": "cpu_core"
407    },
408    {
409        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
410        "CollectPEBSRecord": "2",
411        "Counter": "0,1,2,3",
412        "EventCode": "0x79",
413        "EventName": "IDQ.MITE_UOPS",
414        "PEBScounters": "0,1,2,3",
415        "SampleAfterValue": "2000003",
416        "UMask": "0x4",
417        "Unit": "cpu_core"
418    },
419    {
420        "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
421        "CollectPEBSRecord": "2",
422        "Counter": "0,1,2,3",
423        "CounterMask": "1",
424        "EventCode": "0x79",
425        "EventName": "IDQ.MS_CYCLES_ANY",
426        "PEBScounters": "0,1,2,3",
427        "SampleAfterValue": "2000003",
428        "UMask": "0x20",
429        "Unit": "cpu_core"
430    },
431    {
432        "BriefDescription": "Number of switches from DSB or MITE to the MS",
433        "CollectPEBSRecord": "2",
434        "Counter": "0,1,2,3",
435        "CounterMask": "1",
436        "EdgeDetect": "1",
437        "EventCode": "0x79",
438        "EventName": "IDQ.MS_SWITCHES",
439        "PEBScounters": "0,1,2,3",
440        "SampleAfterValue": "100003",
441        "UMask": "0x20",
442        "Unit": "cpu_core"
443    },
444    {
445        "BriefDescription": "Uops delivered to IDQ while MS is busy",
446        "CollectPEBSRecord": "2",
447        "Counter": "0,1,2,3",
448        "EventCode": "0x79",
449        "EventName": "IDQ.MS_UOPS",
450        "PEBScounters": "0,1,2,3",
451        "SampleAfterValue": "1000003",
452        "UMask": "0x20",
453        "Unit": "cpu_core"
454    },
455    {
456        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
457        "CollectPEBSRecord": "2",
458        "Counter": "0,1,2,3,4,5,6,7",
459        "EventCode": "0x9c",
460        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
461        "PEBScounters": "0,1,2,3,4,5,6,7",
462        "SampleAfterValue": "1000003",
463        "UMask": "0x1",
464        "Unit": "cpu_core"
465    },
466    {
467        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
468        "CollectPEBSRecord": "2",
469        "Counter": "0,1,2,3,4,5,6,7",
470        "CounterMask": "6",
471        "EventCode": "0x9c",
472        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
473        "PEBScounters": "0,1,2,3,4,5,6,7",
474        "SampleAfterValue": "1000003",
475        "UMask": "0x1",
476        "Unit": "cpu_core"
477    },
478    {
479        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
480        "CollectPEBSRecord": "2",
481        "Counter": "0,1,2,3,4,5,6,7",
482        "CounterMask": "1",
483        "EventCode": "0x9c",
484        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
485        "Invert": "1",
486        "PEBScounters": "0,1,2,3,4,5,6,7",
487        "SampleAfterValue": "1000003",
488        "UMask": "0x1",
489        "Unit": "cpu_core"
490    }
491]