1[
2    {
3        "BriefDescription": "Number of clocks",
4        "Counter": "0,1,2,3,4",
5        "CounterType": "PGMABLE",
6        "EventCode": "0x01",
7        "EventName": "UNC_M_CLOCKTICKS",
8        "PerPkg": "1",
9        "Unit": "iMC"
10    },
11    {
12        "BriefDescription": "Incoming VC0 read request",
13        "Counter": "0,1,2,3,4",
14        "CounterType": "PGMABLE",
15        "EventCode": "0x02",
16        "EventName": "UNC_M_VC0_REQUESTS_RD",
17        "PerPkg": "1",
18        "Unit": "iMC"
19    },
20    {
21        "BriefDescription": "Incoming VC0 write request",
22        "Counter": "0,1,2,3,4",
23        "CounterType": "PGMABLE",
24        "EventCode": "0x03",
25        "EventName": "UNC_M_VC0_REQUESTS_WR",
26        "PerPkg": "1",
27        "Unit": "iMC"
28    },
29    {
30        "BriefDescription": "Incoming VC1 read request",
31        "Counter": "0,1,2,3,4",
32        "CounterType": "PGMABLE",
33        "EventCode": "0x04",
34        "EventName": "UNC_M_VC1_REQUESTS_RD",
35        "PerPkg": "1",
36        "Unit": "iMC"
37    },
38    {
39        "BriefDescription": "Incoming VC1 write request",
40        "Counter": "0,1,2,3,4",
41        "CounterType": "PGMABLE",
42        "EventCode": "0x05",
43        "EventName": "UNC_M_VC1_REQUESTS_WR",
44        "PerPkg": "1",
45        "Unit": "iMC"
46    },
47    {
48        "BriefDescription": "Incoming read prefetch request from IA",
49        "Counter": "0,1,2,3,4",
50        "CounterType": "PGMABLE",
51        "EventCode": "0x0A",
52        "EventName": "UNC_M_PREFETCH_RD",
53        "PerPkg": "1",
54        "Unit": "iMC"
55    },
56    {
57        "BriefDescription": "Any Rank at Hot state",
58        "Counter": "0,1,2,3,4",
59        "CounterType": "PGMABLE",
60        "EventCode": "0x19",
61        "EventName": "UNC_M_DRAM_THERMAL_HOT",
62        "PerPkg": "1",
63        "Unit": "iMC"
64    },
65    {
66        "BriefDescription": "Any Rank at Warm state",
67        "Counter": "0,1,2,3,4",
68        "CounterType": "PGMABLE",
69        "EventCode": "0x1A",
70        "EventName": "UNC_M_DRAM_THERMAL_WARM",
71        "PerPkg": "1",
72        "Unit": "iMC"
73    },
74    {
75        "BriefDescription": "incoming read request page status is Page Hit",
76        "Counter": "0,1,2,3,4",
77        "CounterType": "PGMABLE",
78        "EventCode": "0x1C",
79        "EventName": "UNC_M_DRAM_PAGE_HIT_RD",
80        "PerPkg": "1",
81        "Unit": "iMC"
82    },
83    {
84        "BriefDescription": "incoming read request page status is Page Empty",
85        "Counter": "0,1,2,3,4",
86        "CounterType": "PGMABLE",
87        "EventCode": "0x1D",
88        "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
89        "PerPkg": "1",
90        "Unit": "iMC"
91    },
92    {
93        "BriefDescription": "incoming read request page status is Page Miss",
94        "Counter": "0,1,2,3,4",
95        "CounterType": "PGMABLE",
96        "EventCode": "0x1E",
97        "EventName": "UNC_M_DRAM_PAGE_MISS_RD",
98        "PerPkg": "1",
99        "Unit": "iMC"
100    },
101    {
102        "BriefDescription": "incoming write request page status is Page Hit",
103        "Counter": "0,1,2,3,4",
104        "CounterType": "PGMABLE",
105        "EventCode": "0x1F",
106        "EventName": "UNC_M_DRAM_PAGE_HIT_WR",
107        "PerPkg": "1",
108        "Unit": "iMC"
109    },
110    {
111        "BriefDescription": "incoming write request page status is Page Empty",
112        "Counter": "0,1,2,3,4",
113        "CounterType": "PGMABLE",
114        "EventCode": "0x20",
115        "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
116        "PerPkg": "1",
117        "Unit": "iMC"
118    },
119    {
120        "BriefDescription": "incoming write request page status is Page Miss",
121        "Counter": "0,1,2,3,4",
122        "CounterType": "PGMABLE",
123        "EventCode": "0x21",
124        "EventName": "UNC_M_DRAM_PAGE_MISS_WR",
125        "PerPkg": "1",
126        "Unit": "iMC"
127    },
128    {
129        "BriefDescription": "Read CAS command sent to DRAM",
130        "Counter": "0,1,2,3,4",
131        "CounterType": "PGMABLE",
132        "EventCode": "0x22",
133        "EventName": "UNC_M_CAS_COUNT_RD",
134        "PerPkg": "1",
135        "Unit": "iMC"
136    },
137    {
138        "BriefDescription": "Write CAS command sent to DRAM",
139        "Counter": "0,1,2,3,4",
140        "CounterType": "PGMABLE",
141        "EventCode": "0x23",
142        "EventName": "UNC_M_CAS_COUNT_WR",
143        "PerPkg": "1",
144        "Unit": "iMC"
145    },
146    {
147        "BriefDescription": "ACT command for a read request sent to DRAM",
148        "Counter": "0,1,2,3,4",
149        "CounterType": "PGMABLE",
150        "EventCode": "0x24",
151        "EventName": "UNC_M_ACT_COUNT_RD",
152        "PerPkg": "1",
153        "Unit": "iMC"
154    },
155    {
156        "BriefDescription": "ACT command for a write request sent to DRAM",
157        "Counter": "0,1,2,3,4",
158        "CounterType": "PGMABLE",
159        "EventCode": "0x25",
160        "EventName": "UNC_M_ACT_COUNT_WR",
161        "PerPkg": "1",
162        "Unit": "iMC"
163    },
164    {
165        "BriefDescription": "ACT command sent to DRAM",
166        "Counter": "0,1,2,3,4",
167        "CounterType": "PGMABLE",
168        "EventCode": "0x26",
169        "EventName": "UNC_M_ACT_COUNT_TOTAL",
170        "PerPkg": "1",
171        "Unit": "iMC"
172    },
173    {
174        "BriefDescription": "PRE command sent to DRAM for a read/write request",
175        "Counter": "0,1,2,3,4",
176        "CounterType": "PGMABLE",
177        "EventCode": "0x27",
178        "EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
179        "PerPkg": "1",
180        "Unit": "iMC"
181    },
182    {
183        "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
184        "Counter": "0,1,2,3,4",
185        "CounterType": "PGMABLE",
186        "EventCode": "0x28",
187        "EventName": "UNC_M_PRE_COUNT_IDLE",
188        "PerPkg": "1",
189        "Unit": "iMC"
190    },
191    {
192        "BriefDescription": "Counts every 64B read  request entering the Memory Controller 0 to DRAM (sum of all channels)",
193        "CounterType": "FREERUN",
194        "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
195        "PerPkg": "1",
196        "Unit": "iMC"
197    },
198    {
199        "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)",
200        "Counter": "3",
201        "CounterType": "FREERUN",
202        "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
203        "PerPkg": "1",
204        "Unit": "iMC"
205    },
206    {
207        "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
208        "Counter": "1",
209        "CounterType": "FREERUN",
210        "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
211        "PerPkg": "1",
212        "Unit": "iMC"
213    },
214    {
215        "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
216        "Counter": "4",
217        "CounterType": "FREERUN",
218        "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
219        "PerPkg": "1",
220        "Unit": "iMC"
221    }
222]
223