1[
2    {
3        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5",
6        "EventCode": "0x08",
7        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
8        "PEBScounters": "0,1,2,3,4,5",
9        "SampleAfterValue": "200003",
10        "UMask": "0xe",
11        "Unit": "cpu_atom"
12    },
13    {
14        "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5",
17        "EventCode": "0x49",
18        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
19        "PEBScounters": "0,1,2,3,4,5",
20        "SampleAfterValue": "2000003",
21        "UMask": "0xe",
22        "Unit": "cpu_atom"
23    },
24    {
25        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires.",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3,4,5",
28        "EventCode": "0x05",
29        "EventName": "LD_HEAD.DTLB_MISS_AT_RET",
30        "PEBScounters": "0,1,2,3,4,5",
31        "SampleAfterValue": "1000003",
32        "UMask": "0x90",
33        "Unit": "cpu_atom"
34    },
35    {
36        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
37        "CollectPEBSRecord": "2",
38        "Counter": "0,1,2,3",
39        "EventCode": "0x12",
40        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
41        "PEBScounters": "0,1,2,3",
42        "SampleAfterValue": "100003",
43        "UMask": "0x20",
44        "Unit": "cpu_core"
45    },
46    {
47        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
48        "CollectPEBSRecord": "2",
49        "Counter": "0,1,2,3",
50        "CounterMask": "1",
51        "EventCode": "0x12",
52        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
53        "PEBScounters": "0,1,2,3",
54        "SampleAfterValue": "100003",
55        "UMask": "0x10",
56        "Unit": "cpu_core"
57    },
58    {
59        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
60        "CollectPEBSRecord": "2",
61        "Counter": "0,1,2,3",
62        "EventCode": "0x12",
63        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
64        "PEBScounters": "0,1,2,3",
65        "SampleAfterValue": "100003",
66        "UMask": "0xe",
67        "Unit": "cpu_core"
68    },
69    {
70        "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
71        "CollectPEBSRecord": "2",
72        "Counter": "0,1,2,3",
73        "EventCode": "0x12",
74        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
75        "PEBScounters": "0,1,2,3",
76        "SampleAfterValue": "100003",
77        "UMask": "0x8",
78        "Unit": "cpu_core"
79    },
80    {
81        "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
82        "CollectPEBSRecord": "2",
83        "Counter": "0,1,2,3",
84        "EventCode": "0x12",
85        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
86        "PEBScounters": "0,1,2,3",
87        "SampleAfterValue": "100003",
88        "UMask": "0x4",
89        "Unit": "cpu_core"
90    },
91    {
92        "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
93        "CollectPEBSRecord": "2",
94        "Counter": "0,1,2,3",
95        "EventCode": "0x12",
96        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
97        "PEBScounters": "0,1,2,3",
98        "SampleAfterValue": "100003",
99        "UMask": "0x2",
100        "Unit": "cpu_core"
101    },
102    {
103        "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
104        "CollectPEBSRecord": "2",
105        "Counter": "0,1,2,3",
106        "EventCode": "0x12",
107        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
108        "PEBScounters": "0,1,2,3",
109        "SampleAfterValue": "100003",
110        "UMask": "0x10",
111        "Unit": "cpu_core"
112    },
113    {
114        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
115        "CollectPEBSRecord": "2",
116        "Counter": "0,1,2,3",
117        "EventCode": "0x13",
118        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
119        "PEBScounters": "0,1,2,3",
120        "SampleAfterValue": "100003",
121        "UMask": "0x20",
122        "Unit": "cpu_core"
123    },
124    {
125        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
126        "CollectPEBSRecord": "2",
127        "Counter": "0,1,2,3",
128        "CounterMask": "1",
129        "EventCode": "0x13",
130        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
131        "PEBScounters": "0,1,2,3",
132        "SampleAfterValue": "100003",
133        "UMask": "0x10",
134        "Unit": "cpu_core"
135    },
136    {
137        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
138        "CollectPEBSRecord": "2",
139        "Counter": "0,1,2,3",
140        "EventCode": "0x13",
141        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
142        "PEBScounters": "0,1,2,3",
143        "SampleAfterValue": "100003",
144        "UMask": "0xe",
145        "Unit": "cpu_core"
146    },
147    {
148        "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
149        "CollectPEBSRecord": "2",
150        "Counter": "0,1,2,3",
151        "EventCode": "0x13",
152        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
153        "PEBScounters": "0,1,2,3",
154        "SampleAfterValue": "100003",
155        "UMask": "0x8",
156        "Unit": "cpu_core"
157    },
158    {
159        "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
160        "CollectPEBSRecord": "2",
161        "Counter": "0,1,2,3",
162        "EventCode": "0x13",
163        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
164        "PEBScounters": "0,1,2,3",
165        "SampleAfterValue": "100003",
166        "UMask": "0x4",
167        "Unit": "cpu_core"
168    },
169    {
170        "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
171        "CollectPEBSRecord": "2",
172        "Counter": "0,1,2,3",
173        "EventCode": "0x13",
174        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
175        "PEBScounters": "0,1,2,3",
176        "SampleAfterValue": "100003",
177        "UMask": "0x2",
178        "Unit": "cpu_core"
179    },
180    {
181        "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
182        "CollectPEBSRecord": "2",
183        "Counter": "0,1,2,3",
184        "EventCode": "0x13",
185        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
186        "PEBScounters": "0,1,2,3",
187        "SampleAfterValue": "100003",
188        "UMask": "0x10",
189        "Unit": "cpu_core"
190    },
191    {
192        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
193        "CollectPEBSRecord": "2",
194        "Counter": "0,1,2,3",
195        "EventCode": "0x11",
196        "EventName": "ITLB_MISSES.STLB_HIT",
197        "PEBScounters": "0,1,2,3",
198        "SampleAfterValue": "100003",
199        "UMask": "0x20",
200        "Unit": "cpu_core"
201    },
202    {
203        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
204        "CollectPEBSRecord": "2",
205        "Counter": "0,1,2,3",
206        "CounterMask": "1",
207        "EventCode": "0x11",
208        "EventName": "ITLB_MISSES.WALK_ACTIVE",
209        "PEBScounters": "0,1,2,3",
210        "SampleAfterValue": "100003",
211        "UMask": "0x10",
212        "Unit": "cpu_core"
213    },
214    {
215        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
216        "CollectPEBSRecord": "2",
217        "Counter": "0,1,2,3",
218        "EventCode": "0x11",
219        "EventName": "ITLB_MISSES.WALK_COMPLETED",
220        "PEBScounters": "0,1,2,3",
221        "SampleAfterValue": "100003",
222        "UMask": "0xe",
223        "Unit": "cpu_core"
224    },
225    {
226        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
227        "CollectPEBSRecord": "2",
228        "Counter": "0,1,2,3",
229        "EventCode": "0x11",
230        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
231        "PEBScounters": "0,1,2,3",
232        "SampleAfterValue": "100003",
233        "UMask": "0x4",
234        "Unit": "cpu_core"
235    },
236    {
237        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
238        "CollectPEBSRecord": "2",
239        "Counter": "0,1,2,3",
240        "EventCode": "0x11",
241        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
242        "PEBScounters": "0,1,2,3",
243        "SampleAfterValue": "100003",
244        "UMask": "0x2",
245        "Unit": "cpu_core"
246    },
247    {
248        "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
249        "CollectPEBSRecord": "2",
250        "Counter": "0,1,2,3",
251        "EventCode": "0x11",
252        "EventName": "ITLB_MISSES.WALK_PENDING",
253        "PEBScounters": "0,1,2,3",
254        "SampleAfterValue": "100003",
255        "UMask": "0x10",
256        "Unit": "cpu_core"
257    }
258]