1[
2    {
3        "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x49",
7        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
8        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
9        "SampleAfterValue": "100003",
10        "UMask": "0x4"
11    },
12    {
13        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
14        "Counter": "0,1,2,3",
15        "CounterHTOff": "0,1,2,3,4,5,6,7",
16        "EventCode": "0x85",
17        "EventName": "ITLB_MISSES.WALK_PENDING",
18        "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
19        "SampleAfterValue": "100003",
20        "UMask": "0x10"
21    },
22    {
23        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
24        "Counter": "0,1,2,3",
25        "CounterHTOff": "0,1,2,3,4,5,6,7",
26        "EventCode": "0x85",
27        "EventName": "ITLB_MISSES.WALK_COMPLETED",
28        "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
29        "SampleAfterValue": "100003",
30        "UMask": "0xe"
31    },
32    {
33        "BriefDescription": "Load misses in all DTLB levels that cause page walks",
34        "Counter": "0,1,2,3",
35        "CounterHTOff": "0,1,2,3,4,5,6,7",
36        "EventCode": "0x08",
37        "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
38        "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
39        "SampleAfterValue": "100003",
40        "UMask": "0x1"
41    },
42    {
43        "BriefDescription": "STLB flush attempts",
44        "Counter": "0,1,2,3",
45        "CounterHTOff": "0,1,2,3,4,5,6,7",
46        "EventCode": "0xBD",
47        "EventName": "TLB_FLUSH.STLB_ANY",
48        "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
49        "SampleAfterValue": "100007",
50        "UMask": "0x20"
51    },
52    {
53        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
54        "Counter": "0,1,2,3",
55        "CounterHTOff": "0,1,2,3,4,5,6,7",
56        "CounterMask": "1",
57        "EventCode": "0x08",
58        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
59        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
60        "SampleAfterValue": "100003",
61        "UMask": "0x10"
62    },
63    {
64        "BriefDescription": "Page walk completed due to a demand data store to a 1G page",
65        "Counter": "0,1,2,3",
66        "CounterHTOff": "0,1,2,3,4,5,6,7",
67        "EventCode": "0x49",
68        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
69        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1G pages.  The page walks can end with or without a page fault.",
70        "SampleAfterValue": "100003",
71        "UMask": "0x8"
72    },
73    {
74        "BriefDescription": "Store misses in all DTLB levels that cause page walks",
75        "Counter": "0,1,2,3",
76        "CounterHTOff": "0,1,2,3,4,5,6,7",
77        "EventCode": "0x49",
78        "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
79        "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
80        "SampleAfterValue": "100003",
81        "UMask": "0x1"
82    },
83    {
84        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
85        "Counter": "0,1,2,3",
86        "CounterHTOff": "0,1,2,3,4,5,6,7",
87        "EventCode": "0xAE",
88        "EventName": "ITLB.ITLB_FLUSH",
89        "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
90        "SampleAfterValue": "100007",
91        "UMask": "0x1"
92    },
93    {
94        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
95        "Counter": "0,1,2,3",
96        "CounterHTOff": "0,1,2,3,4,5,6,7",
97        "EventCode": "0x49",
98        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
99        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
100        "SampleAfterValue": "2000003",
101        "UMask": "0x10"
102    },
103    {
104        "BriefDescription": "Page walk completed due to a demand data load to a 4K page",
105        "Counter": "0,1,2,3",
106        "CounterHTOff": "0,1,2,3,4,5,6,7",
107        "EventCode": "0x08",
108        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
109        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
110        "SampleAfterValue": "2000003",
111        "UMask": "0x2"
112    },
113    {
114        "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
115        "Counter": "0,1,2,3",
116        "CounterHTOff": "0,1,2,3,4,5,6,7",
117        "EventCode": "0x08",
118        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
119        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
120        "SampleAfterValue": "2000003",
121        "UMask": "0x4"
122    },
123    {
124        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
125        "Counter": "0,1,2,3",
126        "CounterHTOff": "0,1,2,3,4,5,6,7",
127        "EventCode": "0x08",
128        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
129        "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
130        "SampleAfterValue": "2000003",
131        "UMask": "0x10"
132    },
133    {
134        "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
135        "Counter": "0,1,2,3",
136        "CounterHTOff": "0,1,2,3,4,5,6,7",
137        "EventCode": "0x4F",
138        "EventName": "EPT.WALK_PENDING",
139        "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
140        "SampleAfterValue": "2000003",
141        "UMask": "0x10"
142    },
143    {
144        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
145        "Counter": "0,1,2,3",
146        "CounterHTOff": "0,1,2,3,4,5,6,7",
147        "CounterMask": "1",
148        "EventCode": "0x49",
149        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
150        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
151        "SampleAfterValue": "100003",
152        "UMask": "0x10"
153    },
154    {
155        "BriefDescription": "Misses at all ITLB levels that cause page walks",
156        "Counter": "0,1,2,3",
157        "CounterHTOff": "0,1,2,3,4,5,6,7",
158        "EventCode": "0x85",
159        "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
160        "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
161        "SampleAfterValue": "100003",
162        "UMask": "0x1"
163    },
164    {
165        "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
166        "Counter": "0,1,2,3",
167        "CounterHTOff": "0,1,2,3,4,5,6,7",
168        "EventCode": "0x49",
169        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
170        "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
171        "SampleAfterValue": "100003",
172        "UMask": "0x20"
173    },
174    {
175        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
176        "Counter": "0,1,2,3",
177        "CounterHTOff": "0,1,2,3,4,5,6,7",
178        "EventCode": "0x08",
179        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
180        "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
181        "SampleAfterValue": "100003",
182        "UMask": "0xe"
183    },
184    {
185        "BriefDescription": "Page walk completed due to a demand data store to a 4K page",
186        "Counter": "0,1,2,3",
187        "CounterHTOff": "0,1,2,3,4,5,6,7",
188        "EventCode": "0x49",
189        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
190        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
191        "SampleAfterValue": "100003",
192        "UMask": "0x2"
193    },
194    {
195        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
196        "Counter": "0,1,2,3",
197        "CounterHTOff": "0,1,2,3,4,5,6,7",
198        "EventCode": "0x85",
199        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
200        "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
201        "SampleAfterValue": "100003",
202        "UMask": "0x2"
203    },
204    {
205        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
206        "Counter": "0,1,2,3",
207        "CounterHTOff": "0,1,2,3,4,5,6,7",
208        "EventCode": "0x85",
209        "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
210        "PublicDescription": "Counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
211        "SampleAfterValue": "100003",
212        "UMask": "0x8"
213    },
214    {
215        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
216        "Counter": "0,1,2,3",
217        "CounterHTOff": "0,1,2,3,4,5,6,7",
218        "EventCode": "0x85",
219        "EventName": "ITLB_MISSES.STLB_HIT",
220        "SampleAfterValue": "100003",
221        "UMask": "0x20"
222    },
223    {
224        "BriefDescription": "Page walk completed due to a demand data load to a 1G page",
225        "Counter": "0,1,2,3",
226        "CounterHTOff": "0,1,2,3,4,5,6,7",
227        "EventCode": "0x08",
228        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
229        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
230        "SampleAfterValue": "2000003",
231        "UMask": "0x8"
232    },
233    {
234        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
235        "Counter": "0,1,2,3",
236        "CounterHTOff": "0,1,2,3,4,5,6,7",
237        "EventCode": "0x85",
238        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
239        "PublicDescription": "Counts code misses in all ITLB levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
240        "SampleAfterValue": "100003",
241        "UMask": "0x4"
242    },
243    {
244        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
245        "Counter": "0,1,2,3",
246        "CounterHTOff": "0,1,2,3,4,5,6,7",
247        "EventCode": "0x49",
248        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
249        "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
250        "SampleAfterValue": "100003",
251        "UMask": "0xe"
252    },
253    {
254        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
255        "Counter": "0,1,2,3",
256        "CounterHTOff": "0,1,2,3,4,5,6,7",
257        "CounterMask": "1",
258        "EventCode": "0x85",
259        "EventName": "ITLB_MISSES.WALK_ACTIVE",
260        "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.",
261        "SampleAfterValue": "100003",
262        "UMask": "0x10"
263    },
264    {
265        "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
266        "Counter": "0,1,2,3",
267        "CounterHTOff": "0,1,2,3,4,5,6,7",
268        "EventCode": "0x08",
269        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
270        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
271        "SampleAfterValue": "2000003",
272        "UMask": "0x20"
273    },
274    {
275        "BriefDescription": "DTLB flush attempts of the thread-specific entries",
276        "Counter": "0,1,2,3",
277        "CounterHTOff": "0,1,2,3,4,5,6,7",
278        "EventCode": "0xBD",
279        "EventName": "TLB_FLUSH.DTLB_THREAD",
280        "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
281        "SampleAfterValue": "100007",
282        "UMask": "0x1"
283    }
284]