1[
2    {
3        "CollectPEBSRecord": "2",
4        "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the Top-down Microarchitecture Analysis method. This event is counted on a designated fixed counter (Fixed Counter 3) and is an architectural event.",
5        "Counter": "35",
6        "UMask": "0x4",
7        "PEBScounters": "35",
8        "EventName": "TOPDOWN.SLOTS",
9        "SampleAfterValue": "10000003",
10        "BriefDescription": "Counts the number of available slots for an unhalted logical processor."
11    },
12    {
13        "CollectPEBSRecord": "2",
14        "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
15        "EventCode": "0x28",
16        "Counter": "0,1,2,3",
17        "UMask": "0x7",
18        "PEBScounters": "0,1,2,3",
19        "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
20        "SampleAfterValue": "200003",
21        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule."
22    },
23    {
24        "CollectPEBSRecord": "2",
25        "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
26        "EventCode": "0x28",
27        "Counter": "0,1,2,3",
28        "UMask": "0x18",
29        "PEBScounters": "0,1,2,3",
30        "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
31        "SampleAfterValue": "200003",
32        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule."
33    },
34    {
35        "CollectPEBSRecord": "2",
36        "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
37        "EventCode": "0x28",
38        "Counter": "0,1,2,3",
39        "UMask": "0x20",
40        "PEBScounters": "0,1,2,3",
41        "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
42        "SampleAfterValue": "200003",
43        "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule."
44    },
45    {
46        "CollectPEBSRecord": "2",
47        "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
48        "EventCode": "0x32",
49        "Counter": "0,1,2,3",
50        "UMask": "0x1",
51        "PEBScounters": "0,1,2,3",
52        "EventName": "SW_PREFETCH_ACCESS.NTA",
53        "SampleAfterValue": "2000003",
54        "BriefDescription": "Number of PREFETCHNTA instructions executed."
55    },
56    {
57        "CollectPEBSRecord": "2",
58        "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
59        "EventCode": "0x32",
60        "Counter": "0,1,2,3",
61        "UMask": "0x2",
62        "PEBScounters": "0,1,2,3",
63        "EventName": "SW_PREFETCH_ACCESS.T0",
64        "SampleAfterValue": "2000003",
65        "BriefDescription": "Number of PREFETCHT0 instructions executed."
66    },
67    {
68        "CollectPEBSRecord": "2",
69        "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
70        "EventCode": "0x32",
71        "Counter": "0,1,2,3",
72        "UMask": "0x4",
73        "PEBScounters": "0,1,2,3",
74        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
75        "SampleAfterValue": "2000003",
76        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed."
77    },
78    {
79        "CollectPEBSRecord": "2",
80        "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
81        "EventCode": "0x32",
82        "Counter": "0,1,2,3",
83        "UMask": "0x8",
84        "PEBScounters": "0,1,2,3",
85        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
86        "SampleAfterValue": "2000003",
87        "BriefDescription": "Number of PREFETCHW instructions executed."
88    },
89    {
90        "CollectPEBSRecord": "2",
91        "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
92        "EventCode": "0xa4",
93        "Counter": "0,1,2,3,4,5,6,7",
94        "UMask": "0x1",
95        "PEBScounters": "0,1,2,3,4,5,6,7",
96        "EventName": "TOPDOWN.SLOTS_P",
97        "SampleAfterValue": "10000003",
98        "BriefDescription": "Counts the number of available slots for an unhalted logical processor."
99    },
100    {
101        "CollectPEBSRecord": "2",
102        "EventCode": "0xA4",
103        "Counter": "0,1,2,3,4,5,6,7",
104        "UMask": "0x2",
105        "PEBScounters": "0,1,2,3,4,5,6,7",
106        "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
107        "SampleAfterValue": "10000003",
108        "BriefDescription": "Issue slots where no uops were being issued due to lack of back end resources."
109    },
110    {
111        "CollectPEBSRecord": "2",
112        "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
113        "EventCode": "0xc1",
114        "Counter": "0,1,2,3,4,5,6,7",
115        "UMask": "0x7",
116        "PEBScounters": "0,1,2,3,4,5,6,7",
117        "EventName": "ASSISTS.ANY",
118        "SampleAfterValue": "100003",
119        "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware."
120    }
121]