1[
2    {
3        "CollectPEBSRecord": "2",
4        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
5        "EventCode": "0x08",
6        "Counter": "0,1,2,3",
7        "UMask": "0x2",
8        "PEBScounters": "0,1,2,3",
9        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
10        "SampleAfterValue": "2000003",
11        "BriefDescription": "Page walks completed due to a demand data load to a 4K page."
12    },
13    {
14        "CollectPEBSRecord": "2",
15        "PublicDescription": "Counts page walks completed due to demand data loads whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
16        "EventCode": "0x08",
17        "Counter": "0,1,2,3",
18        "UMask": "0x4",
19        "PEBScounters": "0,1,2,3",
20        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
21        "SampleAfterValue": "2000003",
22        "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page."
23    },
24    {
25        "CollectPEBSRecord": "2",
26        "PublicDescription": "Counts demand data loads that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
27        "EventCode": "0x08",
28        "Counter": "0,1,2,3",
29        "UMask": "0xe",
30        "PEBScounters": "0,1,2,3",
31        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
32        "SampleAfterValue": "100003",
33        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)"
34    },
35    {
36        "CollectPEBSRecord": "2",
37        "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
38        "EventCode": "0x08",
39        "Counter": "0,1,2,3",
40        "UMask": "0x10",
41        "PEBScounters": "0,1,2,3",
42        "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
43        "SampleAfterValue": "2000003",
44        "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle."
45    },
46    {
47        "CollectPEBSRecord": "2",
48        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
49        "EventCode": "0x08",
50        "Counter": "0,1,2,3",
51        "UMask": "0x10",
52        "PEBScounters": "0,1,2,3",
53        "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
54        "SampleAfterValue": "100003",
55        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
56        "CounterMask": "1"
57    },
58    {
59        "CollectPEBSRecord": "2",
60        "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
61        "EventCode": "0x08",
62        "Counter": "0,1,2,3",
63        "UMask": "0x20",
64        "PEBScounters": "0,1,2,3",
65        "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
66        "SampleAfterValue": "2000003",
67        "BriefDescription": "Loads that miss the DTLB and hit the STLB."
68    },
69    {
70        "CollectPEBSRecord": "2",
71        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages.  The page walks can end with or without a page fault.",
72        "EventCode": "0x49",
73        "Counter": "0,1,2,3",
74        "UMask": "0x2",
75        "PEBScounters": "0,1,2,3",
76        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
77        "SampleAfterValue": "100003",
78        "BriefDescription": "Page walks completed due to a demand data store to a 4K page."
79    },
80    {
81        "CollectPEBSRecord": "2",
82        "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages.  The page walks can end with or without a page fault.",
83        "EventCode": "0x49",
84        "Counter": "0,1,2,3",
85        "UMask": "0x4",
86        "PEBScounters": "0,1,2,3",
87        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
88        "SampleAfterValue": "100003",
89        "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page."
90    },
91    {
92        "CollectPEBSRecord": "2",
93        "PublicDescription": "Counts demand data stores that caused a completed page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels. The page walk can end with or without a fault.",
94        "EventCode": "0x49",
95        "Counter": "0,1,2,3",
96        "UMask": "0xe",
97        "PEBScounters": "0,1,2,3",
98        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
99        "SampleAfterValue": "100003",
100        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)"
101    },
102    {
103        "CollectPEBSRecord": "2",
104        "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
105        "EventCode": "0x49",
106        "Counter": "0,1,2,3",
107        "UMask": "0x10",
108        "PEBScounters": "0,1,2,3",
109        "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
110        "SampleAfterValue": "2000003",
111        "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle."
112    },
113    {
114        "CollectPEBSRecord": "2",
115        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
116        "EventCode": "0x49",
117        "Counter": "0,1,2,3",
118        "UMask": "0x10",
119        "PEBScounters": "0,1,2,3",
120        "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
121        "SampleAfterValue": "100003",
122        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
123        "CounterMask": "1"
124    },
125    {
126        "CollectPEBSRecord": "2",
127        "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
128        "EventCode": "0x49",
129        "Counter": "0,1,2,3",
130        "UMask": "0x20",
131        "PEBScounters": "0,1,2,3",
132        "EventName": "DTLB_STORE_MISSES.STLB_HIT",
133        "SampleAfterValue": "100003",
134        "BriefDescription": "Stores that miss the DTLB and hit the STLB."
135    },
136    {
137        "CollectPEBSRecord": "2",
138        "PublicDescription": "Counts completed page walks (4K page size) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB. The page walk can end with or without a fault.",
139        "EventCode": "0x85",
140        "Counter": "0,1,2,3",
141        "UMask": "0x2",
142        "PEBScounters": "0,1,2,3",
143        "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
144        "SampleAfterValue": "100003",
145        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)"
146    },
147    {
148        "CollectPEBSRecord": "2",
149        "PublicDescription": "Counts code misses in all ITLB (Instruction TLB) levels that caused a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
150        "EventCode": "0x85",
151        "Counter": "0,1,2,3",
152        "UMask": "0x4",
153        "PEBScounters": "0,1,2,3",
154        "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
155        "SampleAfterValue": "100003",
156        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)"
157    },
158    {
159        "CollectPEBSRecord": "2",
160        "PublicDescription": "Counts completed page walks (2M and 4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
161        "EventCode": "0x85",
162        "Counter": "0,1,2,3",
163        "UMask": "0xe",
164        "PEBScounters": "0,1,2,3",
165        "EventName": "ITLB_MISSES.WALK_COMPLETED",
166        "SampleAfterValue": "100003",
167        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)"
168    },
169    {
170        "CollectPEBSRecord": "2",
171        "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
172        "EventCode": "0x85",
173        "Counter": "0,1,2,3",
174        "UMask": "0x10",
175        "PEBScounters": "0,1,2,3",
176        "EventName": "ITLB_MISSES.WALK_PENDING",
177        "SampleAfterValue": "100003",
178        "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle."
179    },
180    {
181        "CollectPEBSRecord": "2",
182        "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
183        "EventCode": "0x85",
184        "Counter": "0,1,2,3",
185        "UMask": "0x10",
186        "PEBScounters": "0,1,2,3",
187        "EventName": "ITLB_MISSES.WALK_ACTIVE",
188        "SampleAfterValue": "100003",
189        "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
190        "CounterMask": "1"
191    },
192    {
193        "CollectPEBSRecord": "2",
194        "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
195        "EventCode": "0x85",
196        "Counter": "0,1,2,3",
197        "UMask": "0x20",
198        "PEBScounters": "0,1,2,3",
199        "EventName": "ITLB_MISSES.STLB_HIT",
200        "SampleAfterValue": "100003",
201        "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB."
202    },
203    {
204        "CollectPEBSRecord": "2",
205        "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
206        "EventCode": "0xAE",
207        "Counter": "0,1,2,3",
208        "UMask": "0x1",
209        "PEBScounters": "0,1,2,3",
210        "EventName": "ITLB.ITLB_FLUSH",
211        "SampleAfterValue": "100007",
212        "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages."
213    },
214    {
215        "CollectPEBSRecord": "2",
216        "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
217        "EventCode": "0xBD",
218        "Counter": "0,1,2,3",
219        "UMask": "0x1",
220        "PEBScounters": "0,1,2,3",
221        "EventName": "TLB_FLUSH.DTLB_THREAD",
222        "SampleAfterValue": "100007",
223        "BriefDescription": "DTLB flush attempts of the thread-specific entries"
224    },
225    {
226        "CollectPEBSRecord": "2",
227        "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
228        "EventCode": "0xBD",
229        "Counter": "0,1,2,3",
230        "UMask": "0x20",
231        "PEBScounters": "0,1,2,3",
232        "EventName": "TLB_FLUSH.STLB_ANY",
233        "SampleAfterValue": "100007",
234        "BriefDescription": "STLB flush attempts"
235    }
236]