1[
2    {
3        "BriefDescription": "L1D data line replacements",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "EventCode": "0x51",
7        "EventName": "L1D.REPLACEMENT",
8        "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
9        "SampleAfterValue": "2000003",
10        "UMask": "0x1"
11    },
12    {
13        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
14        "Counter": "0,1,2,3",
15        "CounterHTOff": "0,1,2,3,4,5,6,7",
16        "CounterMask": "1",
17        "EventCode": "0x48",
18        "EventName": "L1D_PEND_MISS.FB_FULL",
19        "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
20        "SampleAfterValue": "2000003",
21        "UMask": "0x2"
22    },
23    {
24        "BriefDescription": "L1D miss oustandings duration in cycles",
25        "Counter": "2",
26        "CounterHTOff": "2",
27        "EventCode": "0x48",
28        "EventName": "L1D_PEND_MISS.PENDING",
29        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
30        "SampleAfterValue": "2000003",
31        "UMask": "0x1"
32    },
33    {
34        "BriefDescription": "Cycles with L1D load Misses outstanding.",
35        "Counter": "2",
36        "CounterHTOff": "2",
37        "CounterMask": "1",
38        "EventCode": "0x48",
39        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
40        "SampleAfterValue": "2000003",
41        "UMask": "0x1"
42    },
43    {
44        "AnyThread": "1",
45        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
46        "Counter": "2",
47        "CounterHTOff": "2",
48        "CounterMask": "1",
49        "EventCode": "0x48",
50        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
51        "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
52        "SampleAfterValue": "2000003",
53        "UMask": "0x1"
54    },
55    {
56        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
57        "Counter": "0,1,2,3",
58        "CounterHTOff": "0,1,2,3,4,5,6,7",
59        "EventCode": "0x28",
60        "EventName": "L2_L1D_WB_RQSTS.ALL",
61        "SampleAfterValue": "200003",
62        "UMask": "0xf"
63    },
64    {
65        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
66        "Counter": "0,1,2,3",
67        "CounterHTOff": "0,1,2,3,4,5,6,7",
68        "EventCode": "0x28",
69        "EventName": "L2_L1D_WB_RQSTS.HIT_E",
70        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
71        "SampleAfterValue": "200003",
72        "UMask": "0x4"
73    },
74    {
75        "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
76        "Counter": "0,1,2,3",
77        "CounterHTOff": "0,1,2,3,4,5,6,7",
78        "EventCode": "0x28",
79        "EventName": "L2_L1D_WB_RQSTS.HIT_M",
80        "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
81        "SampleAfterValue": "200003",
82        "UMask": "0x8"
83    },
84    {
85        "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
86        "Counter": "0,1,2,3",
87        "CounterHTOff": "0,1,2,3,4,5,6,7",
88        "EventCode": "0x28",
89        "EventName": "L2_L1D_WB_RQSTS.MISS",
90        "PublicDescription": "Not rejected writebacks that missed LLC.",
91        "SampleAfterValue": "200003",
92        "UMask": "0x1"
93    },
94    {
95        "BriefDescription": "L2 cache lines filling L2",
96        "Counter": "0,1,2,3",
97        "CounterHTOff": "0,1,2,3,4,5,6,7",
98        "EventCode": "0xF1",
99        "EventName": "L2_LINES_IN.ALL",
100        "PublicDescription": "L2 cache lines filling L2.",
101        "SampleAfterValue": "100003",
102        "UMask": "0x7"
103    },
104    {
105        "BriefDescription": "L2 cache lines in E state filling L2",
106        "Counter": "0,1,2,3",
107        "CounterHTOff": "0,1,2,3,4,5,6,7",
108        "EventCode": "0xF1",
109        "EventName": "L2_LINES_IN.E",
110        "PublicDescription": "L2 cache lines in E state filling L2.",
111        "SampleAfterValue": "100003",
112        "UMask": "0x4"
113    },
114    {
115        "BriefDescription": "L2 cache lines in I state filling L2",
116        "Counter": "0,1,2,3",
117        "CounterHTOff": "0,1,2,3,4,5,6,7",
118        "EventCode": "0xF1",
119        "EventName": "L2_LINES_IN.I",
120        "PublicDescription": "L2 cache lines in I state filling L2.",
121        "SampleAfterValue": "100003",
122        "UMask": "0x1"
123    },
124    {
125        "BriefDescription": "L2 cache lines in S state filling L2",
126        "Counter": "0,1,2,3",
127        "CounterHTOff": "0,1,2,3,4,5,6,7",
128        "EventCode": "0xF1",
129        "EventName": "L2_LINES_IN.S",
130        "PublicDescription": "L2 cache lines in S state filling L2.",
131        "SampleAfterValue": "100003",
132        "UMask": "0x2"
133    },
134    {
135        "BriefDescription": "Clean L2 cache lines evicted by demand",
136        "Counter": "0,1,2,3",
137        "CounterHTOff": "0,1,2,3,4,5,6,7",
138        "EventCode": "0xF2",
139        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
140        "PublicDescription": "Clean L2 cache lines evicted by demand.",
141        "SampleAfterValue": "100003",
142        "UMask": "0x1"
143    },
144    {
145        "BriefDescription": "Dirty L2 cache lines evicted by demand",
146        "Counter": "0,1,2,3",
147        "CounterHTOff": "0,1,2,3,4,5,6,7",
148        "EventCode": "0xF2",
149        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
150        "PublicDescription": "Dirty L2 cache lines evicted by demand.",
151        "SampleAfterValue": "100003",
152        "UMask": "0x2"
153    },
154    {
155        "BriefDescription": "Dirty L2 cache lines filling the L2",
156        "Counter": "0,1,2,3",
157        "CounterHTOff": "0,1,2,3,4,5,6,7",
158        "EventCode": "0xF2",
159        "EventName": "L2_LINES_OUT.DIRTY_ALL",
160        "PublicDescription": "Dirty L2 cache lines filling the L2.",
161        "SampleAfterValue": "100003",
162        "UMask": "0xa"
163    },
164    {
165        "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
166        "Counter": "0,1,2,3",
167        "CounterHTOff": "0,1,2,3,4,5,6,7",
168        "EventCode": "0xF2",
169        "EventName": "L2_LINES_OUT.PF_CLEAN",
170        "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
171        "SampleAfterValue": "100003",
172        "UMask": "0x4"
173    },
174    {
175        "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
176        "Counter": "0,1,2,3",
177        "CounterHTOff": "0,1,2,3,4,5,6,7",
178        "EventCode": "0xF2",
179        "EventName": "L2_LINES_OUT.PF_DIRTY",
180        "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
181        "SampleAfterValue": "100003",
182        "UMask": "0x8"
183    },
184    {
185        "BriefDescription": "L2 code requests",
186        "Counter": "0,1,2,3",
187        "CounterHTOff": "0,1,2,3,4,5,6,7",
188        "EventCode": "0x24",
189        "EventName": "L2_RQSTS.ALL_CODE_RD",
190        "PublicDescription": "Counts all L2 code requests.",
191        "SampleAfterValue": "200003",
192        "UMask": "0x30"
193    },
194    {
195        "BriefDescription": "Demand Data Read requests",
196        "Counter": "0,1,2,3",
197        "CounterHTOff": "0,1,2,3,4,5,6,7",
198        "EventCode": "0x24",
199        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
200        "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
201        "SampleAfterValue": "200003",
202        "UMask": "0x3"
203    },
204    {
205        "BriefDescription": "Requests from L2 hardware prefetchers",
206        "Counter": "0,1,2,3",
207        "CounterHTOff": "0,1,2,3,4,5,6,7",
208        "EventCode": "0x24",
209        "EventName": "L2_RQSTS.ALL_PF",
210        "PublicDescription": "Counts all L2 HW prefetcher requests.",
211        "SampleAfterValue": "200003",
212        "UMask": "0xc0"
213    },
214    {
215        "BriefDescription": "RFO requests to L2 cache",
216        "Counter": "0,1,2,3",
217        "CounterHTOff": "0,1,2,3,4,5,6,7",
218        "EventCode": "0x24",
219        "EventName": "L2_RQSTS.ALL_RFO",
220        "PublicDescription": "Counts all L2 store RFO requests.",
221        "SampleAfterValue": "200003",
222        "UMask": "0xc"
223    },
224    {
225        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
226        "Counter": "0,1,2,3",
227        "CounterHTOff": "0,1,2,3,4,5,6,7",
228        "EventCode": "0x24",
229        "EventName": "L2_RQSTS.CODE_RD_HIT",
230        "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
231        "SampleAfterValue": "200003",
232        "UMask": "0x10"
233    },
234    {
235        "BriefDescription": "L2 cache misses when fetching instructions",
236        "Counter": "0,1,2,3",
237        "CounterHTOff": "0,1,2,3,4,5,6,7",
238        "EventCode": "0x24",
239        "EventName": "L2_RQSTS.CODE_RD_MISS",
240        "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
241        "SampleAfterValue": "200003",
242        "UMask": "0x20"
243    },
244    {
245        "BriefDescription": "Demand Data Read requests that hit L2 cache",
246        "Counter": "0,1,2,3",
247        "CounterHTOff": "0,1,2,3,4,5,6,7",
248        "EventCode": "0x24",
249        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
250        "PublicDescription": "Demand Data Read requests that hit L2 cache.",
251        "SampleAfterValue": "200003",
252        "UMask": "0x1"
253    },
254    {
255        "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
256        "Counter": "0,1,2,3",
257        "CounterHTOff": "0,1,2,3,4,5,6,7",
258        "EventCode": "0x24",
259        "EventName": "L2_RQSTS.PF_HIT",
260        "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
261        "SampleAfterValue": "200003",
262        "UMask": "0x40"
263    },
264    {
265        "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
266        "Counter": "0,1,2,3",
267        "CounterHTOff": "0,1,2,3,4,5,6,7",
268        "EventCode": "0x24",
269        "EventName": "L2_RQSTS.PF_MISS",
270        "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
271        "SampleAfterValue": "200003",
272        "UMask": "0x80"
273    },
274    {
275        "BriefDescription": "RFO requests that hit L2 cache",
276        "Counter": "0,1,2,3",
277        "CounterHTOff": "0,1,2,3,4,5,6,7",
278        "EventCode": "0x24",
279        "EventName": "L2_RQSTS.RFO_HIT",
280        "PublicDescription": "RFO requests that hit L2 cache.",
281        "SampleAfterValue": "200003",
282        "UMask": "0x4"
283    },
284    {
285        "BriefDescription": "RFO requests that miss L2 cache",
286        "Counter": "0,1,2,3",
287        "CounterHTOff": "0,1,2,3,4,5,6,7",
288        "EventCode": "0x24",
289        "EventName": "L2_RQSTS.RFO_MISS",
290        "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
291        "SampleAfterValue": "200003",
292        "UMask": "0x8"
293    },
294    {
295        "BriefDescription": "RFOs that access cache lines in any state",
296        "Counter": "0,1,2,3",
297        "CounterHTOff": "0,1,2,3,4,5,6,7",
298        "EventCode": "0x27",
299        "EventName": "L2_STORE_LOCK_RQSTS.ALL",
300        "PublicDescription": "RFOs that access cache lines in any state.",
301        "SampleAfterValue": "200003",
302        "UMask": "0xf"
303    },
304    {
305        "BriefDescription": "RFOs that hit cache lines in M state",
306        "Counter": "0,1,2,3",
307        "CounterHTOff": "0,1,2,3,4,5,6,7",
308        "EventCode": "0x27",
309        "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
310        "PublicDescription": "RFOs that hit cache lines in M state.",
311        "SampleAfterValue": "200003",
312        "UMask": "0x8"
313    },
314    {
315        "BriefDescription": "RFOs that miss cache lines",
316        "Counter": "0,1,2,3",
317        "CounterHTOff": "0,1,2,3,4,5,6,7",
318        "EventCode": "0x27",
319        "EventName": "L2_STORE_LOCK_RQSTS.MISS",
320        "PublicDescription": "RFOs that miss cache lines.",
321        "SampleAfterValue": "200003",
322        "UMask": "0x1"
323    },
324    {
325        "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
326        "Counter": "0,1,2,3",
327        "CounterHTOff": "0,1,2,3,4,5,6,7",
328        "EventCode": "0xF0",
329        "EventName": "L2_TRANS.ALL_PF",
330        "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
331        "SampleAfterValue": "200003",
332        "UMask": "0x8"
333    },
334    {
335        "BriefDescription": "Transactions accessing L2 pipe",
336        "Counter": "0,1,2,3",
337        "CounterHTOff": "0,1,2,3,4,5,6,7",
338        "EventCode": "0xF0",
339        "EventName": "L2_TRANS.ALL_REQUESTS",
340        "PublicDescription": "Transactions accessing L2 pipe.",
341        "SampleAfterValue": "200003",
342        "UMask": "0x80"
343    },
344    {
345        "BriefDescription": "L2 cache accesses when fetching instructions",
346        "Counter": "0,1,2,3",
347        "CounterHTOff": "0,1,2,3,4,5,6,7",
348        "EventCode": "0xF0",
349        "EventName": "L2_TRANS.CODE_RD",
350        "PublicDescription": "L2 cache accesses when fetching instructions.",
351        "SampleAfterValue": "200003",
352        "UMask": "0x4"
353    },
354    {
355        "BriefDescription": "Demand Data Read requests that access L2 cache",
356        "Counter": "0,1,2,3",
357        "CounterHTOff": "0,1,2,3,4,5,6,7",
358        "EventCode": "0xF0",
359        "EventName": "L2_TRANS.DEMAND_DATA_RD",
360        "PublicDescription": "Demand Data Read requests that access L2 cache.",
361        "SampleAfterValue": "200003",
362        "UMask": "0x1"
363    },
364    {
365        "BriefDescription": "L1D writebacks that access L2 cache",
366        "Counter": "0,1,2,3",
367        "CounterHTOff": "0,1,2,3,4,5,6,7",
368        "EventCode": "0xF0",
369        "EventName": "L2_TRANS.L1D_WB",
370        "PublicDescription": "L1D writebacks that access L2 cache.",
371        "SampleAfterValue": "200003",
372        "UMask": "0x10"
373    },
374    {
375        "BriefDescription": "L2 fill requests that access L2 cache",
376        "Counter": "0,1,2,3",
377        "CounterHTOff": "0,1,2,3,4,5,6,7",
378        "EventCode": "0xF0",
379        "EventName": "L2_TRANS.L2_FILL",
380        "PublicDescription": "L2 fill requests that access L2 cache.",
381        "SampleAfterValue": "200003",
382        "UMask": "0x20"
383    },
384    {
385        "BriefDescription": "L2 writebacks that access L2 cache",
386        "Counter": "0,1,2,3",
387        "CounterHTOff": "0,1,2,3,4,5,6,7",
388        "EventCode": "0xF0",
389        "EventName": "L2_TRANS.L2_WB",
390        "PublicDescription": "L2 writebacks that access L2 cache.",
391        "SampleAfterValue": "200003",
392        "UMask": "0x40"
393    },
394    {
395        "BriefDescription": "RFO requests that access L2 cache",
396        "Counter": "0,1,2,3",
397        "CounterHTOff": "0,1,2,3,4,5,6,7",
398        "EventCode": "0xF0",
399        "EventName": "L2_TRANS.RFO",
400        "PublicDescription": "RFO requests that access L2 cache.",
401        "SampleAfterValue": "200003",
402        "UMask": "0x2"
403    },
404    {
405        "BriefDescription": "Cycles when L1D is locked",
406        "Counter": "0,1,2,3",
407        "CounterHTOff": "0,1,2,3,4,5,6,7",
408        "EventCode": "0x63",
409        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
410        "PublicDescription": "Cycles in which the L1D is locked.",
411        "SampleAfterValue": "2000003",
412        "UMask": "0x2"
413    },
414    {
415        "BriefDescription": "Core-originated cacheable demand requests missed LLC",
416        "Counter": "0,1,2,3",
417        "CounterHTOff": "0,1,2,3,4,5,6,7",
418        "EventCode": "0x2E",
419        "EventName": "LONGEST_LAT_CACHE.MISS",
420        "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
421        "SampleAfterValue": "100003",
422        "UMask": "0x41"
423    },
424    {
425        "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
426        "Counter": "0,1,2,3",
427        "CounterHTOff": "0,1,2,3,4,5,6,7",
428        "EventCode": "0x2E",
429        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
430        "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
431        "SampleAfterValue": "100003",
432        "UMask": "0x4f"
433    },
434    {
435        "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.",
436        "Counter": "0,1,2,3",
437        "CounterHTOff": "0,1,2,3",
438        "EventCode": "0xD2",
439        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
440        "PEBS": "1",
441        "SampleAfterValue": "20011",
442        "UMask": "0x2"
443    },
444    {
445        "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.",
446        "Counter": "0,1,2,3",
447        "CounterHTOff": "0,1,2,3",
448        "EventCode": "0xD2",
449        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
450        "PEBS": "1",
451        "SampleAfterValue": "20011",
452        "UMask": "0x4"
453    },
454    {
455        "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
456        "Counter": "0,1,2,3",
457        "CounterHTOff": "0,1,2,3",
458        "EventCode": "0xD2",
459        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
460        "PEBS": "1",
461        "SampleAfterValue": "20011",
462        "UMask": "0x1"
463    },
464    {
465        "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.",
466        "Counter": "0,1,2,3",
467        "CounterHTOff": "0,1,2,3",
468        "EventCode": "0xD2",
469        "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
470        "PEBS": "1",
471        "SampleAfterValue": "100003",
472        "UMask": "0x8"
473    },
474    {
475        "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
476        "Counter": "0,1,2,3",
477        "CounterHTOff": "0,1,2,3",
478        "EventCode": "0xD3",
479        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
480        "SampleAfterValue": "100007",
481        "UMask": "0x3"
482    },
483    {
484        "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
485        "Counter": "0,1,2,3",
486        "CounterHTOff": "0,1,2,3",
487        "EventCode": "0xD3",
488        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
489        "SampleAfterValue": "100007",
490        "UMask": "0xc"
491    },
492    {
493        "BriefDescription": "Data forwarded from remote cache.",
494        "Counter": "0,1,2,3",
495        "CounterHTOff": "0,1,2,3",
496        "EventCode": "0xD3",
497        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD",
498        "SampleAfterValue": "100007",
499        "UMask": "0x20"
500    },
501    {
502        "BriefDescription": "Remote cache HITM.",
503        "Counter": "0,1,2,3",
504        "CounterHTOff": "0,1,2,3",
505        "EventCode": "0xD3",
506        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM",
507        "SampleAfterValue": "100007",
508        "UMask": "0x10"
509    },
510    {
511        "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
512        "Counter": "0,1,2,3",
513        "CounterHTOff": "0,1,2,3",
514        "EventCode": "0xD1",
515        "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
516        "PEBS": "1",
517        "SampleAfterValue": "100003",
518        "UMask": "0x40"
519    },
520    {
521        "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
522        "Counter": "0,1,2,3",
523        "CounterHTOff": "0,1,2,3",
524        "EventCode": "0xD1",
525        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
526        "PEBS": "1",
527        "SampleAfterValue": "2000003",
528        "UMask": "0x1"
529    },
530    {
531        "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.",
532        "Counter": "0,1,2,3",
533        "CounterHTOff": "0,1,2,3",
534        "EventCode": "0xD1",
535        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
536        "PEBS": "1",
537        "SampleAfterValue": "100003",
538        "UMask": "0x8"
539    },
540    {
541        "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
542        "Counter": "0,1,2,3",
543        "CounterHTOff": "0,1,2,3",
544        "EventCode": "0xD1",
545        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
546        "PEBS": "1",
547        "SampleAfterValue": "100003",
548        "UMask": "0x2"
549    },
550    {
551        "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
552        "Counter": "0,1,2,3",
553        "CounterHTOff": "0,1,2,3",
554        "EventCode": "0xD1",
555        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
556        "PEBS": "1",
557        "SampleAfterValue": "50021",
558        "UMask": "0x10"
559    },
560    {
561        "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.",
562        "Counter": "0,1,2,3",
563        "CounterHTOff": "0,1,2,3",
564        "EventCode": "0xD1",
565        "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
566        "PEBS": "1",
567        "SampleAfterValue": "50021",
568        "UMask": "0x4"
569    },
570    {
571        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
572        "Counter": "0,1,2,3",
573        "CounterHTOff": "0,1,2,3",
574        "EventCode": "0xD1",
575        "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
576        "PEBS": "1",
577        "SampleAfterValue": "100007",
578        "UMask": "0x20"
579    },
580    {
581        "BriefDescription": "All retired load uops. (Precise Event)",
582        "Counter": "0,1,2,3",
583        "CounterHTOff": "0,1,2,3",
584        "EventCode": "0xD0",
585        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
586        "PEBS": "1",
587        "SampleAfterValue": "2000003",
588        "UMask": "0x81"
589    },
590    {
591        "BriefDescription": "All retired store uops. (Precise Event)",
592        "Counter": "0,1,2,3",
593        "CounterHTOff": "0,1,2,3",
594        "EventCode": "0xD0",
595        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
596        "PEBS": "1",
597        "SampleAfterValue": "2000003",
598        "UMask": "0x82"
599    },
600    {
601        "BriefDescription": "Retired load uops with locked access. (Precise Event)",
602        "Counter": "0,1,2,3",
603        "CounterHTOff": "0,1,2,3",
604        "EventCode": "0xD0",
605        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
606        "PEBS": "1",
607        "SampleAfterValue": "100007",
608        "UMask": "0x21"
609    },
610    {
611        "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)",
612        "Counter": "0,1,2,3",
613        "CounterHTOff": "0,1,2,3",
614        "EventCode": "0xD0",
615        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
616        "PEBS": "1",
617        "SampleAfterValue": "100003",
618        "UMask": "0x41"
619    },
620    {
621        "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)",
622        "Counter": "0,1,2,3",
623        "CounterHTOff": "0,1,2,3",
624        "EventCode": "0xD0",
625        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
626        "PEBS": "1",
627        "SampleAfterValue": "100003",
628        "UMask": "0x42"
629    },
630    {
631        "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)",
632        "Counter": "0,1,2,3",
633        "CounterHTOff": "0,1,2,3",
634        "EventCode": "0xD0",
635        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
636        "PEBS": "1",
637        "SampleAfterValue": "100003",
638        "UMask": "0x11"
639    },
640    {
641        "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)",
642        "Counter": "0,1,2,3",
643        "CounterHTOff": "0,1,2,3",
644        "EventCode": "0xD0",
645        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
646        "PEBS": "1",
647        "SampleAfterValue": "100003",
648        "UMask": "0x12"
649    },
650    {
651        "BriefDescription": "Demand and prefetch data reads",
652        "Counter": "0,1,2,3",
653        "CounterHTOff": "0,1,2,3,4,5,6,7",
654        "EventCode": "0xB0",
655        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
656        "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
657        "SampleAfterValue": "100003",
658        "UMask": "0x8"
659    },
660    {
661        "BriefDescription": "Cacheable and noncachaeble code read requests",
662        "Counter": "0,1,2,3",
663        "CounterHTOff": "0,1,2,3,4,5,6,7",
664        "EventCode": "0xB0",
665        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
666        "PublicDescription": "Demand code read requests sent to uncore.",
667        "SampleAfterValue": "100003",
668        "UMask": "0x2"
669    },
670    {
671        "BriefDescription": "Demand Data Read requests sent to uncore",
672        "Counter": "0,1,2,3",
673        "CounterHTOff": "0,1,2,3,4,5,6,7",
674        "EventCode": "0xB0",
675        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
676        "PublicDescription": "Demand data read requests sent to uncore.",
677        "SampleAfterValue": "100003",
678        "UMask": "0x1"
679    },
680    {
681        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
682        "Counter": "0,1,2,3",
683        "CounterHTOff": "0,1,2,3,4,5,6,7",
684        "EventCode": "0xB0",
685        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
686        "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
687        "SampleAfterValue": "100003",
688        "UMask": "0x4"
689    },
690    {
691        "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
692        "Counter": "0,1,2,3",
693        "CounterHTOff": "0,1,2,3,4,5,6,7",
694        "EventCode": "0xB2",
695        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
696        "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
697        "SampleAfterValue": "2000003",
698        "UMask": "0x1"
699    },
700    {
701        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
702        "Counter": "0,1,2,3",
703        "CounterHTOff": "0,1,2,3,4,5,6,7",
704        "EventCode": "0x60",
705        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
706        "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
707        "SampleAfterValue": "2000003",
708        "UMask": "0x8"
709    },
710    {
711        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
712        "Counter": "0,1,2,3",
713        "CounterHTOff": "0,1,2,3,4,5,6,7",
714        "CounterMask": "1",
715        "EventCode": "0x60",
716        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
717        "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
718        "SampleAfterValue": "2000003",
719        "UMask": "0x8"
720    },
721    {
722        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
723        "Counter": "0,1,2,3",
724        "CounterHTOff": "0,1,2,3,4,5,6,7",
725        "CounterMask": "1",
726        "EventCode": "0x60",
727        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
728        "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
729        "SampleAfterValue": "2000003",
730        "UMask": "0x2"
731    },
732    {
733        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
734        "Counter": "0,1,2,3",
735        "CounterHTOff": "0,1,2,3,4,5,6,7",
736        "CounterMask": "1",
737        "EventCode": "0x60",
738        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
739        "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
740        "SampleAfterValue": "2000003",
741        "UMask": "0x1"
742    },
743    {
744        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
745        "Counter": "0,1,2,3",
746        "CounterHTOff": "0,1,2,3,4,5,6,7",
747        "CounterMask": "1",
748        "EventCode": "0x60",
749        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
750        "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
751        "SampleAfterValue": "2000003",
752        "UMask": "0x4"
753    },
754    {
755        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
756        "Counter": "0,1,2,3",
757        "CounterHTOff": "0,1,2,3,4,5,6,7",
758        "EventCode": "0x60",
759        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
760        "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
761        "SampleAfterValue": "2000003",
762        "UMask": "0x2"
763    },
764    {
765        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
766        "Counter": "0,1,2,3",
767        "CounterHTOff": "0,1,2,3,4,5,6,7",
768        "EventCode": "0x60",
769        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
770        "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
771        "SampleAfterValue": "2000003",
772        "UMask": "0x1"
773    },
774    {
775        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
776        "Counter": "0,1,2,3",
777        "CounterHTOff": "0,1,2,3,4,5,6,7",
778        "CounterMask": "6",
779        "EventCode": "0x60",
780        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
781        "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
782        "SampleAfterValue": "2000003",
783        "UMask": "0x1"
784    },
785    {
786        "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
787        "Counter": "0,1,2,3",
788        "CounterHTOff": "0,1,2,3,4,5,6,7",
789        "EventCode": "0x60",
790        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
791        "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
792        "SampleAfterValue": "2000003",
793        "UMask": "0x4"
794    },
795    {
796        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
797        "Counter": "0,1,2,3",
798        "CounterHTOff": "0,1,2,3",
799        "EventCode": "0xB7, 0xBB",
800        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
801        "MSRIndex": "0x1a6,0x1a7",
802        "MSRValue": "0x10003c0091",
803        "Offcore": "1",
804        "SampleAfterValue": "100003",
805        "UMask": "0x1"
806    },
807    {
808        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
809        "Counter": "0,1,2,3",
810        "CounterHTOff": "0,1,2,3",
811        "EventCode": "0xB7, 0xBB",
812        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
813        "MSRIndex": "0x1a6,0x1a7",
814        "MSRValue": "0x4003c0091",
815        "Offcore": "1",
816        "SampleAfterValue": "100003",
817        "UMask": "0x1"
818    },
819    {
820        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
821        "Counter": "0,1,2,3",
822        "CounterHTOff": "0,1,2,3",
823        "EventCode": "0xB7, 0xBB",
824        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
825        "MSRIndex": "0x1a6,0x1a7",
826        "MSRValue": "0x1003c0091",
827        "Offcore": "1",
828        "SampleAfterValue": "100003",
829        "UMask": "0x1"
830    },
831    {
832        "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
833        "Counter": "0,1,2,3",
834        "CounterHTOff": "0,1,2,3",
835        "EventCode": "0xB7, 0xBB",
836        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
837        "MSRIndex": "0x1a6,0x1a7",
838        "MSRValue": "0x2003c0091",
839        "Offcore": "1",
840        "SampleAfterValue": "100003",
841        "UMask": "0x1"
842    },
843    {
844        "BriefDescription": "Counts all prefetch data reads that hit the LLC",
845        "Counter": "0,1,2,3",
846        "CounterHTOff": "0,1,2,3",
847        "EventCode": "0xB7, 0xBB",
848        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
849        "MSRIndex": "0x1a6,0x1a7",
850        "MSRValue": "0x3f803c0090",
851        "Offcore": "1",
852        "SampleAfterValue": "100003",
853        "UMask": "0x1"
854    },
855    {
856        "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
857        "Counter": "0,1,2,3",
858        "CounterHTOff": "0,1,2,3",
859        "EventCode": "0xB7, 0xBB",
860        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
861        "MSRIndex": "0x1a6,0x1a7",
862        "MSRValue": "0x10003c0090",
863        "Offcore": "1",
864        "SampleAfterValue": "100003",
865        "UMask": "0x1"
866    },
867    {
868        "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
869        "Counter": "0,1,2,3",
870        "CounterHTOff": "0,1,2,3",
871        "EventCode": "0xB7, 0xBB",
872        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
873        "MSRIndex": "0x1a6,0x1a7",
874        "MSRValue": "0x4003c0090",
875        "Offcore": "1",
876        "SampleAfterValue": "100003",
877        "UMask": "0x1"
878    },
879    {
880        "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
881        "Counter": "0,1,2,3",
882        "CounterHTOff": "0,1,2,3",
883        "EventCode": "0xB7, 0xBB",
884        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
885        "MSRIndex": "0x1a6,0x1a7",
886        "MSRValue": "0x1003c0090",
887        "Offcore": "1",
888        "SampleAfterValue": "100003",
889        "UMask": "0x1"
890    },
891    {
892        "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
893        "Counter": "0,1,2,3",
894        "CounterHTOff": "0,1,2,3",
895        "EventCode": "0xB7, 0xBB",
896        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
897        "MSRIndex": "0x1a6,0x1a7",
898        "MSRValue": "0x2003c0090",
899        "Offcore": "1",
900        "SampleAfterValue": "100003",
901        "UMask": "0x1"
902    },
903    {
904        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
905        "Counter": "0,1,2,3",
906        "CounterHTOff": "0,1,2,3",
907        "EventCode": "0xB7, 0xBB",
908        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
909        "MSRIndex": "0x1a6,0x1a7",
910        "MSRValue": "0x3f803c03f7",
911        "Offcore": "1",
912        "SampleAfterValue": "100003",
913        "UMask": "0x1"
914    },
915    {
916        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
917        "Counter": "0,1,2,3",
918        "CounterHTOff": "0,1,2,3",
919        "EventCode": "0xB7, 0xBB",
920        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
921        "MSRIndex": "0x1a6,0x1a7",
922        "MSRValue": "0x10003c03f7",
923        "Offcore": "1",
924        "SampleAfterValue": "100003",
925        "UMask": "0x1"
926    },
927    {
928        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
929        "Counter": "0,1,2,3",
930        "CounterHTOff": "0,1,2,3",
931        "EventCode": "0xB7, 0xBB",
932        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
933        "MSRIndex": "0x1a6,0x1a7",
934        "MSRValue": "0x4003c03f7",
935        "Offcore": "1",
936        "SampleAfterValue": "100003",
937        "UMask": "0x1"
938    },
939    {
940        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
941        "Counter": "0,1,2,3",
942        "CounterHTOff": "0,1,2,3",
943        "EventCode": "0xB7, 0xBB",
944        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
945        "MSRIndex": "0x1a6,0x1a7",
946        "MSRValue": "0x1003c03f7",
947        "Offcore": "1",
948        "SampleAfterValue": "100003",
949        "UMask": "0x1"
950    },
951    {
952        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
953        "Counter": "0,1,2,3",
954        "CounterHTOff": "0,1,2,3",
955        "EventCode": "0xB7, 0xBB",
956        "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
957        "MSRIndex": "0x1a6,0x1a7",
958        "MSRValue": "0x2003c03f7",
959        "Offcore": "1",
960        "SampleAfterValue": "100003",
961        "UMask": "0x1"
962    },
963    {
964        "BriefDescription": "Counts all writebacks from the core to the LLC",
965        "Counter": "0,1,2,3",
966        "CounterHTOff": "0,1,2,3",
967        "EventCode": "0xB7, 0xBB",
968        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
969        "MSRIndex": "0x1a6,0x1a7",
970        "MSRValue": "0x10008",
971        "Offcore": "1",
972        "SampleAfterValue": "100003",
973        "UMask": "0x1"
974    },
975    {
976        "BriefDescription": "Counts all demand code reads that hit in the LLC",
977        "Counter": "0,1,2,3",
978        "CounterHTOff": "0,1,2,3",
979        "EventCode": "0xB7, 0xBB",
980        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
981        "MSRIndex": "0x1a6,0x1a7",
982        "MSRValue": "0x3f803c0004",
983        "Offcore": "1",
984        "SampleAfterValue": "100003",
985        "UMask": "0x1"
986    },
987    {
988        "BriefDescription": "Counts all demand data reads that hit in the LLC",
989        "Counter": "0,1,2,3",
990        "CounterHTOff": "0,1,2,3",
991        "EventCode": "0xB7, 0xBB",
992        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
993        "MSRIndex": "0x1a6,0x1a7",
994        "MSRValue": "0x3f803c0001",
995        "Offcore": "1",
996        "SampleAfterValue": "100003",
997        "UMask": "0x1"
998    },
999    {
1000        "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1001        "Counter": "0,1,2,3",
1002        "CounterHTOff": "0,1,2,3",
1003        "EventCode": "0xB7, 0xBB",
1004        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1005        "MSRIndex": "0x1a6,0x1a7",
1006        "MSRValue": "0x10003c0001",
1007        "Offcore": "1",
1008        "SampleAfterValue": "100003",
1009        "UMask": "0x1"
1010    },
1011    {
1012        "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1013        "Counter": "0,1,2,3",
1014        "CounterHTOff": "0,1,2,3",
1015        "EventCode": "0xB7, 0xBB",
1016        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1017        "MSRIndex": "0x1a6,0x1a7",
1018        "MSRValue": "0x4003c0001",
1019        "Offcore": "1",
1020        "SampleAfterValue": "100003",
1021        "UMask": "0x1"
1022    },
1023    {
1024        "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1025        "Counter": "0,1,2,3",
1026        "CounterHTOff": "0,1,2,3",
1027        "EventCode": "0xB7, 0xBB",
1028        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1029        "MSRIndex": "0x1a6,0x1a7",
1030        "MSRValue": "0x1003c0001",
1031        "Offcore": "1",
1032        "SampleAfterValue": "100003",
1033        "UMask": "0x1"
1034    },
1035    {
1036        "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
1037        "Counter": "0,1,2,3",
1038        "CounterHTOff": "0,1,2,3",
1039        "EventCode": "0xB7, 0xBB",
1040        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
1041        "MSRIndex": "0x1a6,0x1a7",
1042        "MSRValue": "0x2003c0001",
1043        "Offcore": "1",
1044        "SampleAfterValue": "100003",
1045        "UMask": "0x1"
1046    },
1047    {
1048        "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1049        "Counter": "0,1,2,3",
1050        "CounterHTOff": "0,1,2,3",
1051        "EventCode": "0xB7, 0xBB",
1052        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
1053        "MSRIndex": "0x1a6,0x1a7",
1054        "MSRValue": "0x10003c0002",
1055        "Offcore": "1",
1056        "SampleAfterValue": "100003",
1057        "UMask": "0x1"
1058    },
1059    {
1060        "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
1061        "Counter": "0,1,2,3",
1062        "CounterHTOff": "0,1,2,3",
1063        "EventCode": "0xB7, 0xBB",
1064        "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
1065        "MSRIndex": "0x1a6,0x1a7",
1066        "MSRValue": "0x803c8000",
1067        "Offcore": "1",
1068        "SampleAfterValue": "100003",
1069        "UMask": "0x1"
1070    },
1071    {
1072        "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
1073        "Counter": "0,1,2,3",
1074        "CounterHTOff": "0,1,2,3",
1075        "EventCode": "0xB7, 0xBB",
1076        "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
1077        "MSRIndex": "0x1a6,0x1a7",
1078        "MSRValue": "0x23ffc08000",
1079        "Offcore": "1",
1080        "SampleAfterValue": "100003",
1081        "UMask": "0x1"
1082    },
1083    {
1084        "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
1085        "Counter": "0,1,2,3",
1086        "CounterHTOff": "0,1,2,3",
1087        "EventCode": "0xB7, 0xBB",
1088        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
1089        "MSRIndex": "0x1a6,0x1a7",
1090        "MSRValue": "0x3f803c0040",
1091        "Offcore": "1",
1092        "SampleAfterValue": "100003",
1093        "UMask": "0x1"
1094    },
1095    {
1096        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
1097        "Counter": "0,1,2,3",
1098        "CounterHTOff": "0,1,2,3",
1099        "EventCode": "0xB7, 0xBB",
1100        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
1101        "MSRIndex": "0x1a6,0x1a7",
1102        "MSRValue": "0x3f803c0010",
1103        "Offcore": "1",
1104        "SampleAfterValue": "100003",
1105        "UMask": "0x1"
1106    },
1107    {
1108        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1109        "Counter": "0,1,2,3",
1110        "CounterHTOff": "0,1,2,3",
1111        "EventCode": "0xB7, 0xBB",
1112        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1113        "MSRIndex": "0x1a6,0x1a7",
1114        "MSRValue": "0x10003c0010",
1115        "Offcore": "1",
1116        "SampleAfterValue": "100003",
1117        "UMask": "0x1"
1118    },
1119    {
1120        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1121        "Counter": "0,1,2,3",
1122        "CounterHTOff": "0,1,2,3",
1123        "EventCode": "0xB7, 0xBB",
1124        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1125        "MSRIndex": "0x1a6,0x1a7",
1126        "MSRValue": "0x4003c0010",
1127        "Offcore": "1",
1128        "SampleAfterValue": "100003",
1129        "UMask": "0x1"
1130    },
1131    {
1132        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1133        "Counter": "0,1,2,3",
1134        "CounterHTOff": "0,1,2,3",
1135        "EventCode": "0xB7, 0xBB",
1136        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1137        "MSRIndex": "0x1a6,0x1a7",
1138        "MSRValue": "0x1003c0010",
1139        "Offcore": "1",
1140        "SampleAfterValue": "100003",
1141        "UMask": "0x1"
1142    },
1143    {
1144        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1145        "Counter": "0,1,2,3",
1146        "CounterHTOff": "0,1,2,3",
1147        "EventCode": "0xB7, 0xBB",
1148        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
1149        "MSRIndex": "0x1a6,0x1a7",
1150        "MSRValue": "0x2003c0010",
1151        "Offcore": "1",
1152        "SampleAfterValue": "100003",
1153        "UMask": "0x1"
1154    },
1155    {
1156        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
1157        "Counter": "0,1,2,3",
1158        "CounterHTOff": "0,1,2,3",
1159        "EventCode": "0xB7, 0xBB",
1160        "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
1161        "MSRIndex": "0x1a6,0x1a7",
1162        "MSRValue": "0x3f803c0200",
1163        "Offcore": "1",
1164        "SampleAfterValue": "100003",
1165        "UMask": "0x1"
1166    },
1167    {
1168        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
1169        "Counter": "0,1,2,3",
1170        "CounterHTOff": "0,1,2,3",
1171        "EventCode": "0xB7, 0xBB",
1172        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
1173        "MSRIndex": "0x1a6,0x1a7",
1174        "MSRValue": "0x3f803c0080",
1175        "Offcore": "1",
1176        "SampleAfterValue": "100003",
1177        "UMask": "0x1"
1178    },
1179    {
1180        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1181        "Counter": "0,1,2,3",
1182        "CounterHTOff": "0,1,2,3",
1183        "EventCode": "0xB7, 0xBB",
1184        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1185        "MSRIndex": "0x1a6,0x1a7",
1186        "MSRValue": "0x10003c0080",
1187        "Offcore": "1",
1188        "SampleAfterValue": "100003",
1189        "UMask": "0x1"
1190    },
1191    {
1192        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1193        "Counter": "0,1,2,3",
1194        "CounterHTOff": "0,1,2,3",
1195        "EventCode": "0xB7, 0xBB",
1196        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1197        "MSRIndex": "0x1a6,0x1a7",
1198        "MSRValue": "0x4003c0080",
1199        "Offcore": "1",
1200        "SampleAfterValue": "100003",
1201        "UMask": "0x1"
1202    },
1203    {
1204        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1205        "Counter": "0,1,2,3",
1206        "CounterHTOff": "0,1,2,3",
1207        "EventCode": "0xB7, 0xBB",
1208        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1209        "MSRIndex": "0x1a6,0x1a7",
1210        "MSRValue": "0x1003c0080",
1211        "Offcore": "1",
1212        "SampleAfterValue": "100003",
1213        "UMask": "0x1"
1214    },
1215    {
1216        "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1217        "Counter": "0,1,2,3",
1218        "CounterHTOff": "0,1,2,3",
1219        "EventCode": "0xB7, 0xBB",
1220        "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
1221        "MSRIndex": "0x1a6,0x1a7",
1222        "MSRValue": "0x2003c0080",
1223        "Offcore": "1",
1224        "SampleAfterValue": "100003",
1225        "UMask": "0x1"
1226    },
1227    {
1228        "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
1229        "Counter": "0,1,2,3",
1230        "CounterHTOff": "0,1,2,3",
1231        "EventCode": "0xB7, 0xBB",
1232        "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
1233        "MSRIndex": "0x1a6,0x1a7",
1234        "MSRValue": "0x10400",
1235        "Offcore": "1",
1236        "SampleAfterValue": "100003",
1237        "UMask": "0x1"
1238    },
1239    {
1240        "BriefDescription": "Counts non-temporal stores",
1241        "Counter": "0,1,2,3",
1242        "CounterHTOff": "0,1,2,3",
1243        "EventCode": "0xB7, 0xBB",
1244        "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
1245        "MSRIndex": "0x1a6,0x1a7",
1246        "MSRValue": "0x10800",
1247        "Offcore": "1",
1248        "SampleAfterValue": "100003",
1249        "UMask": "0x1"
1250    },
1251    {
1252        "BriefDescription": "Split locks in SQ",
1253        "Counter": "0,1,2,3",
1254        "CounterHTOff": "0,1,2,3,4,5,6,7",
1255        "EventCode": "0xF4",
1256        "EventName": "SQ_MISC.SPLIT_LOCK",
1257        "SampleAfterValue": "100003",
1258        "UMask": "0x10"
1259    }
1260]