1[
2    {
3        "EventCode": "0xC3",
4        "Counter": "0,1",
5        "UMask": "0x2",
6        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
7        "SampleAfterValue": "200003",
8        "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards"
9    },
10    {
11        "EventCode": "0xB7",
12        "MSRValue": "0x0100400070",
13        "Counter": "0,1",
14        "UMask": "0x1",
15        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
16        "MSRIndex": "0x1a6,0x1a7",
17        "SampleAfterValue": "100007",
18        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
19        "Offcore": "1"
20    },
21    {
22        "EventCode": "0xB7",
23        "MSRValue": "0x0080200070",
24        "Counter": "0,1",
25        "UMask": "0x1",
26        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
27        "MSRIndex": "0x1a6,0x1a7",
28        "SampleAfterValue": "100007",
29        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",
30        "Offcore": "1"
31    },
32    {
33        "EventCode": "0xB7",
34        "MSRValue": "0x0101000070",
35        "Counter": "0,1",
36        "UMask": "0x1",
37        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
38        "MSRIndex": "0x1a6,0x1a7",
39        "SampleAfterValue": "100007",
40        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
41        "Offcore": "1"
42    },
43    {
44        "EventCode": "0xB7",
45        "MSRValue": "0x0080800070",
46        "Counter": "0,1",
47        "UMask": "0x1",
48        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
49        "MSRIndex": "0x1a6,0x1a7",
50        "SampleAfterValue": "100007",
51        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
52        "Offcore": "1"
53    },
54    {
55        "EventCode": "0xB7",
56        "MSRValue": "0x01004032f7",
57        "Counter": "0,1",
58        "UMask": "0x1",
59        "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
60        "MSRIndex": "0x1a6,0x1a7",
61        "SampleAfterValue": "100007",
62        "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
63        "Offcore": "1"
64    },
65    {
66        "EventCode": "0xB7",
67        "MSRValue": "0x00802032f7",
68        "Counter": "0,1",
69        "UMask": "0x1",
70        "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
71        "MSRIndex": "0x1a6,0x1a7",
72        "SampleAfterValue": "100007",
73        "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Local.",
74        "Offcore": "1"
75    },
76    {
77        "EventCode": "0xB7",
78        "MSRValue": "0x01010032f7",
79        "Counter": "0,1",
80        "UMask": "0x1",
81        "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
82        "MSRIndex": "0x1a6,0x1a7",
83        "SampleAfterValue": "100007",
84        "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Far.",
85        "Offcore": "1"
86    },
87    {
88        "EventCode": "0xB7",
89        "MSRValue": "0x00808032f7",
90        "Counter": "0,1",
91        "UMask": "0x1",
92        "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
93        "MSRIndex": "0x1a6,0x1a7",
94        "SampleAfterValue": "100007",
95        "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Local.",
96        "Offcore": "1"
97    },
98    {
99        "EventCode": "0xB7",
100        "MSRValue": "0x0100400044",
101        "Counter": "0,1",
102        "UMask": "0x1",
103        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
104        "MSRIndex": "0x1a6,0x1a7",
105        "SampleAfterValue": "100007",
106        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
107        "Offcore": "1"
108    },
109    {
110        "EventCode": "0xB7",
111        "MSRValue": "0x0080200044",
112        "Counter": "0,1",
113        "UMask": "0x1",
114        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
115        "MSRIndex": "0x1a6,0x1a7",
116        "SampleAfterValue": "100007",
117        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Local.",
118        "Offcore": "1"
119    },
120    {
121        "EventCode": "0xB7",
122        "MSRValue": "0x0101000044",
123        "Counter": "0,1",
124        "UMask": "0x1",
125        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
126        "MSRIndex": "0x1a6,0x1a7",
127        "SampleAfterValue": "100007",
128        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Far.",
129        "Offcore": "1"
130    },
131    {
132        "EventCode": "0xB7",
133        "MSRValue": "0x0080800044",
134        "Counter": "0,1",
135        "UMask": "0x1",
136        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
137        "MSRIndex": "0x1a6,0x1a7",
138        "SampleAfterValue": "100007",
139        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Local.",
140        "Offcore": "1"
141    },
142    {
143        "EventCode": "0xB7",
144        "MSRValue": "0x0100400022",
145        "Counter": "0,1",
146        "UMask": "0x1",
147        "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
148        "MSRIndex": "0x1a6,0x1a7",
149        "SampleAfterValue": "100007",
150        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
151        "Offcore": "1"
152    },
153    {
154        "EventCode": "0xB7",
155        "MSRValue": "0x0080200022",
156        "Counter": "0,1",
157        "UMask": "0x1",
158        "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
159        "MSRIndex": "0x1a6,0x1a7",
160        "SampleAfterValue": "100007",
161        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Local.",
162        "Offcore": "1"
163    },
164    {
165        "EventCode": "0xB7",
166        "MSRValue": "0x0101000022",
167        "Counter": "0,1",
168        "UMask": "0x1",
169        "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
170        "MSRIndex": "0x1a6,0x1a7",
171        "SampleAfterValue": "100007",
172        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Far.",
173        "Offcore": "1"
174    },
175    {
176        "EventCode": "0xB7",
177        "MSRValue": "0x0080800022",
178        "Counter": "0,1",
179        "UMask": "0x1",
180        "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
181        "MSRIndex": "0x1a6,0x1a7",
182        "SampleAfterValue": "100007",
183        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Local.",
184        "Offcore": "1"
185    },
186    {
187        "EventCode": "0xB7",
188        "MSRValue": "0x0100403091",
189        "Counter": "0,1",
190        "UMask": "0x1",
191        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
192        "MSRIndex": "0x1a6,0x1a7",
193        "SampleAfterValue": "100007",
194        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
195        "Offcore": "1"
196    },
197    {
198        "EventCode": "0xB7",
199        "MSRValue": "0x0080203091",
200        "Counter": "0,1",
201        "UMask": "0x1",
202        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
203        "MSRIndex": "0x1a6,0x1a7",
204        "SampleAfterValue": "100007",
205        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Local.",
206        "Offcore": "1"
207    },
208    {
209        "EventCode": "0xB7",
210        "MSRValue": "0x0101003091",
211        "Counter": "0,1",
212        "UMask": "0x1",
213        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
214        "MSRIndex": "0x1a6,0x1a7",
215        "SampleAfterValue": "100007",
216        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Far.",
217        "Offcore": "1"
218    },
219    {
220        "EventCode": "0xB7",
221        "MSRValue": "0x0080803091",
222        "Counter": "0,1",
223        "UMask": "0x1",
224        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
225        "MSRIndex": "0x1a6,0x1a7",
226        "SampleAfterValue": "100007",
227        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Local.",
228        "Offcore": "1"
229    },
230    {
231        "EventCode": "0xB7",
232        "MSRValue": "0x0100408000",
233        "Counter": "0,1",
234        "UMask": "0x1",
235        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
236        "MSRIndex": "0x1a6,0x1a7",
237        "SampleAfterValue": "100007",
238        "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
239        "Offcore": "1"
240    },
241    {
242        "EventCode": "0xB7",
243        "MSRValue": "0x0080208000",
244        "Counter": "0,1",
245        "UMask": "0x1",
246        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
247        "MSRIndex": "0x1a6,0x1a7",
248        "SampleAfterValue": "100007",
249        "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",
250        "Offcore": "1"
251    },
252    {
253        "EventCode": "0xB7",
254        "MSRValue": "0x0101008000",
255        "Counter": "0,1",
256        "UMask": "0x1",
257        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
258        "MSRIndex": "0x1a6,0x1a7",
259        "SampleAfterValue": "100007",
260        "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",
261        "Offcore": "1"
262    },
263    {
264        "EventCode": "0xB7",
265        "MSRValue": "0x0080808000",
266        "Counter": "0,1",
267        "UMask": "0x1",
268        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
269        "MSRIndex": "0x1a6,0x1a7",
270        "SampleAfterValue": "100007",
271        "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",
272        "Offcore": "1"
273    },
274    {
275        "EventCode": "0xB7",
276        "MSRValue": "0x0100402000",
277        "Counter": "0,1",
278        "UMask": "0x1",
279        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
280        "MSRIndex": "0x1a6,0x1a7",
281        "SampleAfterValue": "100007",
282        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
283        "Offcore": "1"
284    },
285    {
286        "EventCode": "0xB7",
287        "MSRValue": "0x0080202000",
288        "Counter": "0,1",
289        "UMask": "0x1",
290        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
291        "MSRIndex": "0x1a6,0x1a7",
292        "SampleAfterValue": "100007",
293        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",
294        "Offcore": "1"
295    },
296    {
297        "EventCode": "0xB7",
298        "MSRValue": "0x0101002000",
299        "Counter": "0,1",
300        "UMask": "0x1",
301        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
302        "MSRIndex": "0x1a6,0x1a7",
303        "SampleAfterValue": "100007",
304        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",
305        "Offcore": "1"
306    },
307    {
308        "EventCode": "0xB7",
309        "MSRValue": "0x0080802000",
310        "Counter": "0,1",
311        "UMask": "0x1",
312        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
313        "MSRIndex": "0x1a6,0x1a7",
314        "SampleAfterValue": "100007",
315        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",
316        "Offcore": "1"
317    },
318    {
319        "EventCode": "0xB7",
320        "MSRValue": "0x0100401000",
321        "Counter": "0,1",
322        "UMask": "0x1",
323        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
324        "MSRIndex": "0x1a6,0x1a7",
325        "SampleAfterValue": "100007",
326        "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
327        "Offcore": "1"
328    },
329    {
330        "EventCode": "0xB7",
331        "MSRValue": "0x0080201000",
332        "Counter": "0,1",
333        "UMask": "0x1",
334        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
335        "MSRIndex": "0x1a6,0x1a7",
336        "SampleAfterValue": "100007",
337        "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",
338        "Offcore": "1"
339    },
340    {
341        "EventCode": "0xB7",
342        "MSRValue": "0x0101001000",
343        "Counter": "0,1",
344        "UMask": "0x1",
345        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
346        "MSRIndex": "0x1a6,0x1a7",
347        "SampleAfterValue": "100007",
348        "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",
349        "Offcore": "1"
350    },
351    {
352        "EventCode": "0xB7",
353        "MSRValue": "0x0080801000",
354        "Counter": "0,1",
355        "UMask": "0x1",
356        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
357        "MSRIndex": "0x1a6,0x1a7",
358        "SampleAfterValue": "100007",
359        "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",
360        "Offcore": "1"
361    },
362    {
363        "EventCode": "0xB7",
364        "MSRValue": "0x0100400400",
365        "Counter": "0,1",
366        "UMask": "0x1",
367        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
368        "MSRIndex": "0x1a6,0x1a7",
369        "SampleAfterValue": "100007",
370        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
371        "Offcore": "1"
372    },
373    {
374        "EventCode": "0xB7",
375        "MSRValue": "0x0080200400",
376        "Counter": "0,1",
377        "UMask": "0x1",
378        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
379        "MSRIndex": "0x1a6,0x1a7",
380        "SampleAfterValue": "100007",
381        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",
382        "Offcore": "1"
383    },
384    {
385        "EventCode": "0xB7",
386        "MSRValue": "0x0101000400",
387        "Counter": "0,1",
388        "UMask": "0x1",
389        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
390        "MSRIndex": "0x1a6,0x1a7",
391        "SampleAfterValue": "100007",
392        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",
393        "Offcore": "1"
394    },
395    {
396        "EventCode": "0xB7",
397        "MSRValue": "0x0080800400",
398        "Counter": "0,1",
399        "UMask": "0x1",
400        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
401        "MSRIndex": "0x1a6,0x1a7",
402        "SampleAfterValue": "100007",
403        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",
404        "Offcore": "1"
405    },
406    {
407        "EventCode": "0xB7",
408        "MSRValue": "0x0100400200",
409        "Counter": "0,1",
410        "UMask": "0x1",
411        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
412        "MSRIndex": "0x1a6,0x1a7",
413        "SampleAfterValue": "100007",
414        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
415        "Offcore": "1"
416    },
417    {
418        "EventCode": "0xB7",
419        "MSRValue": "0x0080200200",
420        "Counter": "0,1",
421        "UMask": "0x1",
422        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
423        "MSRIndex": "0x1a6,0x1a7",
424        "SampleAfterValue": "100007",
425        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Local.",
426        "Offcore": "1"
427    },
428    {
429        "EventCode": "0xB7",
430        "MSRValue": "0x0101000200",
431        "Counter": "0,1",
432        "UMask": "0x1",
433        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
434        "MSRIndex": "0x1a6,0x1a7",
435        "SampleAfterValue": "100007",
436        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Far.",
437        "Offcore": "1"
438    },
439    {
440        "EventCode": "0xB7",
441        "MSRValue": "0x0080800200",
442        "Counter": "0,1",
443        "UMask": "0x1",
444        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
445        "MSRIndex": "0x1a6,0x1a7",
446        "SampleAfterValue": "100007",
447        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Local.",
448        "Offcore": "1"
449    },
450    {
451        "EventCode": "0xB7",
452        "MSRValue": "0x0100400100",
453        "Counter": "0,1",
454        "UMask": "0x1",
455        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
456        "MSRIndex": "0x1a7",
457        "SampleAfterValue": "100007",
458        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
459        "Offcore": "1"
460    },
461    {
462        "EventCode": "0xB7",
463        "MSRValue": "0x0080200100",
464        "Counter": "0,1",
465        "UMask": "0x1",
466        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
467        "MSRIndex": "0x1a7",
468        "SampleAfterValue": "100007",
469        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",
470        "Offcore": "1"
471    },
472    {
473        "EventCode": "0xB7",
474        "MSRValue": "0x0101000100",
475        "Counter": "0,1",
476        "UMask": "0x1",
477        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
478        "MSRIndex": "0x1a7",
479        "SampleAfterValue": "100007",
480        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",
481        "Offcore": "1"
482    },
483    {
484        "EventCode": "0xB7",
485        "MSRValue": "0x0080800100",
486        "Counter": "0,1",
487        "UMask": "0x1",
488        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
489        "MSRIndex": "0x1a7",
490        "SampleAfterValue": "100007",
491        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",
492        "Offcore": "1"
493    },
494    {
495        "EventCode": "0xB7",
496        "MSRValue": "0x2000020080",
497        "Counter": "0,1",
498        "UMask": "0x1",
499        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
500        "MSRIndex": "0x1a6,0x1a7",
501        "SampleAfterValue": "100007",
502        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
503        "Offcore": "1"
504    },
505    {
506        "EventCode": "0xB7",
507        "MSRValue": "0x0100400080",
508        "Counter": "0,1",
509        "UMask": "0x1",
510        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
511        "MSRIndex": "0x1a6,0x1a7",
512        "SampleAfterValue": "100007",
513        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
514        "Offcore": "1"
515    },
516    {
517        "EventCode": "0xB7",
518        "MSRValue": "0x0080200080",
519        "Counter": "0,1",
520        "UMask": "0x1",
521        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
522        "MSRIndex": "0x1a6,0x1a7",
523        "SampleAfterValue": "100007",
524        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Local.",
525        "Offcore": "1"
526    },
527    {
528        "EventCode": "0xB7",
529        "MSRValue": "0x0101000080",
530        "Counter": "0,1",
531        "UMask": "0x1",
532        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
533        "MSRIndex": "0x1a6,0x1a7",
534        "SampleAfterValue": "100007",
535        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Far.",
536        "Offcore": "1"
537    },
538    {
539        "EventCode": "0xB7",
540        "MSRValue": "0x0080800080",
541        "Counter": "0,1",
542        "UMask": "0x1",
543        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
544        "MSRIndex": "0x1a6,0x1a7",
545        "SampleAfterValue": "100007",
546        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Local.",
547        "Offcore": "1"
548    },
549    {
550        "EventCode": "0xB7",
551        "MSRValue": "0x0100400040",
552        "Counter": "0,1",
553        "UMask": "0x1",
554        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
555        "MSRIndex": "0x1a6,0x1a7",
556        "SampleAfterValue": "100007",
557        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
558        "Offcore": "1"
559    },
560    {
561        "EventCode": "0xB7",
562        "MSRValue": "0x0080200040",
563        "Counter": "0,1",
564        "UMask": "0x1",
565        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
566        "MSRIndex": "0x1a6,0x1a7",
567        "SampleAfterValue": "100007",
568        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",
569        "Offcore": "1"
570    },
571    {
572        "EventCode": "0xB7",
573        "MSRValue": "0x0101000040",
574        "Counter": "0,1",
575        "UMask": "0x1",
576        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
577        "MSRIndex": "0x1a6,0x1a7",
578        "SampleAfterValue": "100007",
579        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",
580        "Offcore": "1"
581    },
582    {
583        "EventCode": "0xB7",
584        "MSRValue": "0x0080800040",
585        "Counter": "0,1",
586        "UMask": "0x1",
587        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
588        "MSRIndex": "0x1a6,0x1a7",
589        "SampleAfterValue": "100007",
590        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",
591        "Offcore": "1"
592    },
593    {
594        "EventCode": "0xB7",
595        "MSRValue": "0x2000020020",
596        "Counter": "0,1",
597        "UMask": "0x1",
598        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
599        "MSRIndex": "0x1a6,0x1a7",
600        "SampleAfterValue": "100007",
601        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
602        "Offcore": "1"
603    },
604    {
605        "EventCode": "0xB7",
606        "MSRValue": "0x0100400020",
607        "Counter": "0,1",
608        "UMask": "0x1",
609        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
610        "MSRIndex": "0x1a6,0x1a7",
611        "SampleAfterValue": "100007",
612        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
613        "Offcore": "1"
614    },
615    {
616        "EventCode": "0xB7",
617        "MSRValue": "0x0080200020",
618        "Counter": "0,1",
619        "UMask": "0x1",
620        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
621        "MSRIndex": "0x1a6,0x1a7",
622        "SampleAfterValue": "100007",
623        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",
624        "Offcore": "1"
625    },
626    {
627        "EventCode": "0xB7",
628        "MSRValue": "0x0101000020",
629        "Counter": "0,1",
630        "UMask": "0x1",
631        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
632        "MSRIndex": "0x1a6,0x1a7",
633        "SampleAfterValue": "100007",
634        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",
635        "Offcore": "1"
636    },
637    {
638        "EventCode": "0xB7",
639        "MSRValue": "0x0080800020",
640        "Counter": "0,1",
641        "UMask": "0x1",
642        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
643        "MSRIndex": "0x1a6,0x1a7",
644        "SampleAfterValue": "100007",
645        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",
646        "Offcore": "1"
647    },
648    {
649        "EventCode": "0xB7",
650        "MSRValue": "0x0100400004",
651        "Counter": "0,1",
652        "UMask": "0x1",
653        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
654        "MSRIndex": "0x1a6,0x1a7",
655        "SampleAfterValue": "100007",
656        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
657        "Offcore": "1"
658    },
659    {
660        "EventCode": "0xB7",
661        "MSRValue": "0x0080200004",
662        "Counter": "0,1",
663        "UMask": "0x1",
664        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
665        "MSRIndex": "0x1a6,0x1a7",
666        "SampleAfterValue": "100007",
667        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",
668        "Offcore": "1"
669    },
670    {
671        "EventCode": "0xB7",
672        "MSRValue": "0x0101000004",
673        "Counter": "0,1",
674        "UMask": "0x1",
675        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
676        "MSRIndex": "0x1a6,0x1a7",
677        "SampleAfterValue": "100007",
678        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",
679        "Offcore": "1"
680    },
681    {
682        "EventCode": "0xB7",
683        "MSRValue": "0x0080800004",
684        "Counter": "0,1",
685        "UMask": "0x1",
686        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
687        "MSRIndex": "0x1a6,0x1a7",
688        "SampleAfterValue": "100007",
689        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",
690        "Offcore": "1"
691    },
692    {
693        "EventCode": "0xB7",
694        "MSRValue": "0x0100400002",
695        "Counter": "0,1",
696        "UMask": "0x1",
697        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
698        "MSRIndex": "0x1a6,0x1a7",
699        "SampleAfterValue": "100007",
700        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
701        "Offcore": "1"
702    },
703    {
704        "EventCode": "0xB7",
705        "MSRValue": "0x0080200002",
706        "Counter": "0,1",
707        "UMask": "0x1",
708        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
709        "MSRIndex": "0x1a6,0x1a7",
710        "SampleAfterValue": "100007",
711        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",
712        "Offcore": "1"
713    },
714    {
715        "EventCode": "0xB7",
716        "MSRValue": "0x0101000002",
717        "Counter": "0,1",
718        "UMask": "0x1",
719        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
720        "MSRIndex": "0x1a6,0x1a7",
721        "SampleAfterValue": "100007",
722        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",
723        "Offcore": "1"
724    },
725    {
726        "EventCode": "0xB7",
727        "MSRValue": "0x0080800002",
728        "Counter": "0,1",
729        "UMask": "0x1",
730        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
731        "MSRIndex": "0x1a6,0x1a7",
732        "SampleAfterValue": "100007",
733        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",
734        "Offcore": "1"
735    },
736    {
737        "EventCode": "0xB7",
738        "MSRValue": "0x0100400001",
739        "Counter": "0,1",
740        "UMask": "0x1",
741        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
742        "MSRIndex": "0x1a6,0x1a7",
743        "SampleAfterValue": "100007",
744        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
745        "Offcore": "1"
746    },
747    {
748        "EventCode": "0xB7",
749        "MSRValue": "0x0080200001",
750        "Counter": "0,1",
751        "UMask": "0x1",
752        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
753        "MSRIndex": "0x1a6,0x1a7",
754        "SampleAfterValue": "100007",
755        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",
756        "Offcore": "1"
757    },
758    {
759        "EventCode": "0xB7",
760        "MSRValue": "0x0101000001",
761        "Counter": "0,1",
762        "UMask": "0x1",
763        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
764        "MSRIndex": "0x1a6,0x1a7",
765        "SampleAfterValue": "100007",
766        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",
767        "Offcore": "1"
768    },
769    {
770        "EventCode": "0xB7",
771        "MSRValue": "0x0080800001",
772        "Counter": "0,1",
773        "UMask": "0x1",
774        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
775        "MSRIndex": "0x1a6,0x1a7",
776        "SampleAfterValue": "100007",
777        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",
778        "Offcore": "1"
779    },
780    {
781        "EventCode": "0xB7",
782        "MSRValue": "0x0180600001",
783        "Counter": "0,1",
784        "UMask": "0x1",
785        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
786        "MSRIndex": "0x1a6,0x1a7",
787        "SampleAfterValue": "100007",
788        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",
789        "Offcore": "1"
790    },
791    {
792        "EventCode": "0xB7",
793        "MSRValue": "0x0180600002",
794        "Counter": "0,1",
795        "UMask": "0x1",
796        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
797        "MSRIndex": "0x1a6,0x1a7",
798        "SampleAfterValue": "100007",
799        "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",
800        "Offcore": "1"
801    },
802    {
803        "EventCode": "0xB7",
804        "MSRValue": "0x0180600004",
805        "Counter": "0,1",
806        "UMask": "0x1",
807        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
808        "MSRIndex": "0x1a6,0x1a7",
809        "SampleAfterValue": "100007",
810        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",
811        "Offcore": "1"
812    },
813    {
814        "EventCode": "0xB7",
815        "MSRValue": "0x0180600020",
816        "Counter": "0,1",
817        "UMask": "0x1",
818        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
819        "MSRIndex": "0x1a6,0x1a7",
820        "SampleAfterValue": "100007",
821        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",
822        "Offcore": "1"
823    },
824    {
825        "EventCode": "0xB7",
826        "MSRValue": "0x0180600080",
827        "Counter": "0,1",
828        "UMask": "0x1",
829        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
830        "MSRIndex": "0x1a6,0x1a7",
831        "SampleAfterValue": "100007",
832        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from MCDRAM (local and far)",
833        "Offcore": "1"
834    },
835    {
836        "EventCode": "0xB7",
837        "MSRValue": "0x0180600100",
838        "Counter": "0,1",
839        "UMask": "0x1",
840        "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
841        "MSRIndex": "0x1a7",
842        "SampleAfterValue": "100007",
843        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",
844        "Offcore": "1"
845    },
846    {
847        "EventCode": "0xB7",
848        "MSRValue": "0x0180600200",
849        "Counter": "0,1",
850        "UMask": "0x1",
851        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
852        "MSRIndex": "0x1a6,0x1a7",
853        "SampleAfterValue": "100007",
854        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from MCDRAM (local and far)",
855        "Offcore": "1"
856    },
857    {
858        "EventCode": "0xB7",
859        "MSRValue": "0x0180600400",
860        "Counter": "0,1",
861        "UMask": "0x1",
862        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
863        "MSRIndex": "0x1a6,0x1a7",
864        "SampleAfterValue": "100007",
865        "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",
866        "Offcore": "1"
867    },
868    {
869        "EventCode": "0xB7",
870        "MSRValue": "0x0180601000",
871        "Counter": "0,1",
872        "UMask": "0x1",
873        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
874        "MSRIndex": "0x1a6,0x1a7",
875        "SampleAfterValue": "100007",
876        "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",
877        "Offcore": "1"
878    },
879    {
880        "EventCode": "0xB7",
881        "MSRValue": "0x0180608000",
882        "Counter": "0,1",
883        "UMask": "0x1",
884        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
885        "MSRIndex": "0x1a6,0x1a7",
886        "SampleAfterValue": "100007",
887        "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",
888        "Offcore": "1"
889    },
890    {
891        "EventCode": "0xB7",
892        "MSRValue": "0x0180603091",
893        "Counter": "0,1",
894        "UMask": "0x1",
895        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
896        "MSRIndex": "0x1a6,0x1a7",
897        "SampleAfterValue": "100007",
898        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from MCDRAM (local and far)",
899        "Offcore": "1"
900    },
901    {
902        "EventCode": "0xB7",
903        "MSRValue": "0x0180600022",
904        "Counter": "0,1",
905        "UMask": "0x1",
906        "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
907        "MSRIndex": "0x1a6,0x1a7",
908        "SampleAfterValue": "100007",
909        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from MCDRAM (local and far)",
910        "Offcore": "1"
911    },
912    {
913        "EventCode": "0xB7",
914        "MSRValue": "0x0180600044",
915        "Counter": "0,1",
916        "UMask": "0x1",
917        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
918        "MSRIndex": "0x1a6,0x1a7",
919        "SampleAfterValue": "100007",
920        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from MCDRAM (local and far)",
921        "Offcore": "1"
922    },
923    {
924        "EventCode": "0xB7",
925        "MSRValue": "0x01806032f7",
926        "Counter": "0,1",
927        "UMask": "0x1",
928        "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
929        "MSRIndex": "0x1a6,0x1a7",
930        "SampleAfterValue": "100007",
931        "BriefDescription": "Counts any Read request  that accounts for responses from MCDRAM (local and far)",
932        "Offcore": "1"
933    },
934    {
935        "EventCode": "0xB7",
936        "MSRValue": "0x0180600070",
937        "Counter": "0,1",
938        "UMask": "0x1",
939        "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
940        "MSRIndex": "0x1a6,0x1a7",
941        "SampleAfterValue": "100007",
942        "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",
943        "Offcore": "1"
944    },
945    {
946        "EventCode": "0xB7",
947        "MSRValue": "0x0181800001",
948        "Counter": "0,1",
949        "UMask": "0x1",
950        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
951        "MSRIndex": "0x1a6,0x1a7",
952        "SampleAfterValue": "100007",
953        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
954        "Offcore": "1"
955    },
956    {
957        "EventCode": "0xB7",
958        "MSRValue": "0x0181800002",
959        "Counter": "0,1",
960        "UMask": "0x1",
961        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
962        "MSRIndex": "0x1a6,0x1a7",
963        "SampleAfterValue": "100007",
964        "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
965        "Offcore": "1"
966    },
967    {
968        "EventCode": "0xB7",
969        "MSRValue": "0x0181800004",
970        "Counter": "0,1",
971        "UMask": "0x1",
972        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
973        "MSRIndex": "0x1a6,0x1a7",
974        "SampleAfterValue": "100007",
975        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
976        "Offcore": "1"
977    },
978    {
979        "EventCode": "0xB7",
980        "MSRValue": "0x0181800020",
981        "Counter": "0,1",
982        "UMask": "0x1",
983        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
984        "MSRIndex": "0x1a6,0x1a7",
985        "SampleAfterValue": "100007",
986        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
987        "Offcore": "1"
988    },
989    {
990        "EventCode": "0xB7",
991        "MSRValue": "0x0181800040",
992        "Counter": "0,1",
993        "UMask": "0x1",
994        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
995        "MSRIndex": "0x1a6,0x1a7",
996        "SampleAfterValue": "100007",
997        "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",
998        "Offcore": "1"
999    },
1000    {
1001        "EventCode": "0xB7",
1002        "MSRValue": "0x0181800080",
1003        "Counter": "0,1",
1004        "UMask": "0x1",
1005        "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
1006        "MSRIndex": "0x1a6,0x1a7",
1007        "SampleAfterValue": "100007",
1008        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for responses from DDR (local and far)",
1009        "Offcore": "1"
1010    },
1011    {
1012        "EventCode": "0xB7",
1013        "MSRValue": "0x0181800200",
1014        "Counter": "0,1",
1015        "UMask": "0x1",
1016        "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
1017        "MSRIndex": "0x1a6,0x1a7",
1018        "SampleAfterValue": "100007",
1019        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for responses from DDR (local and far)",
1020        "Offcore": "1"
1021    },
1022    {
1023        "EventCode": "0xB7",
1024        "MSRValue": "0x0181800400",
1025        "Counter": "0,1",
1026        "UMask": "0x1",
1027        "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
1028        "MSRIndex": "0x1a6,0x1a7",
1029        "SampleAfterValue": "100007",
1030        "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",
1031        "Offcore": "1"
1032    },
1033    {
1034        "EventCode": "0xB7",
1035        "MSRValue": "0x0181801000",
1036        "Counter": "0,1",
1037        "UMask": "0x1",
1038        "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
1039        "MSRIndex": "0x1a6,0x1a7",
1040        "SampleAfterValue": "100007",
1041        "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",
1042        "Offcore": "1"
1043    },
1044    {
1045        "EventCode": "0xB7",
1046        "MSRValue": "0x0181802000",
1047        "Counter": "0,1",
1048        "UMask": "0x1",
1049        "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
1050        "MSRIndex": "0x1a6,0x1a7",
1051        "SampleAfterValue": "100007",
1052        "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",
1053        "Offcore": "1"
1054    },
1055    {
1056        "EventCode": "0xB7",
1057        "MSRValue": "0x0181808000",
1058        "Counter": "0,1",
1059        "UMask": "0x1",
1060        "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
1061        "MSRIndex": "0x1a6,0x1a7",
1062        "SampleAfterValue": "100007",
1063        "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
1064        "Offcore": "1"
1065    },
1066    {
1067        "EventCode": "0xB7",
1068        "MSRValue": "0x0181803091",
1069        "Counter": "0,1",
1070        "UMask": "0x1",
1071        "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
1072        "MSRIndex": "0x1a6,0x1a7",
1073        "SampleAfterValue": "100007",
1074        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for responses from DDR (local and far)",
1075        "Offcore": "1"
1076    },
1077    {
1078        "EventCode": "0xB7",
1079        "MSRValue": "0x0181800022",
1080        "Counter": "0,1",
1081        "UMask": "0x1",
1082        "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
1083        "MSRIndex": "0x1a6,0x1a7",
1084        "SampleAfterValue": "100007",
1085        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for responses from DDR (local and far)",
1086        "Offcore": "1"
1087    },
1088    {
1089        "EventCode": "0xB7",
1090        "MSRValue": "0x0181800044",
1091        "Counter": "0,1",
1092        "UMask": "0x1",
1093        "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
1094        "MSRIndex": "0x1a6,0x1a7",
1095        "SampleAfterValue": "100007",
1096        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for responses from DDR (local and far)",
1097        "Offcore": "1"
1098    },
1099    {
1100        "EventCode": "0xB7",
1101        "MSRValue": "0x01818032f7",
1102        "Counter": "0,1",
1103        "UMask": "0x1",
1104        "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
1105        "MSRIndex": "0x1a6,0x1a7",
1106        "SampleAfterValue": "100007",
1107        "BriefDescription": "Counts any Read request  that accounts for responses from DDR (local and far)",
1108        "Offcore": "1"
1109    }
1110]