1[
2    {
3        "BriefDescription": "ddr bandwidth read (CPU traffic only) (MB/sec). ",
4        "Counter": "0,1,2,3",
5        "EventCode": "0x03",
6        "EventName": "UNC_M_CAS_COUNT.RD",
7        "PerPkg": "1",
8        "ScaleUnit": "6.4e-05MiB",
9        "UMask": "0x01",
10        "Unit": "imc"
11    },
12    {
13        "BriefDescription": "ddr bandwidth write (CPU traffic only) (MB/sec). ",
14        "Counter": "0,1,2,3",
15        "EventCode": "0x03",
16        "EventName": "UNC_M_CAS_COUNT.WR",
17        "PerPkg": "1",
18        "ScaleUnit": "6.4e-05MiB",
19        "UMask": "0x02",
20        "Unit": "imc"
21    },
22    {
23        "BriefDescription": "mcdram bandwidth read (CPU traffic only) (MB/sec). ",
24        "Counter": "0,1,2,3",
25        "EventCode": "0x01",
26        "EventName": "UNC_E_RPQ_INSERTS",
27        "PerPkg": "1",
28        "ScaleUnit": "6.4e-05MiB",
29        "UMask": "0x01",
30        "Unit": "edc_eclk"
31    },
32    {
33        "BriefDescription": "mcdram bandwidth write (CPU traffic only) (MB/sec). ",
34        "Counter": "0,1,2,3",
35        "EventCode": "0x02",
36        "EventName": "UNC_E_WPQ_INSERTS",
37        "PerPkg": "1",
38        "ScaleUnit": "6.4e-05MiB",
39        "UMask": "0x01",
40        "Unit": "edc_eclk"
41    }
42]
43