1[
2    {
3        "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
4        "Counter": "0,1,2,3",
5        "CounterHTOff": "0,1,2,3,4,5,6,7",
6        "CounterMask": "2",
7        "EventCode": "0xA3",
8        "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
9        "SampleAfterValue": "2000003",
10        "UMask": "0x2"
11    },
12    {
13        "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
14        "Counter": "0,1,2,3",
15        "CounterHTOff": "0,1,2,3,4,5,6,7",
16        "CounterMask": "6",
17        "EventCode": "0xA3",
18        "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
19        "SampleAfterValue": "2000003",
20        "UMask": "0x6"
21    },
22    {
23        "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
24        "Counter": "0,1,2,3",
25        "CounterHTOff": "0,1,2,3,4,5,6,7",
26        "EventCode": "0xC8",
27        "EventName": "HLE_RETIRED.ABORTED",
28        "PEBS": "1",
29        "PublicDescription": "Number of times HLE abort was triggered.",
30        "SampleAfterValue": "2000003",
31        "UMask": "0x4"
32    },
33    {
34        "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
35        "Counter": "0,1,2,3",
36        "CounterHTOff": "0,1,2,3,4,5,6,7",
37        "EventCode": "0xC8",
38        "EventName": "HLE_RETIRED.ABORTED_EVENTS",
39        "SampleAfterValue": "2000003",
40        "UMask": "0x80"
41    },
42    {
43        "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
44        "Counter": "0,1,2,3",
45        "CounterHTOff": "0,1,2,3,4,5,6,7",
46        "EventCode": "0xC8",
47        "EventName": "HLE_RETIRED.ABORTED_MEM",
48        "SampleAfterValue": "2000003",
49        "UMask": "0x8"
50    },
51    {
52        "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
53        "Counter": "0,1,2,3",
54        "CounterHTOff": "0,1,2,3,4,5,6,7",
55        "EventCode": "0xC8",
56        "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
57        "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
58        "SampleAfterValue": "2000003",
59        "UMask": "0x40"
60    },
61    {
62        "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
63        "Counter": "0,1,2,3",
64        "CounterHTOff": "0,1,2,3,4,5,6,7",
65        "EventCode": "0xC8",
66        "EventName": "HLE_RETIRED.ABORTED_TIMER",
67        "SampleAfterValue": "2000003",
68        "UMask": "0x10"
69    },
70    {
71        "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
72        "Counter": "0,1,2,3",
73        "CounterHTOff": "0,1,2,3,4,5,6,7",
74        "EventCode": "0xC8",
75        "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
76        "SampleAfterValue": "2000003",
77        "UMask": "0x20"
78    },
79    {
80        "BriefDescription": "Number of times an HLE execution successfully committed",
81        "Counter": "0,1,2,3",
82        "CounterHTOff": "0,1,2,3,4,5,6,7",
83        "EventCode": "0xC8",
84        "EventName": "HLE_RETIRED.COMMIT",
85        "PublicDescription": "Number of times HLE commit succeeded.",
86        "SampleAfterValue": "2000003",
87        "UMask": "0x2"
88    },
89    {
90        "BriefDescription": "Number of times an HLE execution started.",
91        "Counter": "0,1,2,3",
92        "CounterHTOff": "0,1,2,3,4,5,6,7",
93        "EventCode": "0xC8",
94        "EventName": "HLE_RETIRED.START",
95        "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
96        "SampleAfterValue": "2000003",
97        "UMask": "0x1"
98    },
99    {
100        "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
101        "Counter": "0,1,2,3",
102        "CounterHTOff": "0,1,2,3,4,5,6,7",
103        "Errata": "SKL089",
104        "EventCode": "0xC3",
105        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
106        "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
107        "SampleAfterValue": "100003",
108        "UMask": "0x2"
109    },
110    {
111        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
112        "Counter": "0,1,2,3",
113        "CounterHTOff": "0,1,2,3",
114        "Data_LA": "1",
115        "EventCode": "0xcd",
116        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
117        "MSRIndex": "0x3F6",
118        "MSRValue": "0x80",
119        "PEBS": "2",
120        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
121        "SampleAfterValue": "1009",
122        "TakenAlone": "1",
123        "UMask": "0x1"
124    },
125    {
126        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
127        "Counter": "0,1,2,3",
128        "CounterHTOff": "0,1,2,3",
129        "Data_LA": "1",
130        "EventCode": "0xcd",
131        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
132        "MSRIndex": "0x3F6",
133        "MSRValue": "0x10",
134        "PEBS": "2",
135        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
136        "SampleAfterValue": "20011",
137        "TakenAlone": "1",
138        "UMask": "0x1"
139    },
140    {
141        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
142        "Counter": "0,1,2,3",
143        "CounterHTOff": "0,1,2,3",
144        "Data_LA": "1",
145        "EventCode": "0xcd",
146        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
147        "MSRIndex": "0x3F6",
148        "MSRValue": "0x100",
149        "PEBS": "2",
150        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
151        "SampleAfterValue": "503",
152        "TakenAlone": "1",
153        "UMask": "0x1"
154    },
155    {
156        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
157        "Counter": "0,1,2,3",
158        "CounterHTOff": "0,1,2,3",
159        "Data_LA": "1",
160        "EventCode": "0xcd",
161        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
162        "MSRIndex": "0x3F6",
163        "MSRValue": "0x20",
164        "PEBS": "2",
165        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
166        "SampleAfterValue": "100007",
167        "TakenAlone": "1",
168        "UMask": "0x1"
169    },
170    {
171        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
172        "Counter": "0,1,2,3",
173        "CounterHTOff": "0,1,2,3",
174        "Data_LA": "1",
175        "EventCode": "0xcd",
176        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
177        "MSRIndex": "0x3F6",
178        "MSRValue": "0x4",
179        "PEBS": "2",
180        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
181        "SampleAfterValue": "100003",
182        "TakenAlone": "1",
183        "UMask": "0x1"
184    },
185    {
186        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
187        "Counter": "0,1,2,3",
188        "CounterHTOff": "0,1,2,3",
189        "Data_LA": "1",
190        "EventCode": "0xcd",
191        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
192        "MSRIndex": "0x3F6",
193        "MSRValue": "0x200",
194        "PEBS": "2",
195        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
196        "SampleAfterValue": "101",
197        "TakenAlone": "1",
198        "UMask": "0x1"
199    },
200    {
201        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
202        "Counter": "0,1,2,3",
203        "CounterHTOff": "0,1,2,3",
204        "Data_LA": "1",
205        "EventCode": "0xcd",
206        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
207        "MSRIndex": "0x3F6",
208        "MSRValue": "0x40",
209        "PEBS": "2",
210        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
211        "SampleAfterValue": "2003",
212        "TakenAlone": "1",
213        "UMask": "0x1"
214    },
215    {
216        "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
217        "Counter": "0,1,2,3",
218        "CounterHTOff": "0,1,2,3",
219        "Data_LA": "1",
220        "EventCode": "0xcd",
221        "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
222        "MSRIndex": "0x3F6",
223        "MSRValue": "0x8",
224        "PEBS": "2",
225        "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
226        "SampleAfterValue": "50021",
227        "TakenAlone": "1",
228        "UMask": "0x1"
229    },
230    {
231        "BriefDescription": "Demand Data Read requests who miss L3 cache",
232        "Counter": "0,1,2,3",
233        "CounterHTOff": "0,1,2,3,4,5,6,7",
234        "EventCode": "0xB0",
235        "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
236        "PublicDescription": "Demand Data Read requests who miss L3 cache.",
237        "SampleAfterValue": "100003",
238        "UMask": "0x10"
239    },
240    {
241        "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
242        "Counter": "0,1,2,3",
243        "CounterHTOff": "0,1,2,3,4,5,6,7",
244        "CounterMask": "1",
245        "EventCode": "0x60",
246        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
247        "SampleAfterValue": "2000003",
248        "UMask": "0x10"
249    },
250    {
251        "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
252        "Counter": "0,1,2,3",
253        "CounterHTOff": "0,1,2,3,4,5,6,7",
254        "EventCode": "0x60",
255        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
256        "SampleAfterValue": "2000003",
257        "UMask": "0x10"
258    },
259    {
260        "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
261        "Counter": "0,1,2,3",
262        "CounterHTOff": "0,1,2,3,4,5,6,7",
263        "CounterMask": "6",
264        "EventCode": "0x60",
265        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
266        "SampleAfterValue": "2000003",
267        "UMask": "0x10"
268    },
269    {
270        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3.",
271        "Counter": "0,1,2,3",
272        "CounterHTOff": "0,1,2,3",
273        "EventCode": "0xB7, 0xBB",
274        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
275        "MSRIndex": "0x1a6,0x1a7",
276        "MSRValue": "0x3FBC000491",
277        "Offcore": "1",
278        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
279        "SampleAfterValue": "100003",
280        "UMask": "0x1"
281    },
282    {
283        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
284        "Counter": "0,1,2,3",
285        "CounterHTOff": "0,1,2,3",
286        "EventCode": "0xB7, 0xBB",
287        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
288        "MSRIndex": "0x1a6,0x1a7",
289        "MSRValue": "0x103FC00491",
290        "Offcore": "1",
291        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
292        "SampleAfterValue": "100003",
293        "UMask": "0x1"
294    },
295    {
296        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
297        "Counter": "0,1,2,3",
298        "CounterHTOff": "0,1,2,3",
299        "EventCode": "0xB7, 0xBB",
300        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
301        "MSRIndex": "0x1a6,0x1a7",
302        "MSRValue": "0x083FC00491",
303        "Offcore": "1",
304        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
305        "SampleAfterValue": "100003",
306        "UMask": "0x1"
307    },
308    {
309        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
310        "Counter": "0,1,2,3",
311        "CounterHTOff": "0,1,2,3",
312        "EventCode": "0xB7, 0xBB",
313        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
314        "MSRIndex": "0x1a6,0x1a7",
315        "MSRValue": "0x063FC00491",
316        "Offcore": "1",
317        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
318        "SampleAfterValue": "100003",
319        "UMask": "0x1"
320    },
321    {
322        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram.",
323        "Counter": "0,1,2,3",
324        "CounterHTOff": "0,1,2,3",
325        "EventCode": "0xB7, 0xBB",
326        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
327        "MSRIndex": "0x1a6,0x1a7",
328        "MSRValue": "0x0604000491",
329        "Offcore": "1",
330        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
331        "SampleAfterValue": "100003",
332        "UMask": "0x1"
333    },
334    {
335        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from remote dram.",
336        "Counter": "0,1,2,3",
337        "CounterHTOff": "0,1,2,3",
338        "EventCode": "0xB7, 0xBB",
339        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
340        "MSRIndex": "0x1a6,0x1a7",
341        "MSRValue": "0x063B800491",
342        "Offcore": "1",
343        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
344        "SampleAfterValue": "100003",
345        "UMask": "0x1"
346    },
347    {
348        "BriefDescription": "Counts all prefetch data reads that miss in the L3.",
349        "Counter": "0,1,2,3",
350        "CounterHTOff": "0,1,2,3",
351        "EventCode": "0xB7, 0xBB",
352        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
353        "MSRIndex": "0x1a6,0x1a7",
354        "MSRValue": "0x3FBC000490",
355        "Offcore": "1",
356        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
357        "SampleAfterValue": "100003",
358        "UMask": "0x1"
359    },
360    {
361        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the modified data is transferred from remote cache.",
362        "Counter": "0,1,2,3",
363        "CounterHTOff": "0,1,2,3",
364        "EventCode": "0xB7, 0xBB",
365        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
366        "MSRIndex": "0x1a6,0x1a7",
367        "MSRValue": "0x103FC00490",
368        "Offcore": "1",
369        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
370        "SampleAfterValue": "100003",
371        "UMask": "0x1"
372    },
373    {
374        "BriefDescription": "Counts all prefetch data reads that miss the L3 and clean or shared data is transferred from remote cache.",
375        "Counter": "0,1,2,3",
376        "CounterHTOff": "0,1,2,3",
377        "EventCode": "0xB7, 0xBB",
378        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
379        "MSRIndex": "0x1a6,0x1a7",
380        "MSRValue": "0x083FC00490",
381        "Offcore": "1",
382        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
383        "SampleAfterValue": "100003",
384        "UMask": "0x1"
385    },
386    {
387        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local or remote dram.",
388        "Counter": "0,1,2,3",
389        "CounterHTOff": "0,1,2,3",
390        "EventCode": "0xB7, 0xBB",
391        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
392        "MSRIndex": "0x1a6,0x1a7",
393        "MSRValue": "0x063FC00490",
394        "Offcore": "1",
395        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
396        "SampleAfterValue": "100003",
397        "UMask": "0x1"
398    },
399    {
400        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from local dram.",
401        "Counter": "0,1,2,3",
402        "CounterHTOff": "0,1,2,3",
403        "EventCode": "0xB7, 0xBB",
404        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
405        "MSRIndex": "0x1a6,0x1a7",
406        "MSRValue": "0x0604000490",
407        "Offcore": "1",
408        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
409        "SampleAfterValue": "100003",
410        "UMask": "0x1"
411    },
412    {
413        "BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from remote dram.",
414        "Counter": "0,1,2,3",
415        "CounterHTOff": "0,1,2,3",
416        "EventCode": "0xB7, 0xBB",
417        "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
418        "MSRIndex": "0x1a6,0x1a7",
419        "MSRValue": "0x063B800490",
420        "Offcore": "1",
421        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
422        "SampleAfterValue": "100003",
423        "UMask": "0x1"
424    },
425    {
426        "BriefDescription": "Counts prefetch RFOs that miss in the L3.",
427        "Counter": "0,1,2,3",
428        "CounterHTOff": "0,1,2,3",
429        "EventCode": "0xB7, 0xBB",
430        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
431        "MSRIndex": "0x1a6,0x1a7",
432        "MSRValue": "0x3FBC000120",
433        "Offcore": "1",
434        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
435        "SampleAfterValue": "100003",
436        "UMask": "0x1"
437    },
438    {
439        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
440        "Counter": "0,1,2,3",
441        "CounterHTOff": "0,1,2,3",
442        "EventCode": "0xB7, 0xBB",
443        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
444        "MSRIndex": "0x1a6,0x1a7",
445        "MSRValue": "0x103FC00120",
446        "Offcore": "1",
447        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
448        "SampleAfterValue": "100003",
449        "UMask": "0x1"
450    },
451    {
452        "BriefDescription": "Counts prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
453        "Counter": "0,1,2,3",
454        "CounterHTOff": "0,1,2,3",
455        "EventCode": "0xB7, 0xBB",
456        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
457        "MSRIndex": "0x1a6,0x1a7",
458        "MSRValue": "0x083FC00120",
459        "Offcore": "1",
460        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
461        "SampleAfterValue": "100003",
462        "UMask": "0x1"
463    },
464    {
465        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
466        "Counter": "0,1,2,3",
467        "CounterHTOff": "0,1,2,3",
468        "EventCode": "0xB7, 0xBB",
469        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
470        "MSRIndex": "0x1a6,0x1a7",
471        "MSRValue": "0x063FC00120",
472        "Offcore": "1",
473        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
474        "SampleAfterValue": "100003",
475        "UMask": "0x1"
476    },
477    {
478        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from local dram.",
479        "Counter": "0,1,2,3",
480        "CounterHTOff": "0,1,2,3",
481        "EventCode": "0xB7, 0xBB",
482        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
483        "MSRIndex": "0x1a6,0x1a7",
484        "MSRValue": "0x0604000120",
485        "Offcore": "1",
486        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
487        "SampleAfterValue": "100003",
488        "UMask": "0x1"
489    },
490    {
491        "BriefDescription": "Counts prefetch RFOs that miss the L3 and the data is returned from remote dram.",
492        "Counter": "0,1,2,3",
493        "CounterHTOff": "0,1,2,3",
494        "EventCode": "0xB7, 0xBB",
495        "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
496        "MSRIndex": "0x1a6,0x1a7",
497        "MSRValue": "0x063B800120",
498        "Offcore": "1",
499        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
500        "SampleAfterValue": "100003",
501        "UMask": "0x1"
502    },
503    {
504        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3.",
505        "Counter": "0,1,2,3",
506        "CounterHTOff": "0,1,2,3",
507        "EventCode": "0xB7, 0xBB",
508        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
509        "MSRIndex": "0x1a6,0x1a7",
510        "MSRValue": "0x3FBC000122",
511        "Offcore": "1",
512        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
513        "SampleAfterValue": "100003",
514        "UMask": "0x1"
515    },
516    {
517        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the modified data is transferred from remote cache.",
518        "Counter": "0,1,2,3",
519        "CounterHTOff": "0,1,2,3",
520        "EventCode": "0xB7, 0xBB",
521        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
522        "MSRIndex": "0x1a6,0x1a7",
523        "MSRValue": "0x103FC00122",
524        "Offcore": "1",
525        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
526        "SampleAfterValue": "100003",
527        "UMask": "0x1"
528    },
529    {
530        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
531        "Counter": "0,1,2,3",
532        "CounterHTOff": "0,1,2,3",
533        "EventCode": "0xB7, 0xBB",
534        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
535        "MSRIndex": "0x1a6,0x1a7",
536        "MSRValue": "0x083FC00122",
537        "Offcore": "1",
538        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
539        "SampleAfterValue": "100003",
540        "UMask": "0x1"
541    },
542    {
543        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local or remote dram.",
544        "Counter": "0,1,2,3",
545        "CounterHTOff": "0,1,2,3",
546        "EventCode": "0xB7, 0xBB",
547        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
548        "MSRIndex": "0x1a6,0x1a7",
549        "MSRValue": "0x063FC00122",
550        "Offcore": "1",
551        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
552        "SampleAfterValue": "100003",
553        "UMask": "0x1"
554    },
555    {
556        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram.",
557        "Counter": "0,1,2,3",
558        "CounterHTOff": "0,1,2,3",
559        "EventCode": "0xB7, 0xBB",
560        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
561        "MSRIndex": "0x1a6,0x1a7",
562        "MSRValue": "0x0604000122",
563        "Offcore": "1",
564        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
565        "SampleAfterValue": "100003",
566        "UMask": "0x1"
567    },
568    {
569        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from remote dram.",
570        "Counter": "0,1,2,3",
571        "CounterHTOff": "0,1,2,3",
572        "EventCode": "0xB7, 0xBB",
573        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
574        "MSRIndex": "0x1a6,0x1a7",
575        "MSRValue": "0x063B800122",
576        "Offcore": "1",
577        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
578        "SampleAfterValue": "100003",
579        "UMask": "0x1"
580    },
581    {
582        "BriefDescription": "Counts all demand code reads that miss in the L3.",
583        "Counter": "0,1,2,3",
584        "CounterHTOff": "0,1,2,3",
585        "EventCode": "0xB7, 0xBB",
586        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
587        "MSRIndex": "0x1a6,0x1a7",
588        "MSRValue": "0x3FBC000004",
589        "Offcore": "1",
590        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
591        "SampleAfterValue": "100003",
592        "UMask": "0x1"
593    },
594    {
595        "BriefDescription": "Counts all demand code reads that miss the L3 and the modified data is transferred from remote cache.",
596        "Counter": "0,1,2,3",
597        "CounterHTOff": "0,1,2,3",
598        "EventCode": "0xB7, 0xBB",
599        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
600        "MSRIndex": "0x1a6,0x1a7",
601        "MSRValue": "0x103FC00004",
602        "Offcore": "1",
603        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
604        "SampleAfterValue": "100003",
605        "UMask": "0x1"
606    },
607    {
608        "BriefDescription": "Counts all demand code reads that miss the L3 and clean or shared data is transferred from remote cache.",
609        "Counter": "0,1,2,3",
610        "CounterHTOff": "0,1,2,3",
611        "EventCode": "0xB7, 0xBB",
612        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
613        "MSRIndex": "0x1a6,0x1a7",
614        "MSRValue": "0x083FC00004",
615        "Offcore": "1",
616        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
617        "SampleAfterValue": "100003",
618        "UMask": "0x1"
619    },
620    {
621        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local or remote dram.",
622        "Counter": "0,1,2,3",
623        "CounterHTOff": "0,1,2,3",
624        "EventCode": "0xB7, 0xBB",
625        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
626        "MSRIndex": "0x1a6,0x1a7",
627        "MSRValue": "0x063FC00004",
628        "Offcore": "1",
629        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
630        "SampleAfterValue": "100003",
631        "UMask": "0x1"
632    },
633    {
634        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram.",
635        "Counter": "0,1,2,3",
636        "CounterHTOff": "0,1,2,3",
637        "EventCode": "0xB7, 0xBB",
638        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
639        "MSRIndex": "0x1a6,0x1a7",
640        "MSRValue": "0x0604000004",
641        "Offcore": "1",
642        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
643        "SampleAfterValue": "100003",
644        "UMask": "0x1"
645    },
646    {
647        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from remote dram.",
648        "Counter": "0,1,2,3",
649        "CounterHTOff": "0,1,2,3",
650        "EventCode": "0xB7, 0xBB",
651        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
652        "MSRIndex": "0x1a6,0x1a7",
653        "MSRValue": "0x063B800004",
654        "Offcore": "1",
655        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
656        "SampleAfterValue": "100003",
657        "UMask": "0x1"
658    },
659    {
660        "BriefDescription": "Counts demand data reads that miss in the L3.",
661        "Counter": "0,1,2,3",
662        "CounterHTOff": "0,1,2,3",
663        "EventCode": "0xB7, 0xBB",
664        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
665        "MSRIndex": "0x1a6,0x1a7",
666        "MSRValue": "0x3FBC000001",
667        "Offcore": "1",
668        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
669        "SampleAfterValue": "100003",
670        "UMask": "0x1"
671    },
672    {
673        "BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferred from remote cache.",
674        "Counter": "0,1,2,3",
675        "CounterHTOff": "0,1,2,3",
676        "EventCode": "0xB7, 0xBB",
677        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
678        "MSRIndex": "0x1a6,0x1a7",
679        "MSRValue": "0x103FC00001",
680        "Offcore": "1",
681        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
682        "SampleAfterValue": "100003",
683        "UMask": "0x1"
684    },
685    {
686        "BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transferred from remote cache.",
687        "Counter": "0,1,2,3",
688        "CounterHTOff": "0,1,2,3",
689        "EventCode": "0xB7, 0xBB",
690        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
691        "MSRIndex": "0x1a6,0x1a7",
692        "MSRValue": "0x083FC00001",
693        "Offcore": "1",
694        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
695        "SampleAfterValue": "100003",
696        "UMask": "0x1"
697    },
698    {
699        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local or remote dram.",
700        "Counter": "0,1,2,3",
701        "CounterHTOff": "0,1,2,3",
702        "EventCode": "0xB7, 0xBB",
703        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
704        "MSRIndex": "0x1a6,0x1a7",
705        "MSRValue": "0x063FC00001",
706        "Offcore": "1",
707        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
708        "SampleAfterValue": "100003",
709        "UMask": "0x1"
710    },
711    {
712        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram.",
713        "Counter": "0,1,2,3",
714        "CounterHTOff": "0,1,2,3",
715        "EventCode": "0xB7, 0xBB",
716        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
717        "MSRIndex": "0x1a6,0x1a7",
718        "MSRValue": "0x0604000001",
719        "Offcore": "1",
720        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
721        "SampleAfterValue": "100003",
722        "UMask": "0x1"
723    },
724    {
725        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from remote dram.",
726        "Counter": "0,1,2,3",
727        "CounterHTOff": "0,1,2,3",
728        "EventCode": "0xB7, 0xBB",
729        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
730        "MSRIndex": "0x1a6,0x1a7",
731        "MSRValue": "0x063B800001",
732        "Offcore": "1",
733        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
734        "SampleAfterValue": "100003",
735        "UMask": "0x1"
736    },
737    {
738        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3.",
739        "Counter": "0,1,2,3",
740        "CounterHTOff": "0,1,2,3",
741        "EventCode": "0xB7, 0xBB",
742        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
743        "MSRIndex": "0x1a6,0x1a7",
744        "MSRValue": "0x3FBC000002",
745        "Offcore": "1",
746        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
747        "SampleAfterValue": "100003",
748        "UMask": "0x1"
749    },
750    {
751        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data is transferred from remote cache.",
752        "Counter": "0,1,2,3",
753        "CounterHTOff": "0,1,2,3",
754        "EventCode": "0xB7, 0xBB",
755        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
756        "MSRIndex": "0x1a6,0x1a7",
757        "MSRValue": "0x103FC00002",
758        "Offcore": "1",
759        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
760        "SampleAfterValue": "100003",
761        "UMask": "0x1"
762    },
763    {
764        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and clean or shared data is transferred from remote cache.",
765        "Counter": "0,1,2,3",
766        "CounterHTOff": "0,1,2,3",
767        "EventCode": "0xB7, 0xBB",
768        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
769        "MSRIndex": "0x1a6,0x1a7",
770        "MSRValue": "0x083FC00002",
771        "Offcore": "1",
772        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
773        "SampleAfterValue": "100003",
774        "UMask": "0x1"
775    },
776    {
777        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local or remote dram.",
778        "Counter": "0,1,2,3",
779        "CounterHTOff": "0,1,2,3",
780        "EventCode": "0xB7, 0xBB",
781        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
782        "MSRIndex": "0x1a6,0x1a7",
783        "MSRValue": "0x063FC00002",
784        "Offcore": "1",
785        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
786        "SampleAfterValue": "100003",
787        "UMask": "0x1"
788    },
789    {
790        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram.",
791        "Counter": "0,1,2,3",
792        "CounterHTOff": "0,1,2,3",
793        "EventCode": "0xB7, 0xBB",
794        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
795        "MSRIndex": "0x1a6,0x1a7",
796        "MSRValue": "0x0604000002",
797        "Offcore": "1",
798        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
799        "SampleAfterValue": "100003",
800        "UMask": "0x1"
801    },
802    {
803        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from remote dram.",
804        "Counter": "0,1,2,3",
805        "CounterHTOff": "0,1,2,3",
806        "EventCode": "0xB7, 0xBB",
807        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
808        "MSRIndex": "0x1a6,0x1a7",
809        "MSRValue": "0x063B800002",
810        "Offcore": "1",
811        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
812        "SampleAfterValue": "100003",
813        "UMask": "0x1"
814    },
815    {
816        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss in the L3.",
817        "Counter": "0,1,2,3",
818        "CounterHTOff": "0,1,2,3",
819        "EventCode": "0xB7, 0xBB",
820        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
821        "MSRIndex": "0x1a6,0x1a7",
822        "MSRValue": "0x3FBC000400",
823        "Offcore": "1",
824        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
825        "SampleAfterValue": "100003",
826        "UMask": "0x1"
827    },
828    {
829        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the modified data is transferred from remote cache.",
830        "Counter": "0,1,2,3",
831        "CounterHTOff": "0,1,2,3",
832        "EventCode": "0xB7, 0xBB",
833        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
834        "MSRIndex": "0x1a6,0x1a7",
835        "MSRValue": "0x103FC00400",
836        "Offcore": "1",
837        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
838        "SampleAfterValue": "100003",
839        "UMask": "0x1"
840    },
841    {
842        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and clean or shared data is transferred from remote cache.",
843        "Counter": "0,1,2,3",
844        "CounterHTOff": "0,1,2,3",
845        "EventCode": "0xB7, 0xBB",
846        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
847        "MSRIndex": "0x1a6,0x1a7",
848        "MSRValue": "0x083FC00400",
849        "Offcore": "1",
850        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
851        "SampleAfterValue": "100003",
852        "UMask": "0x1"
853    },
854    {
855        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local or remote dram.",
856        "Counter": "0,1,2,3",
857        "CounterHTOff": "0,1,2,3",
858        "EventCode": "0xB7, 0xBB",
859        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD",
860        "MSRIndex": "0x1a6,0x1a7",
861        "MSRValue": "0x063FC00400",
862        "Offcore": "1",
863        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
864        "SampleAfterValue": "100003",
865        "UMask": "0x1"
866    },
867    {
868        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from local dram.",
869        "Counter": "0,1,2,3",
870        "CounterHTOff": "0,1,2,3",
871        "EventCode": "0xB7, 0xBB",
872        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
873        "MSRIndex": "0x1a6,0x1a7",
874        "MSRValue": "0x0604000400",
875        "Offcore": "1",
876        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
877        "SampleAfterValue": "100003",
878        "UMask": "0x1"
879    },
880    {
881        "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests that miss the L3 and the data is returned from remote dram.",
882        "Counter": "0,1,2,3",
883        "CounterHTOff": "0,1,2,3",
884        "EventCode": "0xB7, 0xBB",
885        "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
886        "MSRIndex": "0x1a6,0x1a7",
887        "MSRValue": "0x063B800400",
888        "Offcore": "1",
889        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
890        "SampleAfterValue": "100003",
891        "UMask": "0x1"
892    },
893    {
894        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3.",
895        "Counter": "0,1,2,3",
896        "CounterHTOff": "0,1,2,3",
897        "EventCode": "0xB7, 0xBB",
898        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
899        "MSRIndex": "0x1a6,0x1a7",
900        "MSRValue": "0x3FBC000010",
901        "Offcore": "1",
902        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
903        "SampleAfterValue": "100003",
904        "UMask": "0x1"
905    },
906    {
907        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the modified data is transferred from remote cache.",
908        "Counter": "0,1,2,3",
909        "CounterHTOff": "0,1,2,3",
910        "EventCode": "0xB7, 0xBB",
911        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
912        "MSRIndex": "0x1a6,0x1a7",
913        "MSRValue": "0x103FC00010",
914        "Offcore": "1",
915        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
916        "SampleAfterValue": "100003",
917        "UMask": "0x1"
918    },
919    {
920        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
921        "Counter": "0,1,2,3",
922        "CounterHTOff": "0,1,2,3",
923        "EventCode": "0xB7, 0xBB",
924        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
925        "MSRIndex": "0x1a6,0x1a7",
926        "MSRValue": "0x083FC00010",
927        "Offcore": "1",
928        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
929        "SampleAfterValue": "100003",
930        "UMask": "0x1"
931    },
932    {
933        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local or remote dram.",
934        "Counter": "0,1,2,3",
935        "CounterHTOff": "0,1,2,3",
936        "EventCode": "0xB7, 0xBB",
937        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
938        "MSRIndex": "0x1a6,0x1a7",
939        "MSRValue": "0x063FC00010",
940        "Offcore": "1",
941        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
942        "SampleAfterValue": "100003",
943        "UMask": "0x1"
944    },
945    {
946        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from local dram.",
947        "Counter": "0,1,2,3",
948        "CounterHTOff": "0,1,2,3",
949        "EventCode": "0xB7, 0xBB",
950        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
951        "MSRIndex": "0x1a6,0x1a7",
952        "MSRValue": "0x0604000010",
953        "Offcore": "1",
954        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
955        "SampleAfterValue": "100003",
956        "UMask": "0x1"
957    },
958    {
959        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the L3 and the data is returned from remote dram.",
960        "Counter": "0,1,2,3",
961        "CounterHTOff": "0,1,2,3",
962        "EventCode": "0xB7, 0xBB",
963        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
964        "MSRIndex": "0x1a6,0x1a7",
965        "MSRValue": "0x063B800010",
966        "Offcore": "1",
967        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
968        "SampleAfterValue": "100003",
969        "UMask": "0x1"
970    },
971    {
972        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3.",
973        "Counter": "0,1,2,3",
974        "CounterHTOff": "0,1,2,3",
975        "EventCode": "0xB7, 0xBB",
976        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
977        "MSRIndex": "0x1a6,0x1a7",
978        "MSRValue": "0x3FBC000020",
979        "Offcore": "1",
980        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
981        "SampleAfterValue": "100003",
982        "UMask": "0x1"
983    },
984    {
985        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the modified data is transferred from remote cache.",
986        "Counter": "0,1,2,3",
987        "CounterHTOff": "0,1,2,3",
988        "EventCode": "0xB7, 0xBB",
989        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
990        "MSRIndex": "0x1a6,0x1a7",
991        "MSRValue": "0x103FC00020",
992        "Offcore": "1",
993        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
994        "SampleAfterValue": "100003",
995        "UMask": "0x1"
996    },
997    {
998        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
999        "Counter": "0,1,2,3",
1000        "CounterHTOff": "0,1,2,3",
1001        "EventCode": "0xB7, 0xBB",
1002        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
1003        "MSRIndex": "0x1a6,0x1a7",
1004        "MSRValue": "0x083FC00020",
1005        "Offcore": "1",
1006        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1007        "SampleAfterValue": "100003",
1008        "UMask": "0x1"
1009    },
1010    {
1011        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local or remote dram.",
1012        "Counter": "0,1,2,3",
1013        "CounterHTOff": "0,1,2,3",
1014        "EventCode": "0xB7, 0xBB",
1015        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1016        "MSRIndex": "0x1a6,0x1a7",
1017        "MSRValue": "0x063FC00020",
1018        "Offcore": "1",
1019        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1020        "SampleAfterValue": "100003",
1021        "UMask": "0x1"
1022    },
1023    {
1024        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from local dram.",
1025        "Counter": "0,1,2,3",
1026        "CounterHTOff": "0,1,2,3",
1027        "EventCode": "0xB7, 0xBB",
1028        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1029        "MSRIndex": "0x1a6,0x1a7",
1030        "MSRValue": "0x0604000020",
1031        "Offcore": "1",
1032        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1033        "SampleAfterValue": "100003",
1034        "UMask": "0x1"
1035    },
1036    {
1037        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the data is returned from remote dram.",
1038        "Counter": "0,1,2,3",
1039        "CounterHTOff": "0,1,2,3",
1040        "EventCode": "0xB7, 0xBB",
1041        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1042        "MSRIndex": "0x1a6,0x1a7",
1043        "MSRValue": "0x063B800020",
1044        "Offcore": "1",
1045        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1046        "SampleAfterValue": "100003",
1047        "UMask": "0x1"
1048    },
1049    {
1050        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3.",
1051        "Counter": "0,1,2,3",
1052        "CounterHTOff": "0,1,2,3",
1053        "EventCode": "0xB7, 0xBB",
1054        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
1055        "MSRIndex": "0x1a6,0x1a7",
1056        "MSRValue": "0x3FBC000080",
1057        "Offcore": "1",
1058        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1059        "SampleAfterValue": "100003",
1060        "UMask": "0x1"
1061    },
1062    {
1063        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the modified data is transferred from remote cache.",
1064        "Counter": "0,1,2,3",
1065        "CounterHTOff": "0,1,2,3",
1066        "EventCode": "0xB7, 0xBB",
1067        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
1068        "MSRIndex": "0x1a6,0x1a7",
1069        "MSRValue": "0x103FC00080",
1070        "Offcore": "1",
1071        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1072        "SampleAfterValue": "100003",
1073        "UMask": "0x1"
1074    },
1075    {
1076        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and clean or shared data is transferred from remote cache.",
1077        "Counter": "0,1,2,3",
1078        "CounterHTOff": "0,1,2,3",
1079        "EventCode": "0xB7, 0xBB",
1080        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
1081        "MSRIndex": "0x1a6,0x1a7",
1082        "MSRValue": "0x083FC00080",
1083        "Offcore": "1",
1084        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1085        "SampleAfterValue": "100003",
1086        "UMask": "0x1"
1087    },
1088    {
1089        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local or remote dram.",
1090        "Counter": "0,1,2,3",
1091        "CounterHTOff": "0,1,2,3",
1092        "EventCode": "0xB7, 0xBB",
1093        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1094        "MSRIndex": "0x1a6,0x1a7",
1095        "MSRValue": "0x063FC00080",
1096        "Offcore": "1",
1097        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1098        "SampleAfterValue": "100003",
1099        "UMask": "0x1"
1100    },
1101    {
1102        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from local dram.",
1103        "Counter": "0,1,2,3",
1104        "CounterHTOff": "0,1,2,3",
1105        "EventCode": "0xB7, 0xBB",
1106        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1107        "MSRIndex": "0x1a6,0x1a7",
1108        "MSRValue": "0x0604000080",
1109        "Offcore": "1",
1110        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1111        "SampleAfterValue": "100003",
1112        "UMask": "0x1"
1113    },
1114    {
1115        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the L3 and the data is returned from remote dram.",
1116        "Counter": "0,1,2,3",
1117        "CounterHTOff": "0,1,2,3",
1118        "EventCode": "0xB7, 0xBB",
1119        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1120        "MSRIndex": "0x1a6,0x1a7",
1121        "MSRValue": "0x063B800080",
1122        "Offcore": "1",
1123        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1124        "SampleAfterValue": "100003",
1125        "UMask": "0x1"
1126    },
1127    {
1128        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss in the L3.",
1129        "Counter": "0,1,2,3",
1130        "CounterHTOff": "0,1,2,3",
1131        "EventCode": "0xB7, 0xBB",
1132        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
1133        "MSRIndex": "0x1a6,0x1a7",
1134        "MSRValue": "0x3FBC000100",
1135        "Offcore": "1",
1136        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1137        "SampleAfterValue": "100003",
1138        "UMask": "0x1"
1139    },
1140    {
1141        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the modified data is transferred from remote cache.",
1142        "Counter": "0,1,2,3",
1143        "CounterHTOff": "0,1,2,3",
1144        "EventCode": "0xB7, 0xBB",
1145        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
1146        "MSRIndex": "0x1a6,0x1a7",
1147        "MSRValue": "0x103FC00100",
1148        "Offcore": "1",
1149        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1150        "SampleAfterValue": "100003",
1151        "UMask": "0x1"
1152    },
1153    {
1154        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and clean or shared data is transferred from remote cache.",
1155        "Counter": "0,1,2,3",
1156        "CounterHTOff": "0,1,2,3",
1157        "EventCode": "0xB7, 0xBB",
1158        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
1159        "MSRIndex": "0x1a6,0x1a7",
1160        "MSRValue": "0x083FC00100",
1161        "Offcore": "1",
1162        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1163        "SampleAfterValue": "100003",
1164        "UMask": "0x1"
1165    },
1166    {
1167        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local or remote dram.",
1168        "Counter": "0,1,2,3",
1169        "CounterHTOff": "0,1,2,3",
1170        "EventCode": "0xB7, 0xBB",
1171        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD",
1172        "MSRIndex": "0x1a6,0x1a7",
1173        "MSRValue": "0x063FC00100",
1174        "Offcore": "1",
1175        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1176        "SampleAfterValue": "100003",
1177        "UMask": "0x1"
1178    },
1179    {
1180        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from local dram.",
1181        "Counter": "0,1,2,3",
1182        "CounterHTOff": "0,1,2,3",
1183        "EventCode": "0xB7, 0xBB",
1184        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
1185        "MSRIndex": "0x1a6,0x1a7",
1186        "MSRValue": "0x0604000100",
1187        "Offcore": "1",
1188        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1189        "SampleAfterValue": "100003",
1190        "UMask": "0x1"
1191    },
1192    {
1193        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the L3 and the data is returned from remote dram.",
1194        "Counter": "0,1,2,3",
1195        "CounterHTOff": "0,1,2,3",
1196        "EventCode": "0xB7, 0xBB",
1197        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
1198        "MSRIndex": "0x1a6,0x1a7",
1199        "MSRValue": "0x063B800100",
1200        "Offcore": "1",
1201        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
1202        "SampleAfterValue": "100003",
1203        "UMask": "0x1"
1204    },
1205    {
1206        "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
1207        "Counter": "0,1,2,3",
1208        "CounterHTOff": "0,1,2,3,4,5,6,7",
1209        "EventCode": "0xC9",
1210        "EventName": "RTM_RETIRED.ABORTED",
1211        "PEBS": "1",
1212        "PublicDescription": "Number of times RTM abort was triggered.",
1213        "SampleAfterValue": "2000003",
1214        "UMask": "0x4"
1215    },
1216    {
1217        "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
1218        "Counter": "0,1,2,3",
1219        "CounterHTOff": "0,1,2,3,4,5,6,7",
1220        "EventCode": "0xC9",
1221        "EventName": "RTM_RETIRED.ABORTED_EVENTS",
1222        "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
1223        "SampleAfterValue": "2000003",
1224        "UMask": "0x80"
1225    },
1226    {
1227        "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
1228        "Counter": "0,1,2,3",
1229        "CounterHTOff": "0,1,2,3,4,5,6,7",
1230        "EventCode": "0xC9",
1231        "EventName": "RTM_RETIRED.ABORTED_MEM",
1232        "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
1233        "SampleAfterValue": "2000003",
1234        "UMask": "0x8"
1235    },
1236    {
1237        "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
1238        "Counter": "0,1,2,3",
1239        "CounterHTOff": "0,1,2,3,4,5,6,7",
1240        "EventCode": "0xC9",
1241        "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
1242        "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
1243        "SampleAfterValue": "2000003",
1244        "UMask": "0x40"
1245    },
1246    {
1247        "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
1248        "Counter": "0,1,2,3",
1249        "CounterHTOff": "0,1,2,3,4,5,6,7",
1250        "EventCode": "0xC9",
1251        "EventName": "RTM_RETIRED.ABORTED_TIMER",
1252        "SampleAfterValue": "2000003",
1253        "UMask": "0x10"
1254    },
1255    {
1256        "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
1257        "Counter": "0,1,2,3",
1258        "CounterHTOff": "0,1,2,3,4,5,6,7",
1259        "EventCode": "0xC9",
1260        "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
1261        "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
1262        "SampleAfterValue": "2000003",
1263        "UMask": "0x20"
1264    },
1265    {
1266        "BriefDescription": "Number of times an RTM execution successfully committed",
1267        "Counter": "0,1,2,3",
1268        "CounterHTOff": "0,1,2,3,4,5,6,7",
1269        "EventCode": "0xC9",
1270        "EventName": "RTM_RETIRED.COMMIT",
1271        "PublicDescription": "Number of times RTM commit succeeded.",
1272        "SampleAfterValue": "2000003",
1273        "UMask": "0x2"
1274    },
1275    {
1276        "BriefDescription": "Number of times an RTM execution started.",
1277        "Counter": "0,1,2,3",
1278        "CounterHTOff": "0,1,2,3,4,5,6,7",
1279        "EventCode": "0xC9",
1280        "EventName": "RTM_RETIRED.START",
1281        "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
1282        "SampleAfterValue": "2000003",
1283        "UMask": "0x1"
1284    },
1285    {
1286        "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
1287        "Counter": "0,1,2,3",
1288        "CounterHTOff": "0,1,2,3,4,5,6,7",
1289        "EventCode": "0x5d",
1290        "EventName": "TX_EXEC.MISC1",
1291        "SampleAfterValue": "2000003",
1292        "UMask": "0x1"
1293    },
1294    {
1295        "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
1296        "Counter": "0,1,2,3",
1297        "CounterHTOff": "0,1,2,3,4,5,6,7",
1298        "EventCode": "0x5d",
1299        "EventName": "TX_EXEC.MISC2",
1300        "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
1301        "SampleAfterValue": "2000003",
1302        "UMask": "0x2"
1303    },
1304    {
1305        "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
1306        "Counter": "0,1,2,3",
1307        "CounterHTOff": "0,1,2,3,4,5,6,7",
1308        "EventCode": "0x5d",
1309        "EventName": "TX_EXEC.MISC3",
1310        "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
1311        "SampleAfterValue": "2000003",
1312        "UMask": "0x4"
1313    },
1314    {
1315        "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
1316        "Counter": "0,1,2,3",
1317        "CounterHTOff": "0,1,2,3,4,5,6,7",
1318        "EventCode": "0x5d",
1319        "EventName": "TX_EXEC.MISC4",
1320        "PublicDescription": "RTM region detected inside HLE.",
1321        "SampleAfterValue": "2000003",
1322        "UMask": "0x8"
1323    },
1324    {
1325        "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
1326        "Counter": "0,1,2,3",
1327        "CounterHTOff": "0,1,2,3,4,5,6,7",
1328        "EventCode": "0x5d",
1329        "EventName": "TX_EXEC.MISC5",
1330        "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
1331        "SampleAfterValue": "2000003",
1332        "UMask": "0x10"
1333    },
1334    {
1335        "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
1336        "Counter": "0,1,2,3",
1337        "CounterHTOff": "0,1,2,3,4,5,6,7",
1338        "EventCode": "0x54",
1339        "EventName": "TX_MEM.ABORT_CAPACITY",
1340        "SampleAfterValue": "2000003",
1341        "UMask": "0x2"
1342    },
1343    {
1344        "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
1345        "Counter": "0,1,2,3",
1346        "CounterHTOff": "0,1,2,3,4,5,6,7",
1347        "EventCode": "0x54",
1348        "EventName": "TX_MEM.ABORT_CONFLICT",
1349        "PublicDescription": "Number of times a TSX line had a cache conflict.",
1350        "SampleAfterValue": "2000003",
1351        "UMask": "0x1"
1352    },
1353    {
1354        "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
1355        "Counter": "0,1,2,3",
1356        "CounterHTOff": "0,1,2,3,4,5,6,7",
1357        "EventCode": "0x54",
1358        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
1359        "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
1360        "SampleAfterValue": "2000003",
1361        "UMask": "0x10"
1362    },
1363    {
1364        "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
1365        "Counter": "0,1,2,3",
1366        "CounterHTOff": "0,1,2,3,4,5,6,7",
1367        "EventCode": "0x54",
1368        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
1369        "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
1370        "SampleAfterValue": "2000003",
1371        "UMask": "0x8"
1372    },
1373    {
1374        "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
1375        "Counter": "0,1,2,3",
1376        "CounterHTOff": "0,1,2,3,4,5,6,7",
1377        "EventCode": "0x54",
1378        "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
1379        "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
1380        "SampleAfterValue": "2000003",
1381        "UMask": "0x20"
1382    },
1383    {
1384        "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
1385        "Counter": "0,1,2,3",
1386        "CounterHTOff": "0,1,2,3,4,5,6,7",
1387        "EventCode": "0x54",
1388        "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
1389        "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
1390        "SampleAfterValue": "2000003",
1391        "UMask": "0x4"
1392    },
1393    {
1394        "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
1395        "Counter": "0,1,2,3",
1396        "CounterHTOff": "0,1,2,3,4,5,6,7",
1397        "EventCode": "0x54",
1398        "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
1399        "PublicDescription": "Number of times we could not allocate Lock Buffer.",
1400        "SampleAfterValue": "2000003",
1401        "UMask": "0x40"
1402    }
1403]