1[
2    {
3        "BriefDescription": "Counts all microcode FP assists.",
4        "CollectPEBSRecord": "2",
5        "Counter": "0,1,2,3,4,5,6,7",
6        "EventCode": "0xc1",
7        "EventName": "ASSISTS.FP",
8        "PEBScounters": "0,1,2,3,4,5,6,7",
9        "PublicDescription": "Counts all microcode Floating Point assists.",
10        "SampleAfterValue": "100003",
11        "UMask": "0x2"
12    },
13    {
14        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
15        "CollectPEBSRecord": "2",
16        "Counter": "0,1,2,3,4,5,6,7",
17        "EventCode": "0xc7",
18        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
19        "PEBScounters": "0,1,2,3,4,5,6,7",
20        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
21        "SampleAfterValue": "100003",
22        "UMask": "0x4"
23    },
24    {
25        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
26        "CollectPEBSRecord": "2",
27        "Counter": "0,1,2,3,4,5,6,7",
28        "EventCode": "0xc7",
29        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
30        "PEBScounters": "0,1,2,3,4,5,6,7",
31        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
32        "SampleAfterValue": "100003",
33        "UMask": "0x8"
34    },
35    {
36        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
37        "CollectPEBSRecord": "2",
38        "Counter": "0,1,2,3,4,5,6,7",
39        "EventCode": "0xc7",
40        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
41        "PEBScounters": "0,1,2,3,4,5,6,7",
42        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
43        "SampleAfterValue": "100003",
44        "UMask": "0x10"
45    },
46    {
47        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
48        "CollectPEBSRecord": "2",
49        "Counter": "0,1,2,3,4,5,6,7",
50        "EventCode": "0xc7",
51        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
52        "PEBScounters": "0,1,2,3,4,5,6,7",
53        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
54        "SampleAfterValue": "100003",
55        "UMask": "0x20"
56    },
57    {
58        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
59        "CollectPEBSRecord": "2",
60        "Counter": "0,1,2,3,4,5,6,7",
61        "EventCode": "0xc7",
62        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
63        "PEBScounters": "0,1,2,3,4,5,6,7",
64        "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
65        "SampleAfterValue": "100003",
66        "UMask": "0x40"
67    },
68    {
69        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
70        "CollectPEBSRecord": "2",
71        "Counter": "0,1,2,3,4,5,6,7",
72        "EventCode": "0xc7",
73        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
74        "PEBScounters": "0,1,2,3,4,5,6,7",
75        "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
76        "SampleAfterValue": "100003",
77        "UMask": "0x80"
78    },
79    {
80        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
81        "CollectPEBSRecord": "2",
82        "Counter": "0,1,2,3,4,5,6,7",
83        "EventCode": "0xc7",
84        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
85        "PEBScounters": "0,1,2,3,4,5,6,7",
86        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
87        "SampleAfterValue": "100003",
88        "UMask": "0x1"
89    },
90    {
91        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
92        "CollectPEBSRecord": "2",
93        "Counter": "0,1,2,3,4,5,6,7",
94        "EventCode": "0xc7",
95        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
96        "PEBScounters": "0,1,2,3,4,5,6,7",
97        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
98        "SampleAfterValue": "100003",
99        "UMask": "0x2"
100    }
101]